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(IJCSIS) International Journal of Computer Science and Information Security, Vol. 8, No. 9, December 2010 A Survey on Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages B. Sathiyabama and Dr. S. Malarkkan Abstract—Due to the continuous increase in earth's population, The interesting thing to be noted is that the inventor of this adequate supply of resources is going to be a major issue. One basic device states that this unique power controller design analyses essential resource in rising demand is energy and in particular power consumption using an artificial intelligence algorithm electrical energy. The contributions of the scientific community implemented on a high-end micro-controller. The key point toward the goal of sustainability with regard to energy consumption here is the “high-end micro-controller", which is a good of embedded systems are previously discussed in many research example for an embedded system and how they can be present works. Low power has become one of the major design issues due to the increased demand in personal computing devices and portable without being really noticed, often in surprising quantities. communication system. In this paper a survey on minimizing energy This leads to the main topic, the energy consumption of consumption of VLSI Processors using multiple supply voltages is embedded systems or VLSI Processors and the various presented. This survey discusses on search method for a scheduling strategies available to reduce it. Besides helping to save the and module selection problem using multiple supply voltages so as to environment, reducing energy consumption of embedded minimize dynamic energy consumption under time and area systems can lead to immediate monetary rewards for their constraints. The algorithm based on a genetic algorithm is surveyed producers, for example increased sales of the mobile phone to find near-optimal solutions in a short time for large-size problems. with the longest standby time, which is suspected to be the The literature related to the multiple supply voltages with genetic main reason behind the efforts to minimize power approach and energy consumption minimization in various VLSI systems is presented. consumption. In this survey the Genetic Approach based Minimizing energy consumption of VLSI Processors Using Keywords— Energy minimization, Functional pipelining, Multiple Supply Voltages is presented. Multiple supply voltages, dynamic power, scheduling. II. LITERATURE SURVEY I. INTRODUCTION This section presents the literature survey on the minimization of power consumption in VLSI processors. The A T the time of writing, 6.7 billion people live on earth. It is estimated that the world population will reach 9 billion by 2040. This increase alone will result in rapidly rising power consumption can be reduced only if the cause for the power dissipation is found. energy consumption. This problem is amplified by rising Massoud Pedram [17] presented the cause for the power living standards in developing countries. The present world dissipation in VLSI processors. Power dissipation in CMOS electricity production is about 20 trillion kilowatt-hours. By circuits is caused by the three sources: 1) the leakage current 2030, it will reach 30 trillion kilowatt-hours, mostly through which is primarily determined by the fabrication technology, coal and natural gas. Coal is a very dirty form of energy, consists of reverse bias current in the parasitic diodes formed especially when its emissions are not properly filtered, which between source and drain diffusions and the bulk region in a is mostly the case in developing countries. This will result in MOS transistor as well as the subthreshold current that arises serious repercussions for the environment. It stands to reason from the inversion charge that exists at the gate voltages to try to limit those consequences. One approach is sustainable below the threshold voltage, 2) the short-circuit (rush-through) development, which means to use resources to meet ones current which is due to the DC path between the supply rails needs in such a way that future generations have the ability to during output transitions and 3) the charging and discharging meet their needs in the available environment. Producing of capacitive loads during logic changes. energy in ways that destroy the environment obviously The diode leakage takes place when a transistor is turned contradicts this goal. In theory, there is more than enough off and another active transistor charges up or down the drain solar energy available to supply the entire world. In practice, with respect to the first transistor’s bulk potential. The ensuing harvesting this energy in a cheap and efficient way is not easy. current is proportional to the area of the drain diffusion and Therefore it is important to put the created energy to good use the leakage current density. The diode leakage is typically 1 instead of wasting it. picoA for a 1 micro-meter minimum feature size! The subthreshold leakage current for long channel devices increases linearly with the ratio of the channel width over channel length and decreases exponentially with VGS-Vt where B. Sathiyabama, Research Scholar Sathyabama University, Chennai, VGS is the gate bias and Vt is the threshold voltage. Several India. hundred millivolts of “off bias” (say, 300-400 mV) typically Dr. S. Malarkkan, Principal, Manakulavinayagar Institute of Technology, reduces the subthreshold current to negligible values. With Pondicherry, India. 350 http://sites.google.com/site/ijcsis/ ISSN 1947-5500 (IJCSIS) International Journal of Computer Science and Information Security, Vol. 8, No. 9, December 2010 reduced power supply and device threshold voltages, the sub circuit delay remains less than the clock period provides the threshold current will however become more pronounced. In opportunity to reduce power consumption of VLSI circuits. addition, at short channel lengths, the subthreshold current The objective is to change the voltage of the body bias to also becomes exponentially dependent on drain voltage reduce leakage, allowing the circuit to consume less power instead of being independent of VDS (see [18] for a analysis). whenever the clock edge can be met as detected beforehand. The subthreshold current will remain 102 - 105 times smaller Hariyama et al, [1] proposed a novel approach on than the “on current” even at submicron device sizes. minimizing energy consumption of VLSI processors based on The short-circuit (crowbar current) power consumption for dual-supply-voltage assignment and interconnection an inverter gate is proportional to the gain of the inverter, the simplification. His work presents a design technique to cubic power of supply voltage minus device threshold, the minimize energy of both functional units (FUs) and an input rise/fall time, and the operating frequency [19]. The interconnection network between FUs. To reduce complexity highest short circuit current flows when there is no load; this of the interconnection network, data transfers among FUs are current decreases with the load. If gate sizes are selected so classified according to FU types of operations in a data flow that input and output rise/fall times are about equal, the short- graph. The basic idea behind reducing the complexity of circuit power consumption will be less than 15% of the interconnection network is that the interconnection resource dynamic power consumption. If, however, design for high can be shared among data transfers with the same FU type of a performance is taken to the extreme where large gates are used source node and the same FU type of a destination node. to drive relatively small loads, then there will be a stiff penalty Furthermore, an efficient method based on a genetic algorithm in terms of short-circuit power consumption. is presented for large-size problems. The short-circuit and the leakage currents in CMOS circuits Xiaoying et al, [25] studied the problem of leakage power can be made small with proper circuit and device design reduction by means of input vector control, and develop a techniques. The dominant source of power dissipation is thus platform for CMOS combinational circuit leakage power the charging and discharging of the node capacitances (also reduction. Genetic algorithm is worn for searching minimum referred to as the dynamic power dissipation) and is given by: leakage vector with circuit status difference as fitness function. Experimental results indicate that the proposed 0.5 method can achieve satisfied leakage power reduction, and the where C is the physical capacitance of the circuit, Vdd is the run time is reasonable. This method has no necessity for Spice supply voltage, E(sw) (referred as the switching activity) is the simulation and independent from target technology. average number of transitions in the circuit per 1/fclk time, and Hariyama et al, [2] proposed a Genetic approach to fclk is the clock frequency. minimizing energy consumption of VLSI processors using Ishikawa et al., [20] discussed on the power dissipation multiple supply voltages. The author presents an efficient control. A bit-serial multiple-valued reconfigurable VLSI search method for a scheduling and module selection problem using current-mode logic circuits has been introduced by the using multiple supply voltages so as to minimize dynamic author. A Differential-Pair Circuit (DPC) is used as a basic energy consumption under time and area constraints. The component of a cell, so that the static power is dissipated even proposed algorithm is based on the genetic algorithm so that it in the nonactive cells. To solve the problem, autonomous can find near-optimal solutions in a short time for large-size ON/OFF control of the current sources is presented based on problems, n efficient search can be achieved by crossover that superposition of bit-serial data and current-source control prevents generating nonvalid individuals and a local search is signals. In the proposed switched current control technique, also utilized in the algorithm. Experimental results for large- the static power dissipation can be greatly reduced because size problems with 1,000 operations exhibits that the proposed current sources in nonactive circuit blocks are turned off. The method can achieve significant energy reduction up to 50 superposition of data and control signals in a single percent and can find a near-optimal solution in 10 minutes. interconnection is effectively utilized to reduce complexity of Conversely, the ILP-based method cannot find any feasible switches and interconnections, and to eliminate skew between solution in one hour for the large-size problem, even if a state- data and control signals. It is evaluated that the reduction of of-art mathematical programming solver is used. the power dissipation is remarkable, if the operating ratio is W. Hung et al, [22] discussed briefly on the techniques in less than 75%. reduction of power consumption. In this paper, the author Xin He Al-Kadry et.al, [21] proposed a novel concept to presents an algorithm for the minimization of total power control power dissipation in VLSI processors. This paper consumption via multiple VDD assignment, multiple VTH emphasizes on adaptive leakage control using body bias assignment, device sizing and stack forcing, while maintaining technique to reduce the power dissipation of the 65 nm MOS performance requirements. These four power reduction devices. Through adding forward body biasing, the leakage is techniques are correctly encoded in genetic algorithm and reduced in sub-100 nm CMOS devices (unlike above-100 nm evaluated simultaneously. The overhead imposed by insertion devices) while slightly increasing the signal propagation of level converters is also taken into account. The delay. For the conditions where the circuit does not use up the effectiveness of each one of power reduction mechanism is entire clock cycle, this slack can be used to reduce the power verified, as are the combinations of different approaches. dissipation without any loss in performance. The fact that the Experimental results are provided by the author for a number 351 http://sites.google.com/site/ijcsis/ ISSN 1947-5500 (IJCSIS) International Journal of Computer Science and Information Security, Vol. 8, No. 9, December 2010 of 65 nm benchmark circuits that span typical circuit diminution in power consumption comes at no additional topologies, including inverter chains, SRAM decoders, impact to area or performance and does not require any multiplier and a 32bit carry adders. From the experimental alteration to the design flow. It is exposed that the number of results, the author shows that the combination of four low possible input orders increases exponentially in the number of power techniques is the effective way to achieve low power inputs to the checker. As a result, the computational cost of budget. finding the optimum input order can be very expensive as the Power dissipation in CMOS digital circuits consists of number of inputs to the checker increases. The author presents dynamic power, short circuit power and static power. Short a very effective technique to build a reduced cost function to circuit power consumption can be kept within bounds by solve the optimization problem to find a near optimal input careful design and tuning the switching characteristics of order. It scales well with growing number of inputs to the complementary logic (slope engineering); it is usually checker, and the computational costs are independent of the negligible compared to dynamic power and leakage power. complexity of the checker. Experimental results illustrates that Dynamic power was once the dominant power consumption a reduction in power consumption of 16% on the average for term. However, as the result of technology scaling and VTH several types of checkers can be obtained using the proposed (threshold voltage) decreasing, leakage power will soon technique. account for a large portion of total power consumption. Mohanty et al, [4] puts forth an Energy efficient scheduling Although there are many techniques to reduce power for datapath synthesis. In his paper, two new algorithms are dissipation, most existing works focus on one technique in described for datapath scheduling which aim at energy isolation instead of concurrently applying a number of power reduction while maintaining performance. The given minimization techniques. In [22], a power optimization algorithms, time constrained and resource constrained, utilize framework based on the genetic algorithm is presented. The the concepts of multiple supply voltage and dynamic clocking optimization strategy combines four power reduction for energy minimization. In dynamic clocking, the functional techniques: multiple VDD assignment, multiple VTH units can be worked at different frequencies depending on the assignment, gate sizing, and stack forcing. It simultaneously computations occurring within the datapath during a given applies and evaluates the effects of these techniques to achieve clock cycle. The plan is to schedule high energy units, for maximum power saving under a hard timing constraint. The instance the multipliers at lower frequencies such that they can framework can be easily extended to include other power be operated at lower voltages to reduce energy consumption reduction techniques. To the best of our knowledge, this is the and the low energy units, such as adders at higher frequencies, first power optimization framework that simultaneously uses to compensate for speed. The algorithms have been applied to all of these four power reduction techniques. a variety of high level synthesis benchmark circuits under Compared to the ILP approach that were used by [23] [24], different time and resource constraints. The experimental one advantage of GA approach is that the parallel nature of results demonstrate that for the time constrained algorithm, genetic algorithms suggests parallel processing as the natural energy savings in the range of 33-75% are obtained. Similarly, route to explore. The author implements a parallel version of for the resource controlled algorithm, under various resource their algorithm, by dividing the population processing among constraints using two supply voltage levels (5.0 V, 3.3 V) multiple processors. The authors notice that in average more energy savings in the range of 24 - 53% can be obtained. than 3X run-time speed-up on a 4-processor workstation Muthumala et al., [5] presents a technique to minimize the against the single-processor version of the algorithm (The total energy consumption under time and area constraints, reason that the author cannot achieve a 4X speedup is the considering interconnection and functional unit energy. interaction overhead among parallel processes). Another Multiple supply and threshold voltage method is used to advantage is that for ILP approach, the running time for a minimize the static and dynamic energy in the functional large circuit may be prohibitively long; while for the GA- units. A genetic algorithm based search technique is proposed based strategy, it can be set a proper termination criterion to for the energy consumption minimization problem, so that tradeoff the runtime and power saving. near-optimal solution can be found in a reasonable time for Mohanram et al, [3] discussed on the topic of energy large-size problems. Interconnection simplification is attained consumption in which Lowering power consumption in by increasing the sharing of interconnections among concurrent checkers via input ordering is presented. The functional units. Experimental results show that up to 30% of author presents an efficient and scalable technique for energy savings can be achieved by this proposed method. lowering power consumption in checkers used for concurrent Kamble et al, [6] presented a comparative study on Energy- error detection. The basic idea is to make use of the functional efficiency of VLSI caches. The author investigates the use of symmetry of concurrent checkers with respect to their inputs, organizational alternatives that lead to more energy-efficient and to order the inputs such that switching activity (and hence caches for contemporary microprocessors. Dissipative power consumption) in the checker is minimized. The inputs transitions are likely to be very correlated and skewed in of the checker are typically driven by the outputs of the caches, precluding the use of simplistic hit/miss ratio based function logic and check symbol generator logic-spatial power dissipation models for accurate power estimations. The correlations between these outputs are analyzed to compute an authors use a detailed register-level simulator for a typical input order that minimizes power consumption. The pipelined CPU and its multi-level caches, and simulate the 352 http://sites.google.com/site/ijcsis/ ISSN 1947-5500 (IJCSIS) International Journal of Computer Science and Information Security, Vol. 8, No. 9, December 2010 execution of the SPECint92 benchmarks to glean accurate Dynamic Voltage Scaling (DVS), Dynamic Frequency Scaling transition counts. A detailed dissipation model for CMOS (DFS) can be used to find optimized solution. Various caches is brought up for estimating the energy dissipation concepts such as pipelining, parallel processing, retiming, based on electrical parameters of a typical circuit unfolding, systolic array etc. are used in design of modern implementation and the transition counts collected by VLSI based low power. simulation. A block buffering method is presented to allow Implementation of VLSI design algorithms includes high cache energy requirements to be reduced without increasing level architectural transformations. Pipelining ,parallel access latencies. The authors report results for a system with processing, retiming ,unfolding, folding and systolic array an off-chip L2 cache. The authors conclude that block design methodologies plays an important role for optimized buffering, with sub-banking to be very effective in reducing high performance design. Similarly, high level algorithm energy dissipation in the caches, and in the off-chip I/O pad transformations such as strength reduction look ahead and drivers. relaxed look ahead are also utilized for design implementation. Santosh Chede et al, [7] proposed on the Significance of Strength reduction transformations are applied to minimize the VLSI Techniques for Low Power Real Time Systems. In number of multiplications in convolution, parallel infinite microelectronics design, power consumption and the speed of impulse response (FIR) digital filters, discrete cosine operation, are crucial constraints. Propagation delay of the transforms (DCTs) and parallel rank –order filters. Look ahead circuit component has an impact on such factors. Pipelining and relaxed look ahead transformations are pertained to design and parallel processing strategies are used for desirable pipelined direct form and lattice recursive digital filters and propagation delays and hence for clock and throughput adaptive filters and parallel recursive digital filters. And these variation respectively. To some extent variation in propagation strategies are used to develop and design architectures for delay is accountable for power consumption reduction. In his multiplication, addition, digital filters, pipelining styles, low work, pipelining and parallel processing concepts are analyzed power computations and architectures for high performance with reference to task scheduling in real time system. Power programmable or ultra low power embedded digital signal consumption and speed of operation problems of such systems processors, applicable to various biomedical, industrial, are analyzed. defense, consumer applications etc [8]. Main goal of most of the system level or circuit design are Jui-Ming Chang et al, [9] proposed a novel technique for high performance and power optimization. For high Energy Minimization Using Multiple Supply Voltages. A performance system design, propagation delay minimization dynamic programming technique is presented for solving the plays an important role. Basically size, cost, performance and multiple supply voltage scheduling problems in both power consumption are the crucial issues in low power nonpipelined and functionally pipelined data-paths. The portable battery operated system design. Excessive power scheduling problem refers the assignment of a supply voltage dissipation which overheats thereby degrading the level (selected from a fixed and known number of voltage performance and lifetime is not at all affordable. Energy levels) to each operation in a data flow graph so as to consumption being an important constraint for battery life minimize the average energy consumption for given estimation, VLSI based low power design of dedicated computation time or throughput constraints or both. The multimode signal conditioning integrated circuit is desirable. energy model is accurate and accounts for input pattern Modern systems consist of digital realization of analog dependencies, re-convergent fanout induced dependencies, processes and this helps to design system with high precision, and the energy cost of level shifters. Experimental results high signal to noise ratio (SNR), repeatability and flexibility. illustrate that using three supply voltage levels on a number of DSP systems can be realized with custom designed hardware standard benchmarks, an average energy saving of 40.19% circuits or ultra low power high performance programmable (with a computation time constraint of 1.5 times the critical processors fabricated using VLSI circuit technology. path delay) can be attained compared to using a single supply Essentially the role of digital system is to maximize the voltage level. performance with minimum cost and less time to market. One driving factor behind the push for low power design is Performance measures are throughput, clock rate, circuit the growing class of personal computing devices as well as complexity and power dissipation or total energy consumed to wireless communications and imaging systems that demand execute a real/non real time task. In order to design complex high-speed computations and complex functionalities with low digital system using VLSI technology, modeling with node power consumption. Another driving factor is that excessive identification is essential. Generally to carry out design, DSP power consumption has become a limiting factor in integrating algorithms are realized and transformed to hardware. To more transistors on a single chip. Unless power consumption investigate and analyze data flow and data paths i.e. is considerably reduced, the resulting heat will limit the parallelism and pipelining among tasks and subtasks, system feasible packing and performance of VLSI circuits and modeling methods like block diagrams, Signal flow graph systems. The most effective way to lessen power consumption (SFG), Data flow Graph (DFG), Dependence graph etc. is is to lower the supply voltage level for a circuit. Reducing the very much required. In such design there is trade off between supply voltage however increases the circuit delay. sampling frequency, operating frequency and power Chandraskan et al. [10] compensate for the increased delay by consumption, in order to design high performance system. shortening critical paths in the data-path using behavioral 353 http://sites.google.com/site/ijcsis/ ISSN 1947-5500 (IJCSIS) International Journal of Computer Science and Information Security, Vol. 8, No. 9, December 2010 transformations such as parallelization or pipelining. The and to aid in the comparison of results. Results show that resulting circuit consumes lower average power while meeting GALOPS achieves significant power reductions in the the global throughput constraint at the cost of increased circuit presented benchmark designs. In addition, GALOPS generates area. More recently, the use of multiple supply voltages on the a family of unique solutions for each design, all of which chip is attracting attention. This has the advantage of allowing satisfy the multiple design objectives, providing flexibility to modules on critical paths to use the highest voltage level (thus the VLSI designer. meeting the required timing constraints) while allowing The power consumption of the very large scale integration modules on noncritical paths to use lower voltages (thus (VLSI) devices has become an important parameter in recent reducing the energy consumption). This method tends to result years, largely due to the explosion in the use of portable in smaller area overhead compared to parallel architectures. communication and computing systems. Of particular interest There are, however, a number of practical problems that in such systems are digital signal processing (DSP) devices. must be overcome before use of multiple supply voltage These devices are specialized processors used widely in becomes prevalent. These problems include routing of complex functions such as telecommunications, data multiple supply voltage lines, area/delay overhead of required compression, and speech processing. The increasing level shifters, and lack of design tools and methodologies for requirements for portable systems to incorporate these multiple supply voltages. The first issue is an important functions have led to increased demand for low-power DSP concern which should be considered by any designer who devices. However, the design of DSP devices that offer wants to use multiple supply voltages. That is, there is a complex functions with low-power consumption requires the tradeoff between lower energy dissipation and higher routing use of advanced automated synthesis tools. cost. The remaining problems (that is, level shifter cost and Traditional automated synthesis tools optimized the VLSI lack of tools) are addressed in the authors work. That is, device for speed and area. This presented a complex solution shown that the area/delay overhead of level shifters is space, especially when considered at the high level of relatively small and will present an effective algorithm for abstraction (the design capture stage). The addition of power using multiple supply voltages during behavioral synthesis. as a design objective compounds the complexity of the high- In this context, an important problem is to assign a supply level synthesis task. Therefore, high-level low-power voltage level (selected from a finite and known number of synthesis tools require a more robust search and optimization supply voltage levels) to each operation in a data flow graph mechanism to produce designs with optimal tradeoffs between (DFG) and schedule various operations so as to minimize the the objective parameters. Genetic algorithms (GAs) [12] have energy consumption under given timing constraints. To this proven to be a successful technique for tackling the complex problem is referred as the multiple-voltage scheduling problems inherent in the design and optimization of VLSI problem or the MVS problem for short. In his work, the devices. Examples are VLSI synthesis tools such as that problem is tackled in its general form. Chandraskan et al in developed by Arslan et al. [13], which uses a GA for the [10] shows that the MVS problem is NP-hard even when only structural synthesis of logic circuits. A tool for reducing VLSI two points exist on the energy-delay curve for each module implementation area by using a GA to reduce the size of (these curves may be different from one module to another), functional operators was developed by Martin and Knight and then propose a dynamic programming approach for [14]. The authors have previously demonstrated the solving the problem. This algorithm which has pseudo- application of GAs in low-power synthesis [15], [16] using a polynomial complexity (cf., Section IV-C) produces optimal restricted GA with limited genetic operators. results for trees, but is suboptimal for general directed acyclic In his work, genetic algorithm for low-power synthesis graphs. The dynamic programming technique is then (GALOPS) is presented, a GA for the high-level synthesis of generalized to handle functionally pipelined designs. This is low power CMOS-based DSP designs. GALOP uses problem- the first time that the use of multiple supply voltages in a specific techniques for low-power synthesis. As illustrated functionally pipelined design is considered. A novel revolving here, the incorporation of these techniques into the GA schedule for handling these designs is presented by this framework requires modification of the standard genetic author. operations. The primary objective of GALOPS is to construct Bright et al, [11] presents a new tool for the synthesis of a minimum power design from an initial high-level low-power VLSI designs, specifically, those designs targeting specification, while tracking other performance constraints digital signal processing applications. The synthesis tool such as area and speed. The author presents the application of genetic algorithm for low-power synthesis represented as GA for minimizing power consumption in four contributions. GALOPS uses a genetic algorithm to apply power-reducing (1) The formulation of a GA that can be able in handling the transformations to high-level signal-processing designs, VLSI low-power synthesis problem, considering the specified producing designs that satisfy power requirements as well as performance constraints of CMOS devices (2) The timing and area constraints. GALOPS use the problem- development of problem-specific genetic operators that specific genetic operators that are specifically tailored to manipulate a library of low-power transformations. Standard incorporate VLSI-based digital signal processing design genetic operators are modified to incorporate these knowledge. A number of signal-processing benchmarks are transformations, in particular, a crossover operator is utilized to facilitate the analysis of low-power design tools, developed which recognizes and applies power-saving 354 http://sites.google.com/site/ijcsis/ ISSN 1947-5500 (IJCSIS) International Journal of Computer Science and Information Security, Vol. 8, No. 9, December 2010 transformations to designs. The developed crossover operator [13] T. Arslan, D. H. Horrocks, and E. Ozdemir, “Structural cell-based VLSI circuit design using a genetic algorithm,” in Proc. IEEE Int. Symp. preserves the notion of inheritance in a genetic algorithm (3) Circuits Syst., vol. 4, 1996, pp. 308–311. Results that show the significant power reductions obtained [14] R. S. Martin and J. P. Knight, “Genetic algorithms for optimization of using the GA synthesis technique (GALOPS). The effects of integrated circuits synthesis,” in Proc. 5th Int. Conf. Genetic Algorithms, 1993, pp. 432–438. relaxing design constraints, such as area, have also been [15] M. S. Bright and T. Arslan, “A genetic framework for the high-level analyzed and compared. (4) Analysis of the capability of a optimization of low power VLSI DSP systems,” Electron. Lett., vol. 32, GA-based synthesis tool to present multiple solutions to a pp. 1150–1151, June 1996. problem, exploiting the multiple solution nature of the GA [16] Bright, M.S. and Arslan, T., “Transformational-based synthesis of VLSI based DSP systems for low power using a genetic algorithm,” in IEEE search technique. Int. Symp. Circuits and Systems, CA, May 1998, pp. 45–48. III. CONCLUSION [17] Massoud Pedram, "Design Technologies for Low Power VLSI", Encyclopedia of Computer Science and Technology, 1995 The reduction in the power consumption is an important [18] T. A. Fjeldly and M. Shur. " Threshold voltage modeling and the issue in modern portable personal computing and wireless subthreshold regime of operation of short-channel MOSFET’s. " IEEE Transactions on Electron Devices, 40(1):137–145, Jan. 1993. communication systems. Minimizing the energy consumption [19] H. J. M. Veendrick. " Short-circuit dissipation of static CMOS circuitry of VLSI Processors using multiple supply voltages with and its impact on the design of buffer circuits. " IEEE Journal of Solid Genetic Approach is a challenge task. Therefore, any method State Circuits, 19(8):468–473, August 1984. [20] Ishikawa, Akitaka Okada, Nobuaki Kameyama, Michitaka," Low-Power that provides a way to reduce this consumption must be Multiple-Valued Reconfigurable VLSI Based on Superposition of Bit- studied, evaluated and applied to the system in development. Serial Data and Current-Source Control Signals", Multiple-Valued Logic The techniques reviewed from the literature presented in this (ISMVL), 2010 40th IEEE International Symposium on 26-28 May 2010 , pp: 179 – 184 survey promise an interesting way to achieve this issue. Also [21] Xin He Al-Kadry, S. Abdollahi, A.,"Adaptive leakage control on body this literature study can be helpful for the further development biasing for reducing power consumption in CMOS VLSI in the minimization of power consumption in future. circuit",Quality of Electronic Design, 2009. ISQED 2009, pp: 465 – 470 [22] W. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin and Y. Tsai, "Total Power Optimization through Simultaneously Multiple-VDD REFERENCES Multiple-VTH Assignment and Device Sizing with Stack Forcing", [1] Hariyama, M. Yamadera, S. Kameyama, M., "Minimizing energy Proceedings of the 2004 International Symposium on Low Power consumption of VLSI processors based on dual-supply-voltage Electronics and Design (ISLPED’04), pp: 144-149 assignment and interconnection simplification", Circuits and Systems, [23] Srivastava and D. Sylvester, "Minimizing total power by simultaneous 2005. 48th Midwest Symposium on 7-10 Aug. 2005, pp: 1867 - 1870 Vdd/Vth assignment," IEEE/ACM Asia-South Pacific Design Vol.2 Automation Conference, pp. 400-403, 2003. [2] Hariyama, M. Aoyama, T. Kameyama, M., "Genetic approach to [24] D. Nguyen, A. Davare, M. Orshansky, D. Chinnery, B. Thompson, K. minimizing energy consumption of VLSI processors using multiple Keutzer, “Minimization of Dynamic and Static Power Through Joint supply voltages", Computers, IEEE Transactions on Issue Date : Jun Assignment of Threshold Voltages and Sizing Optimization,” ISLPED 2005, Volume : 54 , Issue:6, pp: 642 – 650 2003. [3] Mohanram, K. Touba, N.A., "Lowering power consumption in [25] Xiaoying Zhao, Jiangfang Yi, Dong Tong and Xu Cheng,"Leakage concurrent checkers via input ordering", Very Large Scale Integration Power Reduction for CMOS Combinational Circuits",Micro-Processor (VLSI) Systems, IEEE Transactions on Nov. 2004, Volume : 12 , Research & Development Center, Peking University, Beijing Issue:11, pp: 1234 – 1243 [4] Mohanty, S.P. Ranganathan, N., "Energy efficient scheduling for datapath synthesis", VLSI Design, 2003. Proceedings. 16th International Conference on 4-8 Jan. 2003, pp: 446 – 451 [5] Waidyasooriya Hasitha Muthumala, Masanori Hariyama and Michitaka Kameyama, "GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design", IEEE 2006 [6] Kamble, M.B. and Ghose, K., "Energy-efficiency of VLSI caches: a comparative study", VLSI Design, 1997. Proceedings., Tenth International Conference on 4-7 Jan 1997, pp: 261 – 267 [7] Santosh Chede, Kishore Kulat and Rajesh Thakare, "A Significance of VLSI Techniques for Low Power Real Time Systems", 2010 International Journal of Computer Applications (0975 - 8887), Volume 1 – No. 22, pp: 86-91 [8] Flavius Gruian, “Hard real time scheduling for low energy using stochastic data and DVS processors,” in proc. of Int. symposium on Low Power Electronics and Design California, USA, 2001, 46-51. [9] Jui-Ming Chang and Massoud Pedram. "Energy Minimization Using Multiple Supply Voltages", IEEE Transactions On Very Large Scale Integration (VLSI) Systems, VOL. 5, NO. 4, DECEMBER 1997, pp: 436-444 [10] Chandrakasan, M. Potkonjak, J. Rabaey, and R. W. Brodersen, “HYPER-LP: A system for power minimization using architectural transformations,” in Proc. IEEE Int. Conf. Computer-Aided Design, 1992. [11] Marc S. Bright and Tughrul Arslan, "Synthesis of Low-Power DSP Systems Using a Genetic Algorithm", IEEE Transactions on evolutionary computation, vol. 5, no. 1, February 2001, pp: 27-41 [12] D. E. Goldberg, Genetic Algorithms in Search, Optimization and Machine Learning. Reading, MA: Addison-Wesley, 1989. 355 http://sites.google.com/site/ijcsis/ ISSN 1947-5500

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The International Journal of Computer Science and Information Security (IJCSIS) is a well-established publication venue on novel research in computer science and information security. The year 2010 has been very eventful and encouraging for all IJCSIS authors/researchers and IJCSIS technical committee, as we see more and more interest in IJCSIS research publications. IJCSIS is now empowered by over thousands of academics, researchers, authors/reviewers/students and research organizations. Reaching this milestone would not have been possible without the support, feedback, and continuous engagement of our authors and reviewers.
Field coverage includes: security infrastructures, network security: Internet security, content protection, cryptography, steganography and formal methods in information security; multimedia systems, software, information systems, intelligent systems, web services, data mining, wireless communication, networking and technologies, innovation technology and management. ( See monthly Call for Papers)
We are grateful to our reviewers for providing valuable comments. IJCSIS December 2010 issue (Vol. 8, No. 9) has paper acceptance rate of nearly 35%.
We wish everyone a successful scientific research year on 2011.
Available at http://sites.google.com/site/ijcsis/
IJCSIS Vol. 8, No. 9, December 2010 Edition
ISSN 1947-5500 � IJCSIS, USA.

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