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A Survey on Static Power Optimization in VLSI

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					                                                                (IJCSIS) International Journal of Computer Science and Information Security,
                                                                Vol. 8, No. 9, December 2010



        A Survey on Static Power Optimization in VLSI
                                                     A. Janaki Rani and Dr. S. Malarkkan


   Abstract---Power has become one of the primary constraints for
both the high performance and portable system design. The growing
market of battery powered electronic systems like cellular phones,
personal digital assistants demands the design of microelectronic                     The power dissipation can be minimized only if the source
circuits with low power consumption. Power dissipation in these
systems may be divided into two major components namely static
                                                                                   of power dissipation is analyzed. Power dissipation in digital
and dynamic power dissipation. The static power is the standby                     CMOS circuits is caused due to sources as follows. (a) The
power that is wasted even if the device is not performing any                      leakage current, which is primarily found by the fabrication
function. As technology scales down the static power dissipation is                technology, consists of four components namely sub-threshold
dominant in VLSI circuits which are mainly due to leakage current in               leakage current (Isub), gate direct tunneling current (Ig), gate-
transistors. Hence a focus is necessary on the leakage currents. These             induced drain leakage current IGIDL) and reverse-biased
leakage currents are mainly due to sub-threshold leakage and gate
oxide leakage. The sub-threshold leakage is dominant which can be
                                                                                   junction leakage current (Irev) , (b) the standby current which
minimized by reducing the supply voltage, reducing the transistor                  is the DC current drawn continuously from Vdd to ground, (c)
size, decreasing the temperature and increasing the threshold voltage.             the short-circuit (rush-through) current which is due to the DC
In this paper a survey is presented on static power optimization in                path between the supply rails during output transitions, (d) the
VLSI. It presents the possible solutions to reduce the leakage power               capacitance current which flows to charge and discharge
in various digital logic circuits like CMOS, I2C etc.                              capacitive loads during logic changes. The term static power
                                                                                   dissipation describes the sum of leakage and standby
  Index Terms—Leakage, Low-Power, Power Gating,                                    dissipations. The static power dissipation is dominated by the
Semicustom, Input Vector Control, Body Bias Control, Sleep
                                                                                   leakage components and is given by
Transistor Sizing, Sleepy Stack, Zigzag Power Gating (ZPG)

                          I.     INTRODUCTION                                             Pstatic = Ileak * Vdd ------------------------------------ (1)



I  N the past, the major concerns of the VLSI designer were                            The sub-threshold leakage current and gate direct
   area, performance, cost and reliability; power                                  tunneling current are dominant in the sub-100nm CMOS
considerations were mostly of only secondary importance. In                        circuits. The sub-threshold leakage current is given by
recent years, however, this has begun to change and,
increasingly, power is being given comparable weight to area                         Isubth=I0 exp[(Vgs-Vt) / (n VT) ] [1- exp (-Vds/VT)] —            (2)
and speed. Several factors have contributed to this trend.                                   And I0=μeff Cox (W/L)VT2 ------------------               (3)
Portable computing and communication devices demand high-                             Where μeff is the electron/hole mobility, Cox is the gate
speed computation and complex functionality with low power                         capacitance per unit area, W and L are width and length of the
consumption. Heat production in high-end computer products                         channel respectively, Vt is the threshold voltage, n is the sub-
limits the feasible packing and performance of VLSI circuits                       threshold swing co-efficient, VT is the thermal voltage, Vgs is
and increases the packaging and cooling costs. Circuit and                         the transistor gate to source voltage and Vds is the drain to
device reliability deteriorate with increased heat dissipation,                    source voltage. The sources of static power dissipation is
and thus the die temperature. Heat pumped into the rooms, the                      summarized above and the following section of this paper
electricity consumed and the office noise diminishes with low                      presents the literature survey on the different techniques for
power LSI chipset. Leakage-power problems are a serious                            reducing leakage current which are power supply gating, dual
issue in portable electronic systems that operate mostly in                        threshold voltage, input vector control, body bias control,
standby mode. Lowering power-supply voltage in the system                          sleepy stack, forced stacking and use of MTCMOS, VTCMOS
is one of the most effective schemes to reduce the power                           and guarding.
dissipation. As the VLSI technology and threshold/supply
voltage continue scaling down, leakage power has become                                               II.     LITERATURE SURVEY
more and more significant in the power dissipation of today’s
CMOS circuits. For example, it is projected that subthreshold                         Mutoh et al, [3] presented the concept of Multi Threshold
leakage power can contribute as much as 42% of the total                           CMOS (MTCMOS). In this technique, a high-threshold
power in the 90nm process generation [1].                                          voltage transistor is inserted in series with the power supply
                                                                                   and the existing design and ground as shown in Figure 1.
                                                                                   During active mode of operation, the high threshold Vt
   A. Janaki Rani, Research Scholar Sathyabama University, Chennai, India.         transistors are turned on, thereby facilitating normal operation
  Dr. S. Malarkkan, Principal, Manakulavinayagar Institute of Technology,
                                                                                   of the circuit as there exists a direct path from the output to
Pondicherry, India.

                                                                             344                                http://sites.google.com/site/ijcsis/
                                                                                                                ISSN 1947-5500
                                                           (IJCSIS) International Journal of Computer Science and Information Security,
                                                           Vol. 8, No. 9, December 2010


ground and Vdd. During standby mode, these transistors are
turned off creating a virtual power supply and ground rail and
cutting off the circuit from supply. The high Vt transistors are
called sleep transistors.




                                                                                             Fig.3 Sleepy stack inverter circuit
                       Fig.1 MTCMOS Circuit
                                                                                Preetham Lakshmikanthan et al, [6] presented a self-
   Narendra et al, [4] showed that stacking of two off
                                                                             controlling leakage reduction technique called VCLEARIT for
transistors significantly reduces sub-threshold leakage
                                                                             CMOS circuits. Signal probabilities determine the mode of
compared to a single off transistor. It is an effective way to
                                                                             operation (active or standby) of the gates making up complex
reduce leakage power in active mode. Transistor stacking
                                                                             circuits. Cancellation of leakage effects in both the pull up
technique uses the dependence of Isub on the source terminal
                                                                             network (PUN) as well as the pull down network for CMOS
voltage Vs. With the increase of Vs of the transistor, the sub-
                                                                             gates results in leakage reduction. A combination of high Vt
threshold leakage current reduces exponentially. If natural
                                                                             and standard Vt control transistors achieve voltage balancing
stacking of transistors does not exist in a circuit, then to utilize
                                                                             in the pull up and pull down paths. Results show up to 61%
the stacking effect a single transistor of width W is replaced
                                                                             reduction in leakage power of combinational circuits.
by two transistors each of width W/2. This is called forced
stacking as shown in Figure 2.




                     Fig. 2 Forced stacking circuit
                                                                                                  Fig. 4 VCLEARIT Circuit
   J.C. Park et al, [5] described a sleepy stack technique which
combines the sleep transistor approach during active mode and                   Yu et al, [7] proposed a power optimization technique on
the stack approach during standby mode. In this technique,                   reduced leakage power with thermal awareness using dual
forced stacking is first implemented. Then to one of the                     threshold voltage. Dual- Vth design is an effective leakage
stacked transistors a sleep transistor is inserted in parallel.              power reduction technique at behavioral synthesis level. It
Thus during active mode, the sleep transistors are on thereby                permits designers to replace modules on non-critical path with
reducing the effective resistance of the path. This leads to                 the high-Vth implementation. Though, the existing
reduced propagation delay during active mode as compared to                  constructive algorithms fail to find the optimal solution due to
the forced stacking method. During standby mode, the sleep                   the complexity of the problem and do not consider the on-chip
transistor is turned off and the stacked transistor suppresses               temperature variation. In his research, a two-stage thermal
the leakage power. Figure 3 shows the circuit of a sleepy stack              dependent leakage power minimization algorithm is proposed
inverter, where the S and S’ are sleep control signals.                      by using dual- Vth library during behavioral synthesis. In the

                                                                       345                               http://sites.google.com/site/ijcsis/
                                                                                                         ISSN 1947-5500
                                                         (IJCSIS) International Journal of Computer Science and Information Security,
                                                         Vol. 8, No. 9, December 2010


first stage, the timing impact on other modules caused by                  door for further leakage reduction, when the MLV is not
replacing certain modules with high Vth is quantitatively                  effective. The author then describes a divide and-conquer
evaluated. Based on this analysis and the characteristics of the           approach that combines the gate replacement and input vector
dual- Vth module library, a small set of candidate solutions is            control techniques. It incorporates an algorithm that finds the
generated for the module replacement. Then in the second                   optimal MLV for tree circuits, a fast gate replacement
stage, the on-chip thermal information is obtained from                    heuristic, and a genetic algorithm that connects the tree
thermal-aware floor planning and thermal analysis to select                circuits.
the final solution from the candidate set. Experimental results               Behnam et al, [13] discussed on the leakage minimization
show an average of 17.8% saving in leakage energy                          of SRAM Cells in a Dual-Vt and Dual-Tox Technology.
consumption and a slightly shorter runtime compared to the                 Aggressive CMOS scaling results in the low threshold voltage
best known work. In most cases, this algorithm can actually                and thin oxide thickness for transistors manufactured in deep
find the optimal solution obtained from a complete solution                submicron regime. As a result, reducing subthreshold and
space exploration.                                                         tunneling gate leakage currents has become one of the most
   One of the most effective design techniques for reducing                important criteria in the design of VLSI circuits. His research
leakage is dual- Vth design [8], where performance-critical                puts forth a method based on dual-Vt and dual-Tox assignment
transistors are made of low- Vth to provide the required                   to reduce the total leakage power dissipation of SRAMs while
performance and high- Vth transistors are used everywhere                  maintaining their performance. The technique is based on the
else to reduce leakage. Dual- Vth assignment or allocation can             observation that read and writes delays of a memory cell in an
be applied to all phases of the design flow. Although transistor           SRAM block depend on the physical distance of the cell from
level dual- Vth allocation is the most effective for leakage               the sense amplifier and the decoder. Thus, the idea is to
reduction, it is also the most challenging due to the complexity           implement different configurations of six-transistor SRAM
of dealing with the billions of transistors in modern ICs. Thus            cells corresponding to different threshold voltage and oxide
it has been proposed [9, 10] to allocate Vth at behavioral level,          thickness assignments for the transistors. Different to other
where the solution space is much smaller than that at the                  techniques for low leakage SRAM design, the proposed
transistor level. At behavioral level, dual- Vth allocation can be         technique incurs neither area nor delay overhead. In addition,
converted to the module selection problem. The modules on                  it results in a minor change in the SRAM design flow. The
noncritical path are selected to be replaced with high- Vth                leakage saving obtained by using this technique is a function
implementation. Due to factors such as module sharing in                   of the values of the high threshold voltage and the oxide
behavioral level, it is difficult to model the timing relationship         thickness, as well as the number of rows and columns in the
of modules precisely. And consequently, the optimal module                 cell array.
selection will be hard to obtain. Kawaguch et al, [11] proposed               CMOS scaling beyond the 90nm technology node requires
a circuit called Super Cutoff CMOS (SCCMOS), which is an                   not only very low threshold voltages (Vt) to retain the device
alternate to MTCMOS power gating. In this technique, the                   switching speeds, but also ultra-thin gate oxides (Tox) to
sleep transistors are under-driven (NMOS) or over-driven                   maintain the current drive and keep threshold voltage
(PMOS) when in the standby mode. An NMOS transistor will                   variations under control when dealing with short-channel
be turned off with a slight negative gate voltage instead of               effects [14]. Low threshold voltage results in an exponential
zero voltage. This negative gate voltage decreases the sub-                increase in the subthreshold leakage current, whereas ultra-
threshold leakage current exponentially. In this scheme the                thin oxide causes an exponential increase in the tunneling gate
sleep transistor and the logic transistors are having the same             leakage current. The leakage power dissipation is
standard Vt. Therefore the circuit operates fast in the active             approximately proportional to the area of a circuit. Since in
mode. During standby mode, since the transistor is turned off              many processors caches occupy about 50% of the chip area
with a negative gate voltage, sub-threshold leakage current                [15], the leakage power of caches is one of the major sources
reduces exponentially.                                                     of power consumption in high performance microprocessors.
   Yuan et al, [12] presented an Input Vector Control approach                While one of the ways in reducing the subthreshold leakage
for leakage current reduction. IVC takes advantage of                      is to use higher threshold voltages in some parts of a design, to
transistor stack effect to apply the minimum leakage vector                suppress tunneling gate leakage, high-k dielectrics or multiple
(MLV) to the primary inputs of the circuit during the standby              gate oxides may be used. In [16, 17] a comparative study of
mode. Though, IVC technique becomes less effective for                     using high-k dielectric and dual oxide thickness on the leakage
circuits of large logic depth because the MLV at primary                   power consumption has been presented and an algorithm for
inputs has little impact on internal gates at high logic level. In         simultaneous high-k and high-Tox assignment has been
his research, a technique is presented to overcome this                    proposed. Although some investigation has been done on
limitation by directly controlling the inputs to the internal              Zirconium- and Hafnium-based high-k dielectrics [18], there
gates that are in their worst leakage states. Specifically, a gate         are unresolved manufacturing process challenges in way of
replacement technique is proposed that replaces such gates by              introducing high-k dielectric material under the gate (e.g.,
other library gates while maintaining the circuit’s correct                related to the compatibility of these materials with Silicon [19]
functionality at the active mode. This alteration of the circuit           and the need to switch to metal gates); hence, high-k
does not require changes of the design flow, but it opens the              dielectrics are not expected to be used before 45nm

                                                                     346                               http://sites.google.com/site/ijcsis/
                                                                                                       ISSN 1947-5500
                                                         (IJCSIS) International Journal of Computer Science and Information Security,
                                                         Vol. 8, No. 9, December 2010


technology node [18,20], leaving multiple gate oxide
thicknesses as the one promising solution to reduce tunneling
gate leakage current at the present time. Kyung Ki Kim et al,
[21] proposed a novel design method to minimize the leakage
power during standby mode using a novel adaptive supply
voltage and body-bias voltage generating technique. Based on
the temperature and process conditions, the optimal supply
voltage is generated to reduce leakage power. The body bias
voltage is automatically adjusted continuously by the control
loop to adapt to the process voltage and temperature (PVT)                          Fig. 6 Distributed Sleep Transistor Network (DSTN)
variations. By tuning body-bias voltage using leakage
monitoring circuit, circuits can be biased at the optimal point               Narender Hanchate et al, [23] proposed a novel technique
where sub-threshold leakage current and band-to-band-                      called LECTOR (Refer Fig. 6) for reducing leakage power in
tunneling (BTBT_ leakage current are balanced to accomplish                CMOS circuits. He introduced two leakage control transistors
the minimum leakage power.                                                 (LCT) a PMOS and NMOS within the logic gate. The gate
   Changbo et al, [23] puts forth a Distributed Sleep Transistor           terminal of each LCT is controlled by the source of the other.
Network for power reduction. Sleep transistors are efficient to            In this arrangement, one of the LCT’s is always near its cut-
reduce dynamic and leakage power. The cluster-based design                 off voltage for any input combination. This increases the
(Refer Fig. 4) was presented to reduce the sleep transistor area           resistance of the path from Vdd to ground leading to significant
by clustering gates to minimize the simultaneous switching                 decrease in leakage currents. This technique works effectively
current per cluster and then inserting a sleep transistor per              in both active and idle states of the circuit, resulting in better
cluster. In the research, the author proposes a novel distributed          leakage reduction. The experimental results indicate an
sleep transistor network (DSTN), and show that DSTN is                     average leakage reduction of 79.4% for MCNC “91
intrinsically better than the cluster based design in terms of the         benchmark circuits. De-Shiuan et al, [24] discussed on the
sleep transistor area and circuit performance. The author                  power reduction using sleep transistor sizing for leakage
reveals properties of optimal DSTN designs, and then                       power minimization considering charge balancing. One of the
develops an efficient algorithm for gate level DSTN synthesis.             efficient techniques to reduce leakage power is power gating.
The algorithm obtains DSTN designs with up to 70.7% sleep                  Previously, a DSTN was proposed to reduce the sleep
transistor area reduction when compared to cluster-based                   transistor area for power gating by connecting all the virtual
designs. Furthermore, the author presents custom layout                    ground lines together to minimize the Maximum Instantaneous
designs to verify the area reduction by DSTN. In the cluster-              Current flowing through sleep transistors. In his research, a
based structure shown in Figure 4, a module is decomposed                  new methodology is proposed for determining the sizes of
into several logic clusters, and each cluster is supported by one          sleep transistors of the DSTN structure. The author presents
local sleep transistor. Figure 5 shows the distributed structure           novel algorithms and theorems for efficiently estimating a
called Distributed Sleep Transistor Network (DSTN). In the                 tight upper bound of the voltage drop and minimizing the sizes
DSTN structure, the cluster-based sleep transistor deployment              of sleep transistors. The author also presents mathematical
is enhanced by connecting all the virtual ground lines (VGND)              proofs of the theorems and lemmas in detail. The experimental
together, thus allowing the operating current from each cluster            results show 23.36% sleep transistor area reduction when
to flow through all the sleep transistors. In this way, the                compared to the previous work on space reduction.
discharged current among the sleep transistors tends to be
balanced.




                    Fig. 5. Cluster based design
                                                                                                  Fig. 7 LECTOR Circuit




                                                                     347                               http://sites.google.com/site/ijcsis/
                                                                                                       ISSN 1947-5500
                                                         (IJCSIS) International Journal of Computer Science and Information Security,
                                                         Vol. 8, No. 9, December 2010


   Youngsoo et al, [25] presented a Semicustom Design of                 benchmark circuits. The results from the author’s algorithm
Zigzag Power-Gated Circuits in Standard Cell Elements. ZPG               can lead to about 22% less power dissipation subject to the
solved the long wake-up delay of standard power gating, but              same timing constraints.
its requirement for both nMOS and pMOS current switches, in                 Hyunsik et al [27] developed a technique called variable
a zigzag pattern, requires complicated power networks,                   threshold CMOS, or VTCMOS to reduce standby leakage
limiting application to custom designs. The Zigzag Power                 currents. VTCMOS relies on a triple well process where the
gating (ZPG) circuit is shown in Figure 7. The author                    device Vt is dynamically adjusted by biasing the body
proposed a design framework for cell-based semicustom                    terminal. By applying maximum reverse biasing during the
design of ZPG circuits, using a new power network                        standby mode, the threshold voltage is shifted higher and the
architecture that allows the unmodified conventional logic               sub-threshold leakage current is reduced. The threshold
cells to be combined with custom circuitry such as ZPG flip-             voltage can be tuned during active mode to optimize
flops, input forcing circuits, and current switches. The design          performance.
flow, from the register transfer level description to layout, is
described and applied to a 32-b microprocessor design using a                                      III.      CONCLUSION
1.2-V 65-nm triple-well bulk CMOS process. The use of a
sleep vector in ZPG needs additional switching power when                   As technology scales down below 90 nm, leakage currents
entering standby mode and returning to active mode. The                  have become a critical issue. In the past, circuit techniques and
switching power must be minimized so that is does not                    architectures ignored the effects of these currents because they
outweigh the leakage saved by employing ZPG scheme. The                  were insignificant compared to the switching currents and
author formulates the selection of a sleep vector as a                   threshold voltages were high enough. However, in modern
multiobjective optimization problem, minimizing both the                 technologies, the role of the leakage currents cannot be
transition energy and the total wire length of a design. The             ignored and becomes increasingly significant issue with
author solved the problem by employing multiobjective                    further scaling. Therefore, new circuit techniques and design
genetic-based algorithm. Experimental results of the author              considerations must be developed to control leakage currents
technique show an average saving of 39% in transition energy             in standby mode in order to provide low-power solutions.
and 8% in total wire length for several benchmark circuits in            After analyzing various leakage reduction techniques, it can be
65-nm technology.                                                        concluded that there is a strong correlation between the three
                                                                         performance metrics: leakage power, dynamic power and
                                                                         propagation delay. If one metric is optimized, it leads to a
                                                                         compromise of other metrics. It can be concluded that super
                                                                         cutoff CMOS scheme provides efficient leakage power
                                                                         savings in standby mode and forced stacking is a very
                                                                         effective leakage power saving scheme for active mode of
                                                                         operation. However, if propagation delay is the main criteria,
                                                                         it is recommended that a single sleep transistor based circuits
                                                                         are used in standby mode, though leakage savings of upto an
                                                                         order of magnitude is sacrificed. In active mode of operation,
                                                                         the sleepy stack based approach is suitable for faster circuit
                                                                         operation.
             Fig. 8. Zigzag Power Gating (ZPG) Circuit                                                    REFERENCES
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                                                                   348                                     http://sites.google.com/site/ijcsis/
                                                                                                           ISSN 1947-5500
                                                                      (IJCSIS) International Journal of Computer Science and Information Security,
                                                                      Vol. 8, No. 9, December 2010

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