Dataflow for Library (DOC download)

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					         Lab1: 4-Bit Adder/Subtracter
1. Full ADDER




4-bits ADDER




VHDL Code
   (一) 1-bit full adder
     A. Dataflow
       library ieee;
       use ieee.std_logic_1164.all;
       use ieee.std_logic_arith.all;
       use ieee.std_logic_unsigned.all;
       entity fulladder is
           port(a, b, ci : in std_logic;
                s, co: out std_logic);


                                           1
        end fulladder;
     architecture arch of fulladder is
       begin
        s<=(a xor b) xor ci;
        co<=((a xor b) and ci) or (a and b);
    end arch;


  B. Waveform




(二) 4-bits Full adder
     A. Behavioral
       Ex1:
           library ieee;
           use ieee.std_logic_1164.all;
           use ieee.std_logic_arith.all;
           use ieee.std_logic_unsigned.all;
           entity add4loop is
                 generic(n:integer :=4);
           port(ci : in std_logic;
                  a, b : in std_logic_vector(n-1 downto 0);
                  s: out std_logic_vector(n-1 downto 0);
                  co: out std_logic
                  );
           end add4loop;
           architecture arch of add4loop is
                 signal c: std_logic_vector(n downto 0);
           begin
                process(ci,a,b)
                  begin


                                               2
                 c(0)<=ci;
             for i in 0 to n-1 loop
                 s(i)<=a(i)xor b(i) xor c(i);
                 c(i+1)<=(a(i) and b(i)) or (a(i) and c(i)) or (b(i) and c(i));
             end loop;
           co<=c(n);
       end process;
  end arch;


Ex2:
       library ieee;
       use ieee.std_logic_1164.all;
       use ieee.std_logic_arith.all;
       use ieee.std_logic_unsigned.all;
       entity add4b is
           port(a,b: in std_logic_vector(3 downto 0);
                  ci: in std_logic;
                  s: out std_logic_vector(3 downto 0);
                  c0: out std_logic
                   );
            end add4b;
       architecture arch of add4b is
           signal tmp: std_logic_vector(4 downto 0);
         begin
           tmp<=a+b+ci;
           s<=tmp(3 downto 0);
           c0<=tmp(4);
       end arch;


B. Structure
  Ex1:
       library ieee;
       use ieee.std_logic_1164.all;
       use ieee.std_logic_arith.all;
       use ieee.std_logic_unsigned.all;
       entity adder4bstr is
          port( a,b: in std_logic_vector(3 downto 0);
                  ci: in std_logic;


                                           3
              s: out std_logic_vector(3 downto 0);
              co: out std_logic
           );
      end adder4bstr;
    architecture arch of adder4bstr is
         component fulladder
          port(a,b,ci: in std_logic;
                s,co: out std_logic);
           end component;
         signal c1,c2,c3: std_logic;
      begin
         u1:fulladder port map (a(0),b(0),ci,s(0),c1);
         u2:fulladder port map (a(1),b(1),c1,s(1),c2);
         u3:fulladder port map (a=>a(2),b=>b(2),ci=>c2,s=>s(2),co=>c3);
         u4:fulladder port map (a=>a(3),b=>b(3),ci=>c3,s=>s(3),co=>co);
    end arch;


C. Waveform




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