Block Design - Block Diagram

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Block Design - Block Diagram Powered By Docstoc
					Block Diagram Document
   CranCon Systems

      October 15th, 2007
   Editor: Brandon Sargent
       1.0 Level 0 Block Diagram

                                  Figure 1-0. Level 0 Block Diagram.

       The gantry crane control system will be driven by a 24 V DC power supply. The input to
       the system will be an analog signal varying between ±10 V. The output will be a 0 V to
       24 V square wave with a variable duty cycle determined by the value of the input. The
       output polarity is reversed if the input signal is negative. The output current must be at
       least 2 A. We will provide an auxiliary output signal between 4 mA and 20 mA that
       corresponds linearly to the analog input level.

       2.0 Level 1 Block Diagram

                                                                 Control output                                  4 mA – 20 mA control signal

                                                             HCS12 Microcontroller

  -10 to +10 V analog                        Digital reference
speed reference voltage                           voltage           Microcontroller        Pulse width
                             A-D converter                                                                 PWM output

 Limit switch inputs
                                                                                                         PWM square wave
(forward & reverse)

                                                                                                              24 V reversible-polarity PWM
24 V DC power supply                                                                                            square wave (up to 2 A)
                                                                                  H-bridge circuitry

                             Figure 2-0. Level 1 Block Diagram.

Figure 2-0 above is the level 1 diagram for the gantry crane control system. The
following sections below include an in-depth breakdown of each of the blocks in the level
1 diagram.

3.0 Analog to Digital Converter (ADC) Block

        -10 to +10 V analog
      speed reference voltage                                         Digital reference
   VRL – Low Reference Voltage                                             voltage
                                              A-D converter
   VRH – High Reference Voltage
                 VSSA – Ground
                  VDDA – 5 Volt

                              Figure 3-0. Analog To Digital Block.

The Bechtel project requires our system to accept an analog ± 10 Volt input to the
system. Jonathan Baisch will be working on programming and verifying the
functionality of the Analog to Digital Controller (ADC). To utilize this input voltage and
make it drive our system we needed to convert this analog signal into a digital value
which can be used in calculations. Most microcontrollers have an ADC and the HCS12
is no exception. The HCS12 has an eight-channel, multiplexed, 8-bit or 10-bit,
successive approximation A/D converter with ±1 least significant bit accuracy. This
converter operates by receiving high and low setpoint voltages (VRL & VRH) and from
these it creates a range of digital values which are used to generate analog potentials.
These potentials are compared against the analog input value and the matching or closest
matching generated value is used as the digital result. VDDA is the 5 Volt power input
which drives the analog circuitry and VSSA is the associated ground. The ADC can
complete a single channel 10 bit conversion in 7 μsec. It also has eight input channels,
however, we will probably only use one. The output of this system will be a 10 bit digital
value which will be used by Ryan Shaffer’s function to create a duty cycle for the PWM.

To test this module Jonathan will need to give an analog input voltage, two setpoint
voltages, and the power voltage of 5 Volts. Using the setpoint voltages he will determine
the correct resolution for the 10-bit digital output. Jonathan will then determine the
resolution and find the closest digital output. He will repeatedly input different analog
voltages and determine the correct digital output. This will be verified with the
microcontroller output utilizing LEDs or similar devices.

4.0 Microcontroller Function Block

Ryan Shaffer will be working on the microcontroller function block. The main input to
this block is a digital output from the A-D converter block, representing the value of the
analog speed reference input to the system. The limit switch inputs to the system will
also be fed into this block. The block has two outputs—pulse width and polarity. The

pulse width output represents the desired duty cycle of the system’s square wave output,
and it is sent to the PWM output block. The polarity output is sent to the H-bridge
circuitry and, as its name suggests, controls the polarity of the system’s square wave

The mathematical operation of the block is shown in Figure 4-0. The values
“+maximum”, “-maximum”, “-minimum”, “+minimum”, “-0db”, and “+0db” in the
figure are fixed constants to be defined in code, so in developing the mathematical
representation of the function, these symbols should be used as variables. By the
requirements, the dead band must be centered on 0 V, and so -0db and +0db must be of
equal magnitude.

    Figure 4-0. Duty cycle vs. input speed reference graph provided by Bechtel.

The duty cycle will be output as an 8-bit unsigned integer ranging from 0 to 255, where 0
represents a 0% duty cycle and 255 represents a 100% duty cycle. The polarity will be
output as either a 1 or a 0—1 representing positive polarity, and 0 representing negative

The limit switch inputs (two of them—forward and reverse) will override the normal
operation of the function and set the duty cycle to 0%. This happens if the limit switch
corresponding to the output polarity (i.e., forward or reverse) is closed. If both limit
switches are open, they are ignored, and the duty cycle is output normally.

This block will be tested in multiple ways. To test the software portion, which will be
written in C, we will use another C program as a driver for the function and simulate a
wide range of digital inputs, and when we plot these against the outputs, we should get a
graph nearly identical to the one shown in Figure 4-0. When this block is integrated with

the A-D controller block that precedes it, we will be able to test the full range of analog
inputs (-10 V to +10 V) in small steps (about 0.25 V) and verify that we output the
correct duty cycle and polarity for each input. We will also be able to test the limit
switches using mechanical switches as inputs to the microcontroller and verifying that
closing each limit switch disables the output of appropriate polarity. (Example: a -5 V
analog input with the negative polarity limit switch closed should result in a 0% duty
cycle on the output.)

5.0 Pulse Width Modulator Block

                           Pulse width                PWM square wave
                                         PWM output

                                    Figure 5-0. PWM Block.

Brandon Sargent will be working on the pulse width modulator block, which can be seen
above in Figure 5-0. The single input comes from the microcontroller function block’s
output and represents the required duty cycle for the pulse width modulated square wave
signal that the PWM block will produce as output. The output PWM signal will range
from 0V to 5V. The output will be the input to the H-Bridge block, which will eventually
generate the desired final 0V-24V PWM output signal.

The HCS12 microcontroller has a built-in and quite flexible PWM signal generator. Note
that all programming will be written in C. A total of 32 registers will need to be
programmed to set up the 8 channels of the PWM. The input signal will have to write to
the PWMDTY register to set up the duty cycle. In addition, the 8-bit, left-aligned, and
high polarity modes will have to be programmed using the PWMCTL, PWMCAE, and
PWNPOL registers respectively. Also, the period of the PWM signal will have to be
PWMCTL, PWMSCLA, and PWMSCLB registers. Though a 16-bit PWM is also
available, the 8-bit will be used because we will probably only need a single bit.

To test this module Brandon will need to input several different duty cycles and observe
the output via an oscilloscope to ensure that the required output signals are being

6.0 Control Output Circuitry Block

                           24 V DC power supply

                 -10 to +10 V analog
                                                             4 mA – 20 mA control signal
               speed reference voltage      Control output

                             Figure 6-0. Control Output Block.

Tim Stewart will be working on the control output circuitry block. The input is an analog
voltage signal ranging from -10 V to +10 V. The output of this block is a current control
signal ranging from 4 mA (correlating to the -10 V signal) to 20 mA (correlating to the
+10 V signal).

In order to obtain a current signal from a voltage, a resistance is required. However, it
may become tricky to try and obtain a positive current from a negative voltage. Some
kind of inverting op amp may be required to do this. A resistor, an inverting op amp, and
some kind of control circuitry that will indicate when the input polarity is negative will
probably be needed. Further development and thinking needs to be implemented
concerning this design decision, as there are several potential solutions. Tim needs to
make sure that the current is flowing in the correct direction, in spite of the voltage

It will be pretty easy to test this design. All Tim has to do is vary the input voltage to the
block and measure the current coming out of the block. Tim will then place a resistor at
the output and measure the voltage across it and then calculate the current, because it is
easy to mess up current measurements.

7.0 H-Bridge Circuitry Block

                                  Figure 7-0. H-Bridge Block.

Dale Weaver will be working on the H-Bridge circuitry block, which can be seen in
Figure 7-0 above. The H-Bridge design provides a ±24V DC PWM power output circuit.
Power inputs to the block are the overall 24V DC power source provided by the
preexisting Bechtel design and a 12 V DC source that will power the H-Bridge driver, a
HIP4080A. Signal inputs are shown at the top of the block: a polarity output from the
microcontroller block (0V = 0, 5V = 1) and the pulse width modulated signal (0V = 0, 5V
= 1) providing a duty cycle. The one and only output is a ±24V PWM power output
easily driving a motor load of 2A.

An H-Bridge circuit uses a driver and four MOSFETs acting as switches located around
the load. Figure 7-1 is a basic diagram demonstrating the concept of an H-Bridge. By
activating S1 and S4 the motor can be run in the forward direction. By turning S3 and S2
on, and turning S1 and S4 off, the motor can be run in the opposite direction. If any two
switches are at the top or bottom (S1 & S3 || S2 & S4) the motor will not run at all. With
fast propagation through the MOSFETs and the HIP4080A driver, the input PWM
control signal can turn on and off the output to the motor. Additionally, based on the
input polarity, the direction of the motor can be switched by the driver. The 24V power
supply will be across the four MOSFET switches. The MOSFETs will carry the 2A
motor load allowing for heat sinks if necessary.

                         Figure 7-1. Basic H-Bridge Diagram.

To test the H-Bridge functional block, a signal generator and DC power supply will be
used to simulate the expected output from the microcontroller. The signal generator will
provide a pulse width modulated signal which can be compared against the ±24V DC
output PWM signal viewable on an oscilloscope. A simple 5V DC power supply input
can simulate the polarity input to ensure that the H-Bridge switches polarity between 0-
24V and 0- 24V. A sample motor can be used with similar load specifications to ensure
it meets the 2A requirement from Bechtel.

The H-Bridge concept provides a very effective way of handling large loads, the ability
to switch output polarity, and can be soft-switched by the microcontroller. Alternative
options provided similar features but not all three at the same time. For example, when
using separate stages for amplification and pulse width modulation the motor load would
be acceptable, but switching polarity would require an additional stage. These stages
would also require the ability to be soft-switched by the microcontroller. The H-Bridge
design is proven with many available examples and it was used in the design in the
embedded systems robot last semester.

8.0 Design Decisions – Microcontroller Selection

One of the biggest design decisions in this project was microcontroller selection. There
were several options for the microcontroller. Jonathan Baisch researched a
microcontroller, the TI TMS470R1B1M. This microcontroller was a 32-bit device and
fully capable of performing all functions necessary for this project. The microcontroller
was removed as a possibility for three reasons. First, after talking to Dr. Mohr the project
would probably only need an 8 or 16-bit microcontroller. Secondly, our design team had
experience with the HSC12 from last year’s embedded systems course, so we all know
how to program it and its available features. Finally, the TI microcontroller was almost
double the cost for the chips and the development board than the TI microcontroller, and
cutting cost is always a plus in industry. Furthermore, Brandon Sargent also researched
and investigated into a potential microcontroller. This was the MC68332, which is a
highly-integrated 32 bit microcontroller that combines high-performance data
manipulation capabilities with powerful peripheral subsystems. However, this potential
microcontroller was also discounted for similar reasons to the TI TMS470R1B1M.


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