RadHard Mixed-Signal ASICs by jlhd32


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									RadHard ASIC Products
RadHard Mixed-Signal ASICs
July 2007

INTRODUCTION                                                              SEU-immune to less than 1.0E-12 errors/bits-day available
                                                                          using special library cells
Aeroflex Colorado Springs’ RadHard Mixed-Signal ASICs
combine high-density, high-speed digital logic with analog and            Variety of standard ceramic flat-pack and column grid array
mixed-signal functions on the same monolithic die. Leveraging             packages, or full custom package design available, including
from our commercial mixed-signal design library, our radiation            Plug & SenseSM modules with sensor integrated into
hardening technology, and the capabilities of our QML approved            package
foundry partners, Aeroflex can meet the most complex mixed-
signal requirements.
                                                                          External chip capacitor attachment option available to space
                                                                          quality levels (for improved SSO response)
Aeroflex provides full turn-key mixed-signal design, including
specification development. Our tools and libraries allow us to         Level 1 - Turnkey Design: In cooperation with the customer,
efficiently design ASICs to high-reliability specifications. Our       we develop an ASIC specification from a system specification,
flow allows you the flexibility to choose how best to complete         and perform all detailed design (analog schematics, digital
your ASIC project.                                                     netlist). We assemble a design and development team that
                                                                       includes analog and digital circuit designers, layout engineers,
Table 1 lists the RadHard Mixed-Signal technologies and                test and product engineers, as well as Manufacturing, Reliability
attributes available. Figure 1 describes the design flow.              and QA resources to create a device that meets your
                                                                       specifications. We can also translate your obsolete parts into one
                                                                       of our existing RadHard technologies. Aeroflex chooses a
   Wide range of mixed-signal technologies and attributes              capable process technology in one of our QML-Q and QML-V
   available: 0.6μm, 0.35μm, 0.25μm, and 0.18μm silicon gate           approved wafer foundry fabrication facilities and complete the
   CMOS                                                                assembly, screening, test and qualification processes in our
                                                                       QML-V qualified on-site facility.
   Up to ~10,000,000 usable equivalent gates (0.18μm)
   Toggle rates up to ~2GHz                                            Level 2 - Specification & Netlist Handoff: Aeroflex integrates
                                                                       customers' digital netlist with Aeroflex analog/mixed-signal
   Operating voltage of 10V (0.35μm), 5V and/or 3.3V                   cells to create a design that meets the specification using the
   (0.35μm and 0.18μm)                                                 customer's netlist.
   5-volt compliant I/O buffers in all technologies
                                                                       Level 3 - Co-designed Products: Aeroflex performs layout and
   Supports cold sparing for power down applications                   physical design of customer’s analog schematic and digital
                                                                       netlist, including place and route, back-annotation, and timing
   Analog IP cores (ADC’s, DAC’s, PWM’s, comparators, Op-              closure. Full-chip, mixed-mode simulations performed,
   amps, voltage regulators, Analog Muxes, PLL, RC oscilla-            including Safe Operating Area (SOA) analyses. SEE consulting
   tors/VCO’s, POR and others) and/or full-custom analog               available during design phase. Aeroflex performs all design
   design with custom digital filters for signal processing            integrity checks including analysis and verification of DRC,
                                                                       LVS, then manufactures the device, performing electrical test,
   Full complement of digital IP cores including microcontrol-         environmental screens, and qualification. (NOTE: Execution of
   lers, microprocessors, interface controllers, memory                three-way NDA’s with foundry/and or third-party IP providers
   controllers                                                         may be required. Execution of license agreement to obtain
                                                                       access to Aeroflex proprietary RadHard models required.
   Configurable RAM compilers
   Multiple product assurance levels available, QML Q and V,
   military, medical, industrial
   Radiation hardened from 100 krads(Si) to 1Megarad total
   dose available using Aeroflex Colorado Springs RadHard

 TECHNOLOGY                        90nm CMOS               130nm CMOS             180nm CMOS                0.25μm CMOS              0.35μm CMOS              0.6μm CMOS
 Metal Layers                      6-9 Cu                  6-8 Al/Cu              5-6 Al/Cu                 4-5Al/Cu                 3-4 Al/Cu                3Al/Cu

 Capacitors                        MiM                     Mim                    MiM                       Mim                      MiM/PiP                  PiP

 High-value resistors              No                      Yes                    Yes                       Yes                      Yes                      Yes

 Vertical NPN bipolar              No                      No                     Yes                       Yes                      Yes                      Yes

 Substrate PNP bipolar             Yes                     Yes                    Yes                       Yes                      Yes                      Yes

 HV CMOS support                   No                      No                     5V (self-aligned)         Yes                      10V (self-aligned)       20V (ext drain)

 Thick metal inductor              No                      Yes                    Yes                       No                       Yes                      No

 Digital/analog supply volt-       3.3, 2.5, 1.8, 1.2,     3.3, 2.5, 1.8, 1.5,    5.0, 3.3, 1.8             3.3, 2.5                 10.0, 5.0, 3.3           5.0, 3.3, 2.5
 ages (DVdd, AVdd; Vss=0           1.0                     1.2

 Alternate analog supply                                                          +2.5, +1.65, +0.9                                  +5, +2,5, +1.65
 voltages (AVdd/AVss)

 Maximum toggle frequency          33GHz                   5GHz                   2.4GHz                    1GHz                     375MHz                   215MHz

 Power dissipation - nW/           7                       10                     20                        40                       150                      320
 gate - MHz; 20% duty cycle

 Gate delay 25oC (ps)              6                       20                     50                        65                       140                      225

 Usable gates (NAND2               15-20M                  10-15M                 8M                        3M                       1.5M                     500K

 Typical signal I/O                ~1024                   ~1024                  ~1024                     ~512                     ~425                     ~400

 Flip-chip I/O available           Yes                     No                     Yes                       No                       No                       No

 Cold sparing                      Yes                     Yes                    Yes                       Yes                      Yes                      Yes

 Full 5V compliance                No                      No                     Yes                       No                       Yes                      Yes

 Cold sparing/5V tolerance         Yes                     Yes                    Yes                       Yes                      Yes                      Yes

 Example analog IP (full                                                          Band-gap, Volt. reg.      Band-gap, Volt, reg.     Band-gap, Volt. reg.     Band-gap, Volt. reg.
 custom analog available)                                                         Comp/op-amps,                                      Comp/op-amps,            Comp/op-amps,
                                                           ADCs, DACs             ADCs                      ADCs, DACs               DACs
                                   PLL                     PLL                    PLL, VCO                  PLL                      PLL, VCO                 PLL/DLL
                                                                                  RC oscillator

 SRAM compiled                     Yes                     Yes                    Yes                       Yes                      Yes                      No

 Non-volatile memory                                                              Flash* EEPROM*                                     Flash* EEPROM*
                                                                                  RadHard OTP                                        RadHard OTP
                                                                                  Metal Fuse**                                       Metal Fuse**

 Special I/O                       SSTL, MGT,              SSTL, MGT,             SSTL, MGT,                SSTL, MGT,               SSTL, MGT,               SSTL, MGT,
                                   CML, LVDS,              CML, LVDS,             CML, LVDS,                CML, LVDS,               CML, LVDS,               CML, LVDS,
                                   PCI, PLL                PCI                    PCI, USB1.1               PCI                      PCI, RS232/              PCI
                                                                                                                                     RS485 (+5V),

 Total Ionizing dose Rads(Si)      100-300K                100-300K               100-300K                  100K-1Meg                100-300K                 100-300K

 SEL (MeV-cm2/mg) @Vdd             >100                    >110                   >110                      >110                     >110                     >128
 max and 125oC

 Reliability (FIT rate)            <50                     <20                    <10                       <10                      <10                      <5

 Wafer foundry quality level       ISO-9001                QML-Q&V                QML-Q&V                   QML-Q&V                  QML-Q&V                  QML-Q&V

 Trusted foundry level             ITAR/CCI                ITAR/CCI               N/A                       Classified               N/A                      ITAR
                                   planned                 planned

* Limited total-ionizing dose environments. Floating Gate Memories such as Flash and EEPROM must be periodically re-written in a total ionizing dose environment for reliability.
** QML-V Qualification 1Q2008


              Database                          Initial Design Review

           Block Diagram/                       Preliminary Design

Digital                      Digital Design                              Analog Design                    Analog
Library                                                                                                   Library

                                                 Full Chip Design and
                                                   Physical Layout

    Test              Test                                                                              Layout
                                                 Physical Verification                   GDSII
                   Developmen                                                                          Database

           CDR                                     Critical Design

      CDR Package/
      Results/Physical                             Mask Generation

                                                  Wafer Fabrication

                             Production Test                               Packaging


                                                                                       Figure 1. RadHard Mixed-
                                              Proof of Design/Production                  Signal Design Flow
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www.aeroflex.com                             info-ams@aeroflex.com

Aeroflex Colorado Springs, Inc., reserves the right to make
changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
any responsibility or liability arising out of the application or
use of any product or service described herein, except as
expressly agreed to in writing by Aeroflex; nor does the
purchase, lease, or use of a product or service from Aeroflex
convey a license under any patent rights, copyrights,                                          Our passion for performance is defined by three
trademark rights, or any other of the intellectual rights of                                       attributes represented by these three icons:
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