Fulcrum Microsystems was founded in 2000, based on research from California Institute of Technology, to
develop "a series of standards-based chips leveraging its patented high-performance, low-power 'clockless'
semiconductor design methodology." Fulcrum will apply its patented clockless design methodology "to deliver
semiconductors that are differentiated from traditional clocked chips by their high performance and improved
The company secured $6 million in initial funding. In August 2001, Fulcrum secured $16 million in Series B
funding co-led by Infinity Capital, New Enterprise Associates and Worldview Technology Partners. In June
2003, Fulcrum raised $14 million in an oversubscribed third round of funding, led by new investor Palomar
Ventures, and including existing investors Infinity Capital, New Enterprise Associates, and Worldview
Technology Partners. The company has raised $36 million to date and has 30 employees.
Most ICs use a central clock to coordinate the movement of data through the chip. Without a central clock,
chips designed using Fulcrum's technology consume significantly less power, integrate increased functionality
into the chip more easily, and reduce semiconductor design times, all while achieving Gigahertz performance.
Building on research conducted at Caltech by the company's founding team, Fulcrum claims to have developed
the industry's first high-performance clockless semiconductor design methodology. Previously, clockless
semiconductors were used only for their low power benefit, stemming from the elimination of the inefficient
clock tree and the benefit provided by built-in circuit-level clock gating. Leveraging its patented clockless
design methodology, Fulcrum has taken asynchronous design to new performance levels while still maintaining
the power efficiency of perfect clock gating, and reliable operation over an extremely wide range of operating
Fulcrum refers to its high-performance asynchronous circuit architecture as Integrated Pipelining, which
enables Gigahertz-performance ASICs that are not saddled by integration limitations associated with long
wires. By removing all timing dependencies from the circuit, long wires can be "pipelined" at any stage of the
design process. Characterization results of its first devices verify that instead of having as much as 80% of the
chip performance determined by wire delay (as is the case with ASICs manufactured in today's 130nm process),
its delay-insensitive designs reduce delay attributed to wires to less than 30%.
Fulcrum's Integrated Pipelining is based on a fast delay-insensitive style using domino logic without
latches. The technology uses a dual-rail, four-phased handshake. The technology addresses delay variability
with completion sensing, and power efficiency with asynchronous handshakes. It also leverages more efficient
Fulcrum team members have designed and fabricated several delay-insensitive async chips while at Caltech,
including an FIR filter in 1995 and a MIPS32 instruction set-compatible processor in 1998. Since then, the
company has fabricated and characterized several large-scale chip projects, including a 450MHz, 180nm 13M
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transistor proprietary processor architecture, some of which were conducted on behalf of partners, and all of
which achieved first-pass success.
Based on actual characterization data, Fulcrum's Terabit crossbar circuit, which was fabricated in TSMC's
130nm process, delivers extremely high performance (1.4GHz at nominal voltage, which is comparable to
aggressive full-custom synchronous designs) over a wide voltage range (well beyond the operating range of
synchronous designs) and temperature range.
Fulcrum believes that its technology also provides for a deterministic design cycle allowing schedules to be met
and chips to be delivered with features and performance as initially specified. The company claims to have
developed several devices in less than half the time required using conventional circuit design techniques and
offering more than 3x the performance and 2x the level of integration of equivalent-generation ASICs.
PivotPoint, Fulcrum's first commercial product, is a SPI-4.2 switch chip for board-level system interconnect
applications. PivotPoint replaces discrete daisy-chain designs and inflexible system buses, converting a fixed
hardware configuration into a soft-assignable array of computing and packet processing resources.
PivotPoint provides soft allocation of processing resources on an application-by-application basis. Resources
formerly restricted to an ingress data path, for example, can now access data on the egress data path. PivotPoint
can also cut system costs in some applications by up to 25% by eliminating FPGA glue logic and reducing the
amount of processing resources required in the system, since the resources can be soft-allocated for optimal
The first member of the PivotPoint board-level switch family, the FM1010, is designed for high-performance
networking, storage and computing applications and features six System Packet Interface 4 Phase 2 (SPI-4.2)
interfaces, a configurable generic CPU interface for channel and queue configuration and status monitoring, and
a standard IEEE 1149 JTAG interface for test and debug purposes.
At the core of PivotPoint is Fulcrum's Nexus crossbar switch, which utilizes Fulcrum's high-performance
"clockless" design technology. Nexus ha a total switching capacity of 1.6 Tbps, and delivers 192 Gbps of
sustained non-blocking throughput in the six-port PivotPoint FM1010. This capacity is more than twice the
aggregate bandwidth of the SPI-4.2 interfaces, which can independently operate at speeds up to 14.4 Gbps.
Nexus also gives PivotPoint an ultra-low 3ns of switching and arbitration latency for instantaneous flow control
response. Flow control is further enhanced by PivotPoint's three-stage decoupled flow control architecture,
which addresses congestion at the egress buffer, the switch arbiter, and the ingres buffer. The fine-grain flow
control eliminates buffer overflows and port starvation, providing smooth operation in even the most congested
PivotPoint consumes power linearly with activity to a maximum power consumption of two watts per active
interface at 14.4 Gbps. Fulcrum's clockless design style results in perfect clock gating (on a circuit-by-circuit
basis), resulting in a reduction in average power consumption of up to 25%, compared to clocked designs.
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The FM1010 has more than 32M transistors and 14 separate clock domains, and operates at over 1 GHz. In
addition to the six SPI-4.2 interfaces and the Nexus Terabit Crossbar, the device integrates a quad-port 600MHz
async SRAM. The PivotPoint FM1010 SPI-4.2 switch will be available in a 1036-ball BGA package. The
FM1010 was developed in nine months; samples in November; general availability in January 2004; $225 @
1Ku. The company has interest from roughly 20 potential companies to date and has already sold a half a dozen
Future versions of PivotPoint will feature additional interfaces and will continue to focus on efficiently linking
the data plane with the "midplane." Fulcrum will also license the Nexus crossbar switch to select
companies. While we find PivotPoint to be a truly unique and useful device, we wondered about the potential
market size. Fulcrum sees it as a potential $5 to $10 million opportunity, which naturally implies that the
company will need to develop additional product families.
Bob Nunn, president and CEO (previously GM of Vitesse's Telecom Products Division)
Uri Cummings, co-founder and VP Product Development (currently a Caltech PhD candidate)
Andrew Lines, co-founder, VP, and CTO (PhD candidate at Caltech)
Dr. Peter Beerel, VP of Strategic CAD (Associate professor at the University of Southern California Computer
Alain Gravel, VP of Engineering (previously VP of Engineering at ACT Networks and Clarent after its
acquisition of ACT)
Dave Markowski, VP of Business Development (previously worked in sales at Cisco, as a result of Cisco's
acquisition of StratumOne, where he served as VP of Worldwide Sales)
Mike Zeile, VP of Marketing (previously co-founder and VP of Business Development at Encryptix. Before
Encryptix, he held corporate VP positions at ACT Networks, Comcore Semiconductor, and ADC Telecom)
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