Docstoc
EXCLUSIVE OFFER FOR DOCSTOC USERS
Try the all-new QuickBooks Online for FREE.  No credit card required.

etri_day2

Document Sample
etri_day2 Powered By Docstoc
					        XC9500 CPLDs

“Supporting the Total Product Life Cycle”

 1
               Technical seminar
              Designer's Needs

     In-System Programming
     Enhanced Testability
     Design changes without PCB changes
     Mixed 5V/3.3V I/Os
     High endurance reprogramming
     Multiple speeds/densities in identical
      pinouts and packages
2
                   Technical seminar
The Industry’s First 5V Flash CPLD
     5 V In-System Programming (ISP)
     High performance
       — 5ns pin-to-pin speed
       — 125 MHz count frequency
     Large density range
       — 36 to 288 macrocells (Phase 1 family)
     Flexible architecture
       — optimized for pin-locking
       — global and product term clock, set/reset, OE
     Most complete IEEE 1149.1 (JTAG)

     Highest reprogramming endurance
3
       — 10,000 program/erase cycles
                     Technical seminar
                Smaller Cell Size with FastFLASH

                 Typical E2 CPLD Cell                                                    FastFLASH Cell
                                   Control

                Write       Data                                                           Data
                                   Ground
Word Line
                                                                 1/3         Word Line              Source

                                                                                                    Data

  Control
                 Floating
                                   Data
                                                                Area           Control

                                                                                                             Control
                                                                                                                       Word
                   Gate                                                                                                Line
                        Ground                                                             Source
                                   Write

                                             Word Line




             Product benefits due to smaller cell
               4 More routing switches in the same area supports
                  pinlocking
               4 Lower parasitic capacitance improves performance
               4 Long term cost improvements due to scalability

            4
                                                         Technical seminar
    XC9500 Architectural Features

 Predictable, all pins fast, PAL-like architecture
 FastCONNECT switch matrix provides 100%
  routing with 100% device utilization
 Flexible function block
   — 36 inputs with 18 outputs
   — product term expansion with up to 90
      product terms per macrocell
   — global and product term clocks
   — global and product term 3-state enables
   — global and product term set/reset signals

5
                   Technical seminar
                   XC9500 Architecture
                       3
                             JTAG                     In-System
       JTAG Port           Controller           Programming Controller




                                                              Function
       I/O                                                     Block 1

       I/O
                                                              Function
       I/O                                                     Block 2
                                I/O       FastCONNECT
       I/O                 Blocks         Switch Matrix

I/O - Global                                                  Function
                                                               Block 3
   Clocks          3
I/O - Global
 Set/Reset             1
                                                              Function
I/O - Global                                                  Block n
 Tri-States
                       2 or 4




   6
                                      Technical seminar
              FastFLASH Function Block
                                   Global        3   Global    2
                                   Clocks            3-State
                                                                   I/O
                                      Macrocell 1




                       Product-
               AND
                         Term
               Array
                       Allocator
     36

    From
FastCONNECT




                                      Macrocell 18                 I/O
     To
FastCONNECT

      7
                             Technical seminar
                     XC9500 Macrocell

              to/from other macrocells



    From
FastCONNECT                           SUM-Term
                                        Logic
         36                                       XOR       Register        18
                                                            D/T   Q
                       P-Term
                       Allocator                             R S
                                    P-term Clk
                                    P-term R&S
                                    P-term OE




                                                   3               2 or 4
              to/from other macrocells
                                            Global     Global Global
                                            Clocks      R/S    OEs




     8
                                   Technical seminar
    XC9500 Advanced Macrocell
              From Upper       To Upper
              Macrocell        Macrocell




                                            Global S/R




                                           Global CLKs




                                            Global S/R


                                                Product Term OE



         From Lower        To Lower
         Macrocell         Macrocell
9
                      Technical seminar
                 Flexible Cascading

                                            Forwards 3
                                            p-terms,
 Fast                                      retains 2
                                            p-terms

 Bi-directional cascade
     —   collects/delivers available p-terms Forwards 5
                                            p-terms

 Automatically controlled
  by software                                             Macrocell
                                            Delivers 5    Logic
 One p-term granularity level              p-terms       with 18
                                                          p-terms




                                            Delivers 5
                                            p-terms



10
                               Technical seminar
            Feedback Paths
 FastCONNECT
 Pin
                 FastCONNECT
 Local                                         FB X
                                             Macrocell


                                             Macrocell

                                             Macrocell
                                     Local feedback

                FastCONNECT feedback

                                               Pin feedback

 11
                       Technical seminar
              Complete Interconnectivity
                with FastCONNECT™
     Global                                                  Global
      S/R                                                    3-State

                         Function      Function
                          Block         Block



              Function      FastCONNECT           Function
               Block                               Block




              Function                            Function
               Block                               Block



                         Function      Function
                          Block         Block
                                                             Global
     JTAG                                                    Clocks



12
                            Technical seminar
     Restrictive Max7000/S
         Interconnect
                                                 1

                                                 2

                                                 3

                                                 4



                                                36

         Pin Inputs
       (~ 2 entries / LAB)
                                   Macrocells
                                 (~2 entries / LAB)

13
                    Technical seminar
     XC9500 FastCONNECT
                                                   1

                                                   2

                                                   3

                                                   4



                                                   36
         Pin Inputs
        (~ 3 entries / FB)
                                Macrocells
                               (36 entries / FB)

14
                  Technical seminar
            What is Pin-Locking?

  Ability to retain device pin assignments for
   small to medium design changes
     —   introducing a new variable to existing terms
     —   adding input signals
     —   inverting signals
     —   introducing 1or 2 buried flip flops
     —   adding p-terms

  Requires a symmetric, uniform architecture

  Requires software focus on pin-locking



15
                       Technical seminar
        Pin-Locking is Key for ISP

 Must retain pinouts as the design evolves
     — best done when the design software initially assigns
       pins
     — different from pinout pre-assigning
     — strong function of utilization in typical CPLD
       architectures
     — result of both architecture and software strategy

 Pin-locking is valuable
     — eliminates or reduces PC Board rework
     — minimizes time to market, saves money
     — lowers designer frustration, risk



16
                      Technical seminar
       Leading Edge Features Support
        Superior Pin Locking for ISP
3X more routing switches
- superior input/feedback routability

                                                                           Largest block fan-in
                                                                              - 36 direct inputs
                    FastCONNECT                       Function Block
                                                                              - wired-AND provides extra
                                                                                           logic/more fan-in
                                                                          I/O Block
                                        36




                                                                          I/O Block

                                        36




                                         Wired-AND       Function Block
                                         Capability




                                              Powerful bi-directional logic allocation
                                                 - any number of p-terms (up to 90 max.)

 17
                                   Technical seminar
   XC9500 Supports Design Changes
          with Fixed Pinouts

Design Change                       XC9500 Feature

Add another input                       FastCONNECT switch
matrix
 pin or FB output                   with 100% connectivity

Add more logic in                  XC9500 allows expansion
 the macrocell                      up to 90 P-terms

Add additional input               36 total inputs are available
 connections to the FB              plus FastCONNECT AND
                                    gate capability

  18
                         Technical seminar
            XC9500 System Features

 Enhanced Data Security Features
      — Read security bits prevent unauthorized reading
      — Write security bits prevent accidental program/erase
 Reduced power option per macrocell
 3.3v/5v outputs                                             Additional Ground Pin
                                                              • Lower ground inductance
                                                              • Reduce ground noise
 24 mA, 100% PCI compliant                  Internal Logic


 Output Noise Reduction                                                 User Programmable
                                                                          Ground Pin
      — Slew rate control                                              User I/O Pin

      — User programmable ground pin
                                                                       User I/O Pin
        capability
                                                                         Ground Pin




 19
                         Technical seminar
      Advanced System Features
  Enhanced Data Security Features
    — Read security bit prevents unauthorized reading
    — Write security bit prevents inadvertent user
       program/erase
  System Power Reduction
    — Reduced power option per macrocell
  Output drive capability
    — 3.3v/5v outputs
    — 24 mA, 100% PCI compliant outputs
  Output Noise Reduction in High-Pincount PQFP
   Packages
    — Slew rate control
    — User programmable ground pins


20
                    Technical seminar
           Planned FastFLASH™ CPLD Family
                                          0.6µ Phase I Family                          Phase II Expansion


                XC9536   XC9572   XC95108     XC95144   XC95180    XC95216   XC95288   XC95432   XC95576


Macrocells        36       72       108         144       180        216       288       432       576

Usable
                  800     1600     2400         3200      4000      4800      6400      9600      12800
Gates

tPD (ns)          5        7.5      7.5         7.5        10        10        10        12        15


Registers         36       72       108         144       180        216       288       432       576

Max. User
                  34       72       108         133       168        168       192       240       240
  I/Os

Packages         44PC
                 44PQ
                         84PC      84PC
                         100PQ     100PQ       100PQ
                                   160PQ       160PQ     160PQ      160PQ
                                                         208PQ      208PQ     208PQ
                                                                              304PQ     304PQ     304PQ




           21
                                               Technical seminar
       The Next Generation CPLD
 The Industry’s first 5V Flash CPLD
 Highest program/erase reliability of 10,000
  cycles
 The best Pin-Locking CPLD architecture
 Most complete manufacturing and engineering
  JTAG support


   Support for the Total Product Life Cycle

  22
                     Technical seminar

				
DOCUMENT INFO
Shared By:
Categories:
Tags:
Stats:
views:6
posted:1/3/2011
language:English
pages:22