SESSION 2 CMOS ESD by hcj

VIEWS: 25 PAGES: 4

									SESSION 2: CMOS/ESD
Monday, April 24, 1:30 p.m. ~ 5:40 p.m.
Ballroom B


Co-Chairs: Clement Wann (IBM, USA)
           Jack Sun (TSMC, Taiwan)
1:30 p.m.
T21 Uniaxial Process Induced Strained Si: Extending the CMOS Roadmap
     (Invited)
     Scott Thompson
     University of Florida, USA
     Uniaxial process induced stress is a key enhancement to planar CMOS for 90,
     65 and 45 nm technology nodes. In this work, we look at the history of
     strained Si, the physics behind some strained Si experimental data, and the
        state-of-the-art of strained Si devices in commercial production. The talk
        covers insight into the physical mechanisms responsible for hole and electron
        mobility enhancement and shows the importance of reduced mass (as opposed
        to reduced scattering) to enhance performance in nanoscale devices. Lastly,
        the maximum Si inversion layer hole and electron mobility enhancement will
        be estimated along with key scaling issues for sub 45nm technology nodes.


2:00 p.m.
T22 Optimization of Source/Drain Extension for Robust Speed Performance to
    Process Variation in Undoped Double-Gate CMOS
    Ji-Woon Yang, Daniel Pham, Peter Zeitzoff, Howard Huff, and George Brown
    SEMATECH, USA
     The speed performance of undoped double-gate CMOS with a gate to
     source/drain underlap structure is investigated using a 2D device and compact
     model simulation. The gate to source/drain underlap structure yields optimal
     characteristics and shows robustness to process variation when the structure is
     optimized.


2:25 p.m.
T23 Mo Gate Deformation Induced by Laser Annealing Process
    1,2
        Kentaro Shibahara, 1,2,3Akira Matsuno, 1,2Masaki Hino, and 2Ken-ichi Kurobe
    1
      Research Center for Nanodevices and Systems, Hiroshima University, Japan
    2
      Graduate School of Advanced Sciences of Matter, Hiroshima University, Japan
    3
      Phoeton Corp, Japan.
     Laser annealing is a promising candidate for ultra-shallow junction formation.
     However, melt-annealing that utilizes fast recrystallization to achieve
     non-equilibrium activation tends to cause undesirable melting in area portions
     other than the junction areas. In this paper, deformation of Mo gate is discussed
     through experimental and simulation work.


2:50 p.m.
T24 Low-Leakage Diode String Design without Extra Circuits for ESD
    Applications
    Shao-Chang Huang, Yu-Hung Chu, Chen-Chi Kuo, T.Y. Huang, M.H. Song and
    Mi-Chang Chang
    TSMC, Taiwan
    A novel low-leakage diode string design using separate diode objects in 0.18μm
    CMOS processes is proposed in this paper. Diode strings can be divided into
     two (or three) groups with only a large shallow trench isolation (STI) used as
     spacing. With STI used to separate the groups, the diode string successfully
     prevents excessive current leakage. The turn-on voltage of the diode string can
     be derived from the equations calibrated with the experimental results.


3:15p.m.
T25 Investigation on RF Characteristics of Stacked P-I-N Polysilicon Diodes for
    ESD Protection Design in 0.18-µm CMOS Technology
     Yu-Da Shiu, Che-Hao Chuang, and Ming-Dou Ker
     Industrial Technology Research Institute, Taiwan


     An ESD protection design by using the stacked diodes for CMOS RF integrated
     circuits is proposed to reduce the capacitance. The RF S-parameters and ESD
     robustness of the stacked P-I-N polysilicon diode are investigated. This robost
     ESD is fully process compatible to general CMOS process without extra process
     modification.


3:40 p.m. Coffee Break


4:00 p.m.
T26 65nm SOI CMOS Technology for High Performance Microprocessor
    Application
    Samuel K.H.Fung, P.A.Grudowski1, C.H.Wu, V. Kolagunta1, N. Cave1,
    C.T.Yang, S.J.Lian, V. Adams1, O. Zia1, B. Min1, N. Grove1, K.H.Chen,
     W.J.Liang, D.H.Lee, H.T.Huang, J. Cheek1 and H.C.Tuan
     TSMC, Taiwan
     1
       Freescale Semiconductor, USA
     This paper presents a state-of-the-art 65nm SOI CMOS transistor technology
     target for high performance microprocessor application. N/PFET shows short
     channel control meeting manufacturing margin at 32/35nm respectively. By
     using Dual Contact Etch Stop Layer (CESL) process, PFET Ion is higher than
     90nm node. The 65nm technology also offers SRAM cell sizes ranging from
     0.499µm2 to 0.64µm2 for various speed and density requirement.


4:25 p.m.
T27 A Promising Planar Transistor with in-situ Doped Selective Si Epitaxy
    Technology (GORES MOSFET) for 32nm node and beyond
     Y. Kikuchi, Y. Tateshita, T. Kataoka, J. Wang, Y. Miyanami, N. Yamagishi, T.
     Ikuta, Y. Yamamoto, S. Hiyama, H. Ugajin, H. Ikeda, S. Fujita, R.Yamamoto, S.
     Kanda, T. Imoto, S. Kashiwadate, Y. Tagawa, H. Iwamoto, T. Ohno, T.
     Kobayashi, M. Saito, S. Kadomura and N. Nagashima
     Sony Corporation, Japan
     We demonstrated 40nm gate length “Gate Overlapped Raised Extension
     Structure: GORES MOSFET” without halo implantation to demonstrate that the
     ultra shallow junction (USJ) does not compromize parasitic resistance in
     GORES MOSFET. Short channel effect is thus improved.


4:50 p.m.
T28 Strain-Induced Channel Backscattering Modulation in Nanoscale
     CMOSFETs
     Hung-Wei Chen, Hong-Nien Lin, Chih-Hsin Ko, Chung-Hu Ge, Horng-Chih
     Lin, Tiao-Yuan Huang, and Wen-Chin Lee
     TSMC, Taiwan
     The channel backscattering ratios as well as the ballistic efficiency of strained
     CMOSFETs were studied for both nondegenerate and degenerate-limited cases.
     We found that the simple nondegenerate assumption can predict strain-induced
     change of ballistic efficiency with fair accuracy. The mechanism of drain current
     dependence on strain-induced mobility change was also investigated based on
     channel backscattering theory.


5:15 p.m.
T29 PSDG MOSFET
Deyuan Xiao, Gary Chen, Roger Lee, Daniel Lu, Leong Tan, Yung Liu, CC Shen
Semiconductor Manufacturing International (Shanghai) Corp., China


In this paper, we introduce a novel planar split dual gate MOSFET device (PSDG
MOSFET) which enables independent biasing and provides the ability to
dynamically adjust the threshold voltage and sub-threshold swing (SS). The
device structure, physics and characteristics as well as the simulation and
experimental results are described.

								
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