A NEW LOW POWER HIGHER BANDWIDTH CURRENT MODE DESIGN OF ANALOG SIGNAL MULTIPLIER Mr. U. B. S. CHANDRAWAT Lecturer, EI Engg. Deptt,, S.G.S.I.T.S Indore, M.P. 452003, India Dr. D. K. MISHRA Proff. & HOD of EI Engg. Deptt, S.G.S.I.T.S., Indore, M.P. 452003, India. Mr. ADITYA VELLORE Lecturer, EI Engg. Deptt,, S.G.S.I.T.S Indore, M.P. 452003, India Mr. AFTAB BEIG MTECH (MICROELEX. & VLSI DESIGN), EI ENGG. DEPTT, S.G.S.I.T.S., INDORE, M.P. 452003, INDIA. ABSTRACT: This paper presents a research work on a analog signal multiplier using current conveyor. Normally, we make a multiplier by using op-amp. The major problem with these analogue multipliers is the limited bandwidth for many signal processing applications. The proposed building block introduces a technique, based on current-conveyor, suitable for the design of a high frequency bandwidth analogue multiplier. Since a current mode circuit has greater advantages over a voltage mode circuit like large gain, more linearity, higher slew rate etc, we can replace the OP-AMP by a current mode circuit i.e. by a current conveyor. The most advantage of this circuit is the large bandwidth. Here we using a differential difference current conveyor which has better linearity, gain & bandwidth with a differential input facility as compare to other current conveyor circuit like CCI, CCII, etc. We design a Full-Differential CMOS Analog Multiplier using Current Conveyors with rail to rail voltage of ±2.5 volt & 85 MHz bandwidth in 0.5 um technology using tanner tool. The power consumption is about 4.2mW from a ±2.5V power supply voltage, and the total harmonic distortion is 1.23% with a 1V input signal.