C MO S O PE R ATI O NAL A M PLIFI E R DE S I G N PRO J E C T EECS 413 December 15th, 2000 Joseph A. Potkay OVERVIEW The CMOS operational amplifier shown below was designed to achieve the specifications given in the “Performance” section and, in general, is a low power, moderate gain, and fast settling time operational amplifier consisting of three stages. The first stage provides of the biasing circuitry for the amplifier. Transistors M10 and M11 provide the gate bias voltage of transistor M9 and, in doing so, sets its “on” resistance. Transistors M12, M13 and M14 are simply used to decrease the voltage drop across resistor Rref, which sets the current for this stage. This current sets the gate voltage of transistor M8, and this gate voltage is used as a gate bias voltage for the transistor current sources, M5 and M7, which bias the second and third stages of the amplifier. VDD=+2.5V M8 M5 M7 18u/0.8u 54u/0.8u 2.4u/0.8u Rref M1 M2 40k (-) (+) M12 66u/0.8u 66u/0.8u 1.2u/2.4u M13 1.2u/2.4u M14 Cc 1.2u/2.4u Vout M9 M10 0.443p CL 40u/0.8u 2p 8u/0.8u M6 M11 M3 M4 64u/0.8u 14u/0.8u 14u/0.8u 8u/0.8u VSS=-2.5V Figure 1 The complete CMOS operational amplifier circuit. The second stage of the amplifier is the first gain stage and provides the differential input for the op-amp. Transistors M1 and M2 are the drivers for this stage, with M3 and M4 acting as the active current mirror load for this first stage. The high output resistances of these transistors provide a high gain for this stage, and its single ended output feeds the second gain stage. The last stage is the second gain stage and consists of transistors M6 and M7. The NMOS transistor M6 is the driver with M7 acting as the load. Again, the high output resistances of these two transistors equate to a relatively large gain for this stage and an overall moderate gain for the complete amplifier. The large gain of the last stage is further utilized in the compensation of the amplifier via the capacitance Cc. Without compensation, the op-amp will oscillate in feedback circuits with a high loop gain. By taking advantage of the Miller Effect and the high resistance at the drain of M2, a smaller value for the capacitance Cc is used than would be needed otherwise. However, due to the low transconductance of MOSFETS, the transistor M9 is needed to provide a nulling resistance to reduce the effects of that right hand plane zero in the transfer function, and, in fact, can be used to improve the frequency response of the amplifier. The three stages of the amplifier and its compensation circuitry provide a stable, moderate gain, low power and fast settling time monolithic CMOS operational amplifier. The following sections discuss the design of this amplifier, the constraints for the design, the simulation and performance results, and a discussion of the overall amplifier. DESIGN The design and design constraints were approached by first deciding on an appropriate topology. Due to its well-studied and simple nature, the standard CMOS operational topology was chosen. The folded cascode seemed to have also been a viable solution with many advantages, but was passed up due to design time constraints. Due to the fast settling time requirements, a PMOS input stage was chosen to increase the slew rate of the amplifier and, a NMOS driver in the second gain stage would provide the needed drive strength at the output. Then, after deciding upon the topology, the circuit was analyzed and the design specifications were reduced to simpler design constraints. Each specification led to different design constraints, as shown below. DC Gain: W W k p 2k n ( ) 2 ( )6 vo g m 2 g m6 L L vi ( g ds 2 g ds 4 ) ( g ds 6 g ds 7 ) ( 2 4) ( 6 7) I D5 I D7 Given the design specification of 85dB and using the minimum L=0.8um to minimize capacitance, this reduces to the following: W W ( )2 ( )6 L L 15.44 X 1012 A 2 I D5 I D7 Common-Mode Input Range: I D5 I D5 CMR VGS 3 VDSAT1 VGS1 0.75V or, 32.4 10 6 W W kn ( )3 ( )3 L L 2I D5 I D5 CMR VDSAT 5 VGS 2 Vto 0.75 , or W W k p ( )5 k p ( )2 L L 2I D5 I D5 380 10 6 A1 / 2 W W ( )5 ( )2 L L Output Swing: 2I D7 I Vout V DSAT 7 0.3 or, D 7 2.6 10 6 A W W k p ( )7 ( )7 L L 2I D7 I Vout V DSAT 6 0.3 or, D 7 5.7 10 6 A W W k n ( )6 ( )6 L L Power Dissipation: (ID8 + ID5 + ID7)*(VDD-VSS) 250uW, or, (ID8 + ID5 + ID7) 50uA Unity Gain Frequency: W W I D5 k p ( )2 I D5 ( )2 g L 50MHz , or, L 41.4 109 A1 / 2 F 1 fu m 2 2CC 2CC CC Settling Time: C C SR C L I D5 I D7 1 ( 4 )(6 7 ) I D 5 I D 7 p1 u 2 g m 6 Ro1 Ro 2 CC avo W 2CC 2k n ( ) 6 L W 2I D7 k n ( ) 6 g L p2 m6 CC CC n p1 p2 avo p1 p2 2 p1 p2 avo VOVERSHOOT Vo exp 1 2 1 0.001 Vo TS ln n 1 2 n VOVERSHOOT Power Supply Rejection Ratio: g GB m 2 CC W W k p kn ( )2 ( )6 g m 2 g m6 L L Avo ( g ds 2 g ds 4 ) g ds 6 (2 4 )6 I D5 I D7 GB ( 4 ) 6 I D 5 I D 7 p 2 Avo W 2CC k p ( ) 6 L W W k p kn ( )2 ( )6 g m2 g m6 L L Avo ( g ds 2 g ds 4 ) g ds 7 (2 4 )7 I D5 I D7 ( g ds 2 g ds 4 ) ( 2 4 ) I D 5 p CC 2C C Using the above equations, an initial design was estimated and entered into spice and simulated. To begin, a rough estimate of CC was determined as 0.2*CL. Then (W/L)2 and (W/L)5 were set to meet what appeared to be the major constraint on the design – the CMR. ID5 was then set to meet the unity gain frequency and the CMR, and, initially ID7 was set about equal to ID5 to keep the gain high. As mentioned before, the CMR was the major constraint for the design according to hand calculations, requiring a small ID5 and a large (W/L)2 and (W/L)5. In spice, however, the CMR was not a constrain at all and, in fact, the area of the transistors needed to be decreased significantly to improve the frequency response and settling time of the amplifier. Throughout the design process, the PSRR- and the settling time were the major constraints to the design. The slew rate of the amplifier initially limited its settling time. To improve this, ID7 was increased to improve the current available to charge the capacitance at the output node. The PSRR- was improved by increasing the magnitude of its pole as shown in the equations above. The whole design process was a set of tradeoffs, which finally converged to a working design. When all parameters were extremely close to meeting the specifications, the nulling resistor as implemented by M9 was tweaked to obtain the optimal frequency response and settling time. The transistor and bias summary for this final design is shown in the next section. The hand calculations for the final design are included in the table in the “Design Performance” section. Additional design information and the differences between the hand calculations and the spice simulations are further addressed in the “Discussion” section. TRANSISTOR AND BIAS SUMMARY Transistor W/L (um/um) ID (uA) VGS (mV) gm (uA/V) gds (nA/V) M1 66/0.8 4.107 738.861 211.485 482.505 M2 66/0.8 4.108 738.858 211.489 482.527 M3 14/0.8 4.107 761.959 132.705 643.662 M4 14/0.8 4.108 761.959 132.729 643.898 M5 18/0.8 8.215 809.476 150.287 890.241 M6 64/0.8 26.790 763.131 849.558 5779.200 M7 54/0.8 26.790 809.476 490.102 3155.900 M8 2.4/0.8 0.993 809.476 18.165 97.542 M9 40/0.8 0.000 717.635 0.000 111629.300 M10 8/0.8 0.993 740.383 49.208 155.086 M11 8/0.8 0.993 740.383 49.208 155.086 M12 1.2/2.4 0.993 890.014 10.479 3.686 M13 1.2/2.4 0.993 890.014 10.479 3.686 M14 1.2/2.4 0.993 890.014 10.479 3.686 Table 1 A summary of the transistors and biasing. DESIGN PERFORMANCE Parameter Design Objective Hand Calculated* Simulated Performance DC Gain 85 dB or more 92.03 dB 85.02 dB Common Mode Input Range Positive 1.75 V or more 1.69 V 1.79 V Negative -1.75 V or less -2.44 V -2.43 V Output Swing Positive 2.2 V or more 2.413 V 2.499 V Negative -2.2 V or less -2.439 V -2.490 V Power Dissipation 250uW or less 180 uW 180 uW Unity Gain Frequency 50 MHz 95 MHz 65.9 MHz Settling Time 0 to +1 V Output Step 250 ns to 0.1% 210 ns 158 ns 0 to -1 V Output Step 250 ns to 0.1% 210 ns 132 ns CMRR at DC 85 dB or more inifinite 95.2 dB PSRR PSRR+ at DC 85 dB or more 97.1 dB 94.0 dB PSRR+ at 800kHz 40 dB or more 86.4 dB 60.6 dB PSRR- at DC 85 dB or more 87.4 dB 94.5 dB PSRR- at 800kHz 40 dB or more 32.6 dB 40.0 dB Table 2 Comparison of the design objective and the calculated and simulated results. * Using the drain current values from the spice simulation and the equations in the “Design” section DISCUSSION Overall, the final design performed above and beyond the design specification. In particular, the unity gain frequency, settling time, and power particularly excelled. The low power biasing, the moderate to small device size and hence small device capacitances, and the moderate current available to charge the capacitances helped to meet and improve on the design specifications. Each specification is further examined below, but a few issues affected the whole circuit and are described here. In the design of the amplifier, the bulks were tied to the sources for simplicity in design and this is a valid simplification for several reasons. First of all, by looking at the circuit, it can be seen that most of the transistors naturally have their bulks and sources connected. Second, a current dual well process could implement this type of configuration. Finally, if the bulks were tied to their respective power supply, it would have little impact on the performance of the circuit. The only impact on the circuit would be to increase Vt1 and Vt2 by p[(2f+VSB)1/2 – (2f)1/2)=60 mV. The gain of the circuit would be unaffected, because, gm1 and gm2 are fixed by the value of ID5. The CMR+ would decrease by 60 mV and this change would have to be compensated by a slightly larger (W/L)1 and (W/L)2, but would otherwise affect the circuit very little. In addition, the bias circuitry would have to change slightly to produce the same current in its branch, but would otherwise not affect the performance of the amplifier. However, CMOS processes have at least one well and thus either the M1 and M2 would have to be adjusted slightly or the biasing circuitry would, but not both. Another issue that hampered the initial design stages was the fact that the calculated values differed somewhat from the simulated values, as can be seen in table 2. It appears that short channel effects caused the differences in gain and in the ouput swing and CMR values. With an Leff of 0.44 um for the PMOS transistors and 0.56 um for NMOS, short channel effects become significant, reducing the gain and VDSAT of the devices, especially for the smaller PMOS transistors. This helped to meet the output swing and CMR specifications, but hurt the gain slightly. The difference in the frequency response and hence unity gain frequency was due to assumption that the first pole was dominant and the frequency response was not affected by the others. In reality, a second pole that was below the unity gain frequency existed at about 35 MHz and thus affected the frequency response. Each specification is further examined and validated in the following subsections. DC GAIN Throughout the design, the dc gain was not a factor and was reduced in trading off other performance characteristics of the design. The gain was measure using the configuration shown in figure 2, below, because it allows the direct measurement of vo/vin at dc. VOS VDD Vin V+ + OUT Vo CL V- - 2p VSS Figure 2 Configuration for the measurement of the open loop gain. Figure 3 DC Gain and –3dB frequency of the amplifier. The graph in Figure 3, above, shows the result of the simulation. The DC gain is just slightly over 85 dB, 85.02 dB to be exact, and the gain starts to roll off around the –3dB frequency of 4.06 kHz. COMMON-MODE INPUT RANGE In hand calculations, the CMR appeared to be the most limiting constraint for the design, requiring a small value for ID5 and large values for (W/L)5 and (W/L)2. In simulations, however, the CMR posed no limit on the design and stayed relatively independent to design changes. The CMR was measured using the circuit in figure 4 by sweeping the input voltage from VSS to VDD. This configuration was chosen because, in a high gain configuration, the output swing of the amplifier limits the linearity of the circuit. In the unity gain configuration, however, the linear portion of the curve represents the CMR of the amplifier. The results from this simulation are shown in figures 5, 6 and 7 and show a CMR+ of 1.79 V and a CMR- or –2.42 V. The difference between hand calculations and simulation was due to the short channel nature of the devices, which caused the VDSAT of the devices to be less than the (VGS-Vth) that long channel theory predicts. This effect was more pronounced in the PMOS devices, which had a smaller Leff. In addition, this effect was also seen when simulating the output swing of the device, which is discussed in the next section. VDD V+ Vin + OUT Vout V- - CL 2p VSS Figure 4 The configuration for the measurement of the CMR. Figure 5 The common mode input range of the amplifier. Figure 6 A close-up of the CMR+. Figure 7 A close-up of the CMR-. OUTPUT SWING The output swing of the device was not a major constraint on the design, but was even less so in simulations than in hand calculations. The reason for this short channel effects, as described above in the CMR section. The circuit in figure 8 was used to measure the output swing of the amplifier. In the unity gain configuration, the linearity of the transfer curve is limited by the CMR. Using this configuration of higher gain, the linearity region of a plot of vo vs. vin corresponds to the output swing of the amplifier. The results of the simulation are displayed in figures 9 through 11 and plot vo vs. vin. VDD V+ + OUT Vout RF2 V- Vin - CL 1M 2p VSS RF1 10M Figure 8 The configuration for the measurement of the output swing. Figure 6 The output voltage swing of the amplifier. Figure 10 A close-up of the positive output swing. Figure 11 A close-up of the negative output swing. POWER DISSIPATION The circuit was initially designed for a maximum open loop quiescent power or 250 uW. To save power, the current source biasing and biasing for the nulling resistor were combined in a single low current branch. This allowed a lot of flexibility in choosing and modifying the current in the two gain stages. In the final design, this biasing stage consumed only about 4.5 uW of quiescent power. Overall, the total open loop quiescent power was 180 uW, as given by the output of the spice simulation. Furthermore, figures 13 and 15 below show that, with a capacitive load, the maximum dc power that this amplifier will consume under any conditions is 248 uW. This occurs when the amplifier is connected in unity gain feedback and its output is at –2.5 V. As Vo varies, VDS7 varies and causes a corresponding change in ID7 due to the channel modulation effect. This causes the power to vary with output voltage. The additional increase in power and current in the unity gain configuration is due to the fact that the output voltage is connected to the input, and thus modulates VDS5 as well as VDS7. It should be noted that the distortion in the power curve for the unity gain feedback configuration is due the current source transistor, M5, exiting its saturation region. VOS VDD Vin V+ + OUT Vo CL V- - 2p VSS Figure 12 Circuit for the Figure 13 The open loop power, in watts, as a function of vo. measurement of the open loop power. VDD V+ Vin + OUT Vout V- - CL 2p VSS Figure 14 Circuit for the measurement Figure 15 The unity gain power, in watts, as a function of vo. of the unity gain feedback power. UNITY GAIN FREQUENCY The unity gain frequency was not much of a limitation on the design until the final stages, at which point it was necessary to make small modifications to Cc to trade off frequency response for settling time. This is discussed more in the section on settling time. When the design was almost complete, (W/L)9 was modified to modulate the nulling resistance and determine the optimal pole-zero configuration. This resulted in the open-loop frequency response shown in figure 16 and a unity gain frequency of 65.9 MHz. For reference, the frequency response of the amplifier in the unity gain configuration is shown in figure 17. This plot exhibits a slight peaking near the unity gain frequency due to the 39 phase margin that was achieved, but is consistent with the open-loop results. Figure 16 The open-loop gain of the amplifier, highlighting the unity-gain frequency. Figure 17 Frequency response of the amplifier in the unity gain configuration, displaying a peak near the unity gain frequency due to the 39 phase margin SETTLING TIME The settling time was the most demanding constraint in the design of the amplifier. The initial design contained large (W/L) ratios and a small current in the differential pair in order to meet the CMR specification. This, however, led to a extremely poor settling time hampered by both a small charging current and large device capacitances. After discovering the CMR was not much of a limiting constraint, the device sizes were scaled aggressively to improve the settling time of the amplifier, at the expense of the gain. At this point, the capacitance at the output node was the limiting factor for the settling time and therefore the current in the second gain stage was increased to improve the charging current for that capacitance. The ringing that was observed was improved through the increase in Cc and through the modulation of the (W/L)9. These were used to obtain the optimal pole-zero configuration and resulted in a phase margin of 39 as shown in figure 18 below. This phase margin reduced the overshoot and improved the settling time significantly. The configuration in figure 19 was used to measure the settling time of the final design and was used for accuracy in setting the output voltage step range. The results of this simulation are shown in figures 20 through 22. The settling time to 0.1% for the amplifier was 158 ns for a 0 to +1 V output step and 132 ns for a 0 to –1 V output step. Figure 18 The phase response of the open-loop amplifier, displaying a phase margin of 39. VDD V+ Vin + OUT Vout V- - CL 2p VSS Figure 19 The amplifier configuration for the measurement of the settling time Figure 20 The settling time of the amplifier for a 0 to +1 and –1 output step. Figure 21 A close-up of the settling time for the Figure 22 A close-up of the settling time for the 0 to +1 V step. 0 to –1 V step CMRR The CMRR specification was not much of a constraint during the design of the amplifier, and basically required a commode-gain of less than 1 V/V. The deviation from the ideal CMRR of infinity is due to the finite output resistance of the current-mirror load transistor M3. This causes the small signal current that is mirrored in M4 to vary slightly and thus, id3 and id4 to not cancel exactly. The CMRR of the circuit was measure using the circuit in figure 23. The output of this circuit is approximately equal to 1/CMRR. The graph in figure 24 plots –20log(1/CMRR) to give the CMRR of the amplifier, in dB. The CMRR at DC is highlighted and is equal to 95.2 dB. Vcm VDD V+ + Vcm OUT Vout V- - CL 2p VSS Figure 23 The circuit for the Figure 24 CMRR as a function of frequency for the amplifier. measurement of the CMRR. PSRR The PSRR turned out to be an important constraint near the end of the design process. After meeting all of the other constraints, the PSRR was measured and found to not meet the specification. In order to fix this, and not adversely affect the other specifications, the p- of the PSRR was increased by increasing ID5 and decreasing (W/L)6. This improved the p-, but had very little effect on the gain. These relationships can be seen in the equations in the “Design” section of this document. It was also interesting to note that as the offset voltage of the amplifier was reduced by changing (W/L)3 and (W/L)4, the DC value of the PSRR increased. The reason for this is unclear, but it appears that when the circuit is unbalanced, a small DC voltage exists across either the M1 and M2 or M3 and M4. This small DC voltage would tend to decrease the output resistance of that device as the device neared the linear region, and this decrease in output resistance leads to a decrease in the PSRR. Also, to reduce the PSRR over all, the Rref was kept as large as possible to minimize the change in bias currents due to a change in the supply voltage. The PSRR was measured using the circuit of figure 25, with vss active for PSRR- and vdd active for PSRR+. As was shown in class, the unity gain configuration produces an output that is approximately equal to 1/PSRR. Figure 25 and 26 plot the PSRR+ and PSRR-, respectively. v dd VDD V+ + OUT Vout V- - CL 2p VSS v ss Figure 25 A circuit for the measurement of the PSRR. Figure 7 A plot of the PSRR+ of the amplifier as a function of frequency. Figure 8 A plot of the PSRR- of the amplifier as a function of frequency. CONCLUSION The design process that was followed resulted in a complete CMOS operational amplifier that at least met and, in a few cases, exceeded the design objectives by a large margin. The notable performance areas were the settling time of 158 ns, the unity gain frequency of 67 MHz, and the power consumption of 180 uW. A great deal was learned in the design process, including how to approach a design project, the tradeoffs involved in a CMOS op-amp design, patience, and how to stay up late. I felt that not much knowledge was gained from doing the report, but that it was still a necessary part of the project. I felt that the specification could have been a little more explicit in some areas, such as the process type being used (N-well, dual well, etc.), and maybe the maximum area or a maximum resistance value given from the start. Some redesign was necessary to decrease Rref below 40 k. Overall, it was a worthwhile and valuable experience.
Pages to are hidden for
"CMOS OPERATIONAL AMPLIFIER DESIGN PROJECT"Please download to view full document