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					SPI
(serial peripheral interface, Motorola specific), Valvano Chapter 7.7
synchronous interface, upto 1 Mbit/second
8 bit transfer at once
Can use more than one device with
         − Daisy chain or
         − Chip select


 Micro controller 6811                                  Peripheral
                                            enable

               MSB LSB             SS*                  CS              MSB LSB
              8 Bit SPDR        MISO                    MISO            8 Bit SPDR

                                MOSI                    MOSI

                                  SCK                   SCK

                                 GND                    GND




                         76543210               76543210
Control
       − Baud
       − Mode
         o Primary or Secondary Controller
         o Clock Polarity
         o Clock Phase
       − Arm Interrupt (transmission complete)
       − Ability to make output open drain (multiple devices) or standard logic


Status
       − SPIF transmission complete
       − WCOL write collision
       − MODF mode fault

If device is secondary controler: SCK is input, Primary Controller Out Secondary Controller In
(MOSI) is input, MISO is output


SPCR1
Bit 7: SPIE, enable SPI interrupt
Bit 6: SPE, eable SPI
Bit 5: DWOM, CMOS or open drain
Bit 4: SPTIE, enables Transmit interrupt (if HC12 is the slave)
Bit 3: CPOL polarity
Bit 2: CPHA phase
Bit 1: SSOE, slave select output enable
Bit 0: LSBFE, send LSBit first


SPCR2
New in HC12

SPIBR
Selects Baud rate
CPOL, CPHA
Illustration of polarity and phase.


                                                                             Trans.
                                                                             Complete

                                                                             Clock




                                                                             Data
                                                                             Available




usually
CPOL = 0, CPHA = 1 or
CPOL = 1, CPHA = 1


SPISR
Status register
Bit 7: SPIF, transfer complete
Bit 6: 0
Bit 5: SPTEF, transmit empty interrupt flag
Bit 4: MODF, mode fault, error with Primary/Secondary controller selection
Bit 3: 0
Bit 2: 0
Bit 1: 0
Bit 0: 0


SPDR
Data register, 8 bit
Example: 4 channel, 12 bit AD Converter
12 bit -> needs 2 transfers
4 channel -> needs channel select
MSB first
AD converter is peripheral, samples/sends data at rising edge of clock therefore SPI needs to
send data at falling edge of clock.
CPOL=0, CPHA=0 or
CPOL=1, CPHA=1
Input 0..2.5V
2MHz max -> 83 ksamples/second max
4 Channel 12 bit AD Converter Software

void ADinitilize(void)
{
DDRD |= 0x38 /* 0011 1000 makes CS, CLK, MOSI output, MISO input */
PORTD |= 0x20 /* 0010 0000 pulls CS high, no activity requested */
SPCR = 0x50 /* 0101 0000, SPIE=0, SPE=1, DWOM=0, MSTR=1, CPOL=0, CPHA=0,
CPR1=0, CPR0=0 is 1 MHz speed */
}

unsigned int ADread(unsigned char channel) /*returns 16 bit integer, requests 8 bit channel)
{
unsigned int data;
PORTD &= ~0x20; /* CS=0, indicates master, logical and with inverted 0x20 */
SPDR = channel; /* request channel */
while((SPSR&SPIF)==0) /*wait until SPIF is set*/
Data=SPDR; /* clear SPIF flag */

SPDR=0; /* start ADC */
while((SPSR&SPIF)==0) /*wait until SPIF is set*/
Data=SPDR<<8; /* read MS byte */

SPDR=0; /* second transfer*/
while((SPSR&SPIF)==0) /*wait until SPIF is set*/
Data+=SPDR; /* read LS byte */

PORTD |= 0x20; /* CS=1 end transfer */

Return data>>3; /* right justify */
}

				
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