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     To store a single bit, we can use flip flops or latches
     Larger memories can be built by using a 2D array of these 1-bit devices. This will
       result in what is called Static RAMs (SRAMs)
     Dynamic RAMs (DRAMs) use a tiny capacitor to store a bit.
     DRAMs require a write-after-read to restore the contents of memory while
       SRAMs do not.
     DRAMs require less power to operate and occupy less space.

The following will focus on building SRAMs from starting with a simple DFlip-Flop.
The design process is inherently simple and will involve first building a 1 bit cell, then
registers from the 1 bit cell, then memory blocks from registers and SRAMs from
memory blocks.

Figure 1 shows how to build a 1 bit cell from a D-Flip-Flop. The operation is simple;
when load is ‘1’ whatever is on ‘D’ will be stored at ‘Q’. When load is ‘0’ the stored
value does not change regardless of what the input is.

In                       Out
            D        Q
                                                             1 BIT

             clock                                          clk

     1 bit memory cell built                           Block diagram for a
        from a D-flip-flop                              1 bit memory cell

                                          Figure 1


The construction of an eight bit register to store 8 bits is shown in figure 2 and involves
connecting eight 1 bit cells together as shown. When load is ‘1’ all the cells will be
activated and the eight input values will be stored at their ‘q’ output. When load is ‘0’ the
stored value does not change regardless of what the input is.
                                          Figure 2

                                          Figure 3

Figure 3 shows the block diagram for the eight bit register that was constructed in figure
4. This block diagram can easily used to build a 16 bit register as shown in figure 4. The
principle of operation is the same here except that one register is used to store bits 0 to 7
and the other is used to store bits 8 to 15. Again both registers will store whatever is on
their inputs when load is ‘1’ and ignore the input when load is ‘0’.
Figure 4

Figure 5

This section covers the gradual construction of a SRAM from registers and other logic

Figure 6 is an embedded flash animation that shown how the 4 by 16 RAM works. It
incorporates four 16 bit registers (see figure 5) and has 2 bits (A0 and A1) for addressing
each register or memory location in the RAM. It also has a special write pin (WR) that
controls write access to each register. Click the blue buttons to view the simulations.

                                         Figure 6
                                         Figure 7

Before we can continue any further it is necessary to introduce a new device called a tri-
state buffer. This device is shown below. When S = ‘1’, A=B. When S = ‘0’ A is not =
to B, in fact A is disconnected from B.

Using the block diagram for the 4 by 16 RAM (figure 7) designed earlier and our tri-state
buffer, we are now in a position to design a Complete SRAM with the same specification
as those available on the market. This final design has a read (RD), write (WR), a chip
select (CS) and a bidirectional input-output data bus.

When RD and CS is ‘1’ data is allowed to be read from the RAM, also when WR and CS
is ‘1’ data is allowed to be written to the RAM. This is possible because of the action of
the tri-state buffer. Note also that when CS is ‘0’ the RAM chip will be disconnected
from the input-output bus. The importance of disconnecting from the input-output bus
will be seen in the next chip design.

                                       Figure 8
                                       Figure 9

Expand Memory by connecting RAMs together

Using the block diagram for our SRAM (Figure 9) we are able to double our memory by
combining two blocks of RAM as shown in figure 10. The resulting chip is an 8 by 16
SRAM. This means that there are eight address locations resulting from the two RAMs.
To address 8 locations we need 3 bits. The third bit is connected to decode that will
connect and disconnect each RAM from the data bus as necessary. The idea is to turn off
the RAM on the right and turn on the RAM on the left for address locations A2 =0, A1=
0, A1 = 0 to 011. When addressing higher memory locations 100 to 111 the RAM on the
left is disconnected and the RAM on the right is connected.
Figure 10

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