Afety Management in the Telecom Industry by gzg20129


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                                Multi Annual Strategic Plan 1and
                                            Research Agenda

                                      Proposed by the AENEAS association

V3. Changes compared to V2 are in dark-red. Added are a PowerPoint draft on “Grand Challenges of Si
process & process integration” and the first textual outputs of the working groups on “Wireless
Communication”, “Design Methods & Tools”, “Energy Efficiency”, “Automotive & Transport” and “Silicon
Processes & Integration”.
The changes in this version are marked in dark-red.
In the matrix in the embedded excel file, a cross is added at CO2 reduction / Industry. Rows 9 and 10 of
the matrix have been combined. Previous Row 12 has been included in row 30 (now row 28).
The document on Wireless Communication is replaced by a concise grand-challenge-oriented version.
Requirements of the Wirelees Communcation WG to Si-processes have been added to the latter chapter
by means of en embedded file, anticipating inclusion in a final textual version.

August 4th, 2009.

    The MASP is sub-ordinate to the second edition ENIAC Strategic Research Agenda as launched in November 2007

                                Context of the presented strategy.

The start of the new millennium brought new élan to Europe but also many new issues.
The European citizens demand to address the global warming, the aging society and their security. At the
same time they want to ensure prosperity for the young generation by building a firm economic basis.
In our competitive world business as usual will not address these demands. A top down strategy based
upon innovation is required. The Nano-Electronics industry is a cornerstone industry for innovation2. It is
at the root of solutions for health, medical, environmental and many other developments that will make
the difference in the coming years between “Europe as a leader” and “Europe as a follower of other
A consistent strategy in these fields will allow Europe to set the agenda on Global Warming and on
Security. It will turn Europe’s aging population into an asset, bringing Europe at the forefront of health
and ambient assisted living solutions. In return it will strengthen the European nano-electronics eco-
system consisting of world class scientists, thousands of SME’s and many globally operating
semiconductor companies. Investing in R&D for nano-electronics is an investment in an industry that is
at the roots of more than 10% of the European GDP and that generates more than 90% of the patents in
these fields.
Not everything in nano-electronics is needed to address the above mentioned demands. A top down
strategy is required to derive from the demands of the European citizens a set of connected challenges
to the nano-electronics industry. This document provides such a strategy.
On the other hand, Europe must also design strategies to make it attractive for the nano-electronics
industry to stay on the continent. Such strategies address conditions like taxation, employment and
education. When comparing Europe to Asia or to the USA it needs to ensure minimally an equal level
playing field. Preferably however it results in measures that make Europe the continent of choice for
nano-electronics activities. These strategies are not addressed by this document. The ESIA
competitiveness report of 2008 and the ENIAC SRA of 2007 provide an overview of these strategies.
       The current economical and financial crisis provides a good opportunity for counter-cyclical public
    funding. Not only will this soften the consequences of the crisis, but it will also ensure a strong position
       of the continent for the days when the crisis is over. Times of crisis are times that reward especially
       those who made bold investments in the future. Those investments should be made specifically in
     industrial research to stimulate European developments in lead markets and to prepare the European
                                   industry to emerge stronger out of the crisis.

    For the bigger picture about the position of the European Nano-Electronics industry in the global market see:

      bigger picture

                       Mapping the Future: The SEMIP strategy

The European demands for innovative solutions can be summarized by a 5 letter acronym: SEMIP. It
identifies the 5 most important areas, where the innovative power of the nano-electronics scientists and
industry can help: Safety, Environment, Mobility, Industry and People. Each of these 5 themes call upon
nano-electronics’ based innovations in present and future lead markets that will enable the systems
industry, the nano-electronics industry and the public authorities together to come with solutions to
enhance Europe’s competitiveness. SEMIP provides a top-down strategy to achieve these goals.
A feeling of unsafeness or insecurity works paralysing on a society. Ensuring safety and security is a
classic task of public authorities. The increased complexity of the European society calls for innovations
in protection of both goods and privacy and at the same time for surveillance, defence systems,
trustworthy identification, secure and safe transport of people, data, money and goods. These
innovations should simultaneously address the exploding costs (and waiting times) associated to safety
and security.
Climate change and the accompanying challenges to the energy supply have implications for the way we
live and do business. It demonstrates dramatically the need for innovations in the areas of renewable
energy, energy efficiency, smart grid, tele-presence and improvements for the air and the buildings we
live and work in. As such NanoElectronics contributes significantly to the “energy efficient buildings”
initiatives. Europe’s political willingness to address the environment will create the basis for a global
environmental industry that is based upon technologies from the nano-electronics.
An efficient, omnipresent, “green” and economic network for communication and transport is an
important infrastructural enabler. Wireless will be the buzz-word for future communication and GSM is a
first success of global dimension, born in Europe. The car industry, whose innovation is by and large
based upon nano-electronics, is pivotal for our transportation needs. Nano Electronics elements, like
sensors and power electronics, are important enablers of Green Car projects. Road Pricing and Virtual
Offices are other key innovative solutions that address our needs for mobility.
Economic growth and future prosperity are rightful demands from our younger generation. They require
a healthy industrial base. To safeguard the innovative power of Europe in the future, this holds even
more for the nano-electronics industry. Our world-class position in Production Equipment and Materials
is envied by many outside Europe. Our capability to produce profitable new semiconductor-based
solutions enables future innovations that would otherwise not be possible inside Europe. The “factories
of the future” initiative will build upon contributions from NanoElectronics.
An ageing society, due to a declining birth rate, causes increased competition for a qualified workforce.
On the other hand, it also represents an opportunity for technological R&D in medical electronics,

intelligent drugs, biotronics, measurements & diagnostics and Ambient Assisted Living (AAL). People live
in social networks. We are currently just at the beginning of a major role for nano-electronics in
expanding and maintaining our social networks.

    The semiconductor industry is going through fundamental changes:
   A slow down in the semiconductor market which is moving from a double digit average growth
    during the last years to a single structural digit growth. Independently of the economic crisis, this
    trend is reflecting that the microelectronics industry is maturing.
   The convergence between wireless, consumer and computer is requesting to develop silicon systems
   Strong development of new domains of applications in Automotive and Energy are driving the
    development of “More than Moore technologies” (power, analog/RF, sensors, Mems).
   Evolution of the customer base which are moving-up in the value chain to let industry pool
    investments in common subsystems and components.
   The requested scale of R&D and manufacturing means that cooperation is becoming vital.

                                      European strengths
   World class industrial laboratories and institutes
   World leader in material, equipment, IP, foundry and IDM
   World class clusters ( but challenged by scale)
   World OEM leaders in Telecom, Automotive, Industrial and Energy

                Vision of the European Nano-Electronics Industry

•   Executing the MASP allows ENIAC to be an impactful contributor towards Europe’s global leadership in
    Nano-Electronics by leveraging innovations to enable sustainable solutions to the contemporary
    societal challenges
•   European Nano-Electronics Industry intends to improve its position by focusing on the most urgent
    challenges in our society and by building on existing strengths and competencies in semiconductor
    technology, manufacturing skills and advanced equipment development. European companies have
    the potential to occupy top positions in technologies by responding to the major concerns of today’s
    society, ranking high on the public agenda: SEMIP.

•   Nano-Electronics is an essential provider of technology solutions countering these concerns
•   European independence in providing solutions for societal needs and addressing associated lead
    markets can only be achieved if backed by world-class knowhow in Nano-Electronics
•   R&D continuity and enhancements in high tech industry are a prerequisite for fast recovery from the
    current economic crisis
•   The existence of advanced semiconductor production sites in Europe is strongly depending on
    effective public-private-partnerships
•   Sentence about supply chain
•   A broad set of measures is required to create an appropriate business and investment climate both
    for R&D and for sustaining European based manufacturing capabilities
•   The ENIAC MASP provides the R&D framework for the above.
•   The ENIAC MASP paves the way for economic growth in the industry sector in Europe by doubling
    R&D investment in public/private partnerships in line with the ENIAC SRA
•   The ENIAC MASP ensures value creation and benefits throughout the supply chain on the basis of
    European IP ownership.
•   This MASP update enhances the visibility of key enabling technologies
•   Applications are the immediate link between technology and lead markets, and essential for overall
    industry continuity
•   AENEAS has identified a set of 3 enabling technologies and 3 lead applications
•   SEMIP and “Grand Challenges” are leading in each of these 6 domains

      Linking SEMIP to the intricacies of the Nano-Electronics Industry.

The nano-electronics industry is not organized in terms of “aging society” or “environmental needs”. It is
organized in terms of value-chain: universities, suppliers, production, customers. It is also organized in
terms of product lifecycle: research, development, manufacturing, sales. Both the value-chain and the
chain of the product life cycle cannot and are not constraint by national borders. They are international
by nature and require collaborative efforts that involve multiple European countries. The industry is
highly competitive and has for that reason not a common strategy. Competition is healthy. It keeps the
total eco-system in an efficient conditions. In the value chain competition exists between suppliers. In
the product life-cycle there is a precompetitive part in the very beginning. But the final phases of the
Development, and the Sales and Marketing are certainly competitive, making an overall common
strategy difficult, if not impossible to achieve. Nevertheless SEMIP poses a number of precompetitive
challenges to the industry that have been acknowledged and that require cooperative action between
the various contributors in the value chain. This chapter translates the SEMIP needs into so-called
“Grand Challenges” for the nano-electronics industry. Although each “Grand Challenge” is pre-
competitive, the link with industry is so strong, that in general terms the business reasons to embark on
them, like expected market size, needed investments, etc. can and will be given in this document3.
The nano-electronics industry describes its pre-competitive activities in terms of technologies and
applications. The most important technologies are: “Equipment, Materials and Manufacturing”, “Design
Methods and Tools” and “Silicon Processes and Integration”. The most important applications are
“Automotive and Transport”, “Energy Efficiency” and “Wireless Communication”. In each technology and
application domain “Grand Challenges” need to be solved in order to enable innovative solutions as
demanded by SEMIP. The table below gives the relation between SEMIP and the “Grand Challenges”.
Each cross in this matrix will be elucidated as part of the following chapters.

    MASP structure

ENIAC calls upon all R&D actors in Europe to come with solutions for the mentioned “Grand Challenges”
and stimulates a linkage to the systems industry and to Public Authorities in order to map together
Europe’s future, as formulated by SEMIP. Funding should be based upon fit of the proposals with the
“Grand Challenges” as given.

 Also specific terms exist, but those cannot be communicated within the scope of this MASP, because of existing
anti-trust legislation.

                                       Making it happen

This MASP emphasizes large projects combining enabling technologies topics with topics from lead
applications. The total ecosystem value will be leveraged by addressing all players along the product and
knowledge supply chain (SME, corporations, institutes, education, PA’s).
Process alignment with Eureka cluster CATRENE will be done in close cooperation with PA’s.

                    Equipment, Materials and Manufacturing


For semiconductor manufacturing, Europe has a long history of successful mechanical
engineering, tailor made machinery, optical equipment, and chemical processing tools. In
addition, operating supplies, raw materials, auxiliary materials and substrate materials were
offered and developed in leading qualities. Currently, we observe a certain focus towards
tangible end products. It is, however, of utmost importance to realize and to make aware of the
imperative to maintain and to improve these capabilities and skills, comprising the whole supply
chain of materials, equipment, and manufacturing. They are the fundament of future markets, of
future technologies and of future wealth. Above skills are THE innovation drivers for other
European core industries in automotive, automation, energy, communication and medical
solutions and products.

Mainstream CMOS technology is today somewhat a commodity, and the supply chain markets
are solidified. However, advances in the technology nodes and in the cost-of-ownership require
modifications and improvements of equipment and materials. In addition, More-than-Moore
technologies reveal new challenges and chances in equipment, metrology equipment, materials,
and manufacturing solutions. Thus, substantial improvements are offered for 300mm and
200mm fabs by R&D within the grand challenges, including forefront R&D for 450mm
equipment, materials and manufacturing solutions.

Grand Challenge 1 – Substrate/SOI
Vision: Maintain Europe’s leading position w.r.t. substrates including SOI for 200mm and
300mm technology and prepare for 450mm technology

The world market for Silicon substrates is 12 b€ in 2009 with a European share of about 15%. In
comparison the market for SOI is significantly smaller with a volume of 0.5 b€ in 2009. Currently,
a few European suppliers (e.g. MEMC, Siltronic and Soitec) are able to sustain competitive in
the world market.

It is the ambition to increase the European market share for next generation 300mm and 200mm
and to sustain or gain leading European position also during the technology transition to 450mm.

The following issues can be identified as topics for ENIAC

   o   Tailored material solutions: Designed substrates are of high interest as the specifically
       customized substrates with designed and functional layers and areas are able to
       guarantee the European leadership within this market segment. This demand for joint
       efforts for development of innovative designs and substrates.
   o   Quality Control Strategies: The efforts for inspection of substrates to guarantee
       specifications are a dominant portion of the cost of a substrate. Therefore, the
       development of enhanced and new quality control strategies but also the implementation
       of new standards for substrate specifications will be a focus of applied industrial research
       in the next years.
   o   High Purity Si: The pureness and the crystal quality are essential for the achieved
       performance of the substrates. Essential for the quality of the ingots, especially with
       respect to 450 mm diameter ingots, is the pureness of the silicon raw material, the
       temperature control, and the growth process.
   o   Substrate processing: The transition for 450 mm substrate diameter requires for new and
       innovative production, sawing, grinding, polishing, and cleaning processes to fulfill the
       expected specifications defined by the integrated device manufacturers.

Grand Challenge 2 – EUV
Vision: Realize EUV Lithography as the chip mass manufacturing technology of the next
decade and sustain Europe’s leading position in lithography
Extreme Ultra-Violet Lithography (EUVL) is anticipated to become the key enabler for More
Moore chip mass manufacturing beginning at 22nm feature sizes (half-pitch). Accordingly, EUVL
addresses a large future market of several b€ annual volume, and is of strategic importance
because of its enabling character, and its extendibility over several technology nodes down to
the 11nm node and below. EUVL requires the development of major technological solutions:
high power EUV sources, optics for high quality imaging at 13.5nm wavelength of EUV, mask
fabrication processes with low defect density, and sensitive resists with low linewidth roughness,
new metrology equipment e.g. for defect engineering and process control, and supporting
process equipment e.g. for mask cleaning and inspection. The investments are expected to
exceed 1b€. Accordingly, the development of EUV lithography will have a large impact on the
semiconductor equipment market. Europe’s leading role achieved in the currently used 193nm
immersion lithography can only be defended by a successful introduction of EUVL. The objective
of ENIAC is to focus existing European competencies which are not available in a single country
or company to realize EUVL, and thereby sustain highly qualified employment in Europe, and
guarantee European access to this key strategic technology.

Grand Challenge 3 - Metrology

Vision: Use of existing excellent European infrastructure to gain market share in US
dominated market.
The estimated world market of semiconductor metrology tools amounts to ca. 2500 M€ (2005).
New technology nodes require new tools of higher resolution and speed. The integration of new
designs will become increasingly important. Technologies are needed for:
     o process control
     o review
     o fab inline inspection
     o composition control
     o analytics (lab)

A transition to 450mm technology imposes significant challenges for metrology suppliers and will
provide benefits for 300mm and 200mm technologies.
Because Europe has world leading know how in e-beam and optical technologies, the ambition
is to use these strengths to increase European market share in metrology tools.

Grand Challenge 4 - Microstructuring
Vision: Leading position of Europe in micro structuring equipment to offer superior
solutions for customized low volume manufacturing and “More than Moore” applications
The estimated global market for etch tools is 500 M€ (2010) with a market share of 10 % for
European companies. Micro structuring markets are in an emerging state. With the aggressive
scaling of device feature sizes, etching has been one of the critical steps in IC-manufacturing.
Etch processing is extended for new materials, e.g. new metal electrodes and high-k dielectrics
which are introduced in all technology drivers, e.g. microprocessors, DRAMs, ASICs but also in
mixed signal and power devices. Heterogeneous integration of these devices has driven 3d
integration from the silicon level. High-rate through silicon via etching and processing of thinned
wafers are key steps for realization of this concept.
These developments give good opportunity to gain significant market shares for European
suppliers in a short timeframe by offering superior technical solutions in the etch and also the
related metrology equipment market, hence sustaining and developing highly qualified
employment in Europe. The objective of the ENIAC program is to provide European chip
manufacturers with superior solutions for low volume manufacturing and heterogeneous
integration (e.g. More than Moore) and to achieve a leading European position in micro
structuring equipment.

Grand Challenge 5 - Deposition
Vision: Leading position of Europe in deposition equipment to offer superior solutions for customized
low volume manufacturing and “More than Moore” applications

The world wide deposition equipment market including thermal processing equipments, vapor
deposition technologies and sputter equipment are predicted for 2010 to reach 6 bn. Euro with a
European share of about 13%.

Some European deposition equipment suppliers are world wide recognized experts in modern
deposition techniques like ALD, AVD and optimized PVD and CVD processes. These
technologies are essential for the manufacturing of ultra thin films for ultra-low power products
and for the development of modern semiconductor applications (e.g. phase change memory).
The introduction of new materials for sensor technologies and heterogeneous integration are in
an emerging state with a great potential in the new future. This gives good opportunity to gain
significant market shares in a comparably short timeframe by offering superior technical
solutions with European partners.

The deposition technology is often substrate size independent and a possible transition to
450mm technology imposes significant challenges and opportunities for deposition equipment
suppliers with excellent benefits also for 300mm and 200mm applications.

Grand Challenge 6 – Manufacturing and 450 mm
Vision: Strengthen the position of European semiconductor manufacturing and of
European equipment manufacturers.

The ambition is to provide a European chip manufacturing environment with superior solutions
for flexible and sustainable manufacturing and to achieve a leading European position in process
and metrology equipment also based on early participation in 450mm.

Semiconductor Manufacturing: Most European IC manufacturers are on the way towards a
production with high product diversity and an increasing number of small lots. Today, almost all
existing fab infrastructures, factory operation models and methodologies as well as factory
information and control systems were designed for small product diversity and lot sizes of 25 -
50 wafers. In the future, flexible generic fab models are needed which allow the production of
small lots at high productivity figures. In addition to that, changing fab utilization has to be
considered and innovative automation on tool and on fab level is required. Above those
technological challenges, sustainable and benign manufacturing becomes more important.

Semiconductor Equipment: The world wide equipment market predicted for 2010 is about 30000
M€. It is assumed that in the future between 20 – 30 % of the total sales will be covered by
450mm which equals to up to 10000 M€. About 10 % of this market is currently covered by
European equipment suppliers. Additionally, caused by the cross fertilization for the 300mm and

200mm, additional benefit is expected, especially in the area of standardized solutions for
hardware and software components (such as loader and handling components, generalized
hook-up of facilities, methods for cyle time reduction, or standardized APC methodologies).

Early participation in 450 mm equipment development will offer significant benefit and cross
fertilization for 300mm and 200mm and gain a leading position of Europe in both manufacturing
and equipment.

Grand Challenge 7 – Backend technologies
Vision: Amplify European strength in back end technologies.

The global market of back end technologies is XXX €. European share : XX %
System integration on wafer level will be an important part of future backend technologies. This
includes e.g. 3D integration, thin wafer technologies, wafer dicing, encapsulation technologies
such as wafer molding and optical interconnects. Concerning substrates this includes embedded
devices technologies, printable wiring also on organic substrates, thick copper power lines.
There is a huge portfolio of upcoming backend technologies where solutions and improvements
have to be found for. E.g. low temperature interconnects, package stacking, self alignment,
power electronic packaging, alternative encapsulation processes, shielding technologies and
thin package.

                                 Automotive and Transport

Introduction and Grand Challenges
The Grand Challenges of this Sub-Programme are both in the domain of the main economical and
technological driver, which the Automotive sector. We have identified two Grand Challenges, which are
to an extremely high degree dependent from new achievements in semiconductor technology, one of
them covering the environmental aspects, the “Full Electric Car”, the other one covering the security and
safety aspects, the “Safe Car”. As shortly described in the next chapter, both are of very high relevance
for Europe and address typical European competences, available in companies,institutes and
universities. The results of the planned R&D work will also impact Aeronautics and other transportation

Relevance for Europe

Market value
Environment and safety are clear societal needs for the future intelligent road-traffic. As the volume of
traffic on our roads continues to increase, there will be an increased demand for safety, emission
control, fuel saving and comfort. The automotive industry represents 3% of Europe’s gross domestic
product and 8% of EU government’s total revenues. Electronic components have reached 20% (of which
Microelectronics is 44 %) of the car value, and the figure will continue growing after the actual economic
crisis (the microelectronics share could even grow up to 55%) in the next years. In total, Automotive
components represented 19% of European electronic component market in 2006.
These numbers include the micro- and nanoelectronics components for the “Safe Car” challenge. The
future market share of the “Full Electric Car” is not easy to predict, but recently announced targets in
some European countries allow an expectation of a few million Electric Cars in Europe in the year 2020,
which corresponds to a market of around 50 Billion €. Increasing oil price on one side and introduction of
the smart e-grid will foster the market penetration of the Electric Car.
Car industry is quite widely spread in Europe. Besides traditional main players in Germany, France, Italy
and UK, strong car industry exists in Spain, Poland, Czech Republic and Rumania. Automotive industry is
even more widely spread among different countries. Nanoelectronics will also give an essential
contribution to the integration of all other modes of transport (air, rail and waterways) that are
projected to form the largest part of freight transport and to contribute significantly to passenger traffic
in year 2020.

Social Benefits
The European transport system is a vital element in ensuring Europe's economic and social prosperity. It
serves key roles in the transportation of people and goods in a local, regional, national, European and
international context. Beside the direct impact on the transport sector, the development of new
Nanoelectronics technologies for transport will bring indirect benefits to all European countries. In the
first place Nanoelectronics will contribute to the reduction of energy consumption and atmospheric
pollution, and help to meet Kyoto Protocol. In Europe, road transportation alone accounts for 21% of
fossil fuel consumption, and 60% of all oil (OECD). Sophisticated electronics for engine management have
already contributed to strongly reduce both the overall emissions and primary energy use, but much
progress is still possible. The move towards hybrid and fully electric cars is the next step and will require
a full set of new technologies for power management. Concerning the CO2 emission, the Full Electric Car
has the potential for reduction from todays > 120g/km to around 45g/km. An integrated approach that
links all modes of transport (air, rail, road and waterway), is essential for ensuring that sustainable and
competitive transport solutions make a visible and positive difference for Europe, its citizens and its
Road safety is another critical issue: there are 5 deadly accidents every hour, and road accidents are the
main cause of death in the under-45 age group. The introduction of safety features like ABS, Airbags, and
Electronic Stability Control, enabled by the quick evolution of Microelectronics have already significantly
contributed to reduce the number of casualties. Nanoelectronics-based enabling technologies will allow
a quick move toward the goal of zero road fatalities. In an aging society, the number of senior citizens is
continuously growing. Assistive systems, driver monitoring and alerting can be leveraged to mitigate
cognitive shortcomings due to age-caused disabilities. Such systems will increase security for all road
users, and at the same time extend the mobility and self-determined independence of the elderly.

Application Areas and Technology Challenges
The grand challenges as introduced above are – of course – not the only topics of this sub-chapter. On
the way to the full electric car, there are different steps starting from the optimisation of conventional
combustion machines and also focussing on the development of hybrid cars. These targets require the
introduction of Nanoelectronics in all aspects of automotive industry.
a) Improvement of the conventional combustion technology:
o   More sophisticated engine management units, coupled to sensors and actuators can further reduce
    fuel consumption in present internal combustion engines, allowing to a 30% reduction in average
    CO2 emissions for the new vehicle fleet in 2020.
o   Efficiency increase and reduction of pollution in Internal combustion engines will require advanced
    mechatronics for fuel and air control, coupled with low-cost sensors and highly efficient computing
    units, based on the most advanced CMOS technology.

b) Development of advanced hybrid technology and of the full electric car:
    o   The process of moving to hybrid and afterwards full electric cars is expected to require several
        steps, involving increasingly more sophisticated systems of energy storage (batteries, super-
        capacitors) and energy management. Europe-made hybrid vehicle could gain a significant part of
        new registration by 2012, while commercial fully electric cars will start to be available around
        the same date.
    o   Hybrids and full electric vehicles will require power electronics and sophisticated and reliable
        power management systems, able to withstand high voltages and power surges, in order to
        manage power distribution among engine(s), batteries, super capacitors, and the external power
        supplies. The same basic technologies could be adapted to power management in industrial
        applications, and to the exploitation of renewable sources, mainly photovoltaics.

c) The way towards the safe car:
o   Active safety will see an increased use of detectors (solid state optical and IR cameras, ultrasonic
    sensors, radars) coupled to high performance logic for real time obstacle detection and driving
    assistance. This has to be coupled with high speed, low cost data storage and processing for collision
o   Passive safety will rely on increased use of sensors distributed through all the car or plane, and
    connected by RF or power-line. Energy scavenging will be the medium-long term energy source.
o   Traffic congestion can be reduced by advancements in navigation systems, based of wireless
    communications and GPS, to exchange data with road infrastructures and among the cars
d) General requirements:
o   Distributed sensor networks, communicating through RF and supplied by energy scavenging, can
    strongly reduce car weight and costs, and could be applied to a variety of segments including
    aeronautics and large structures, like building and bridges. It will require, in addition to reliable
    technology for sensors and energy scavenging sources, high performance low power logic for sensor
    data acquisition and handling and low cost RF CMOS technology.
o   All electronic systems for automotive and aerospace applications have to withstand very harsh
    environments, including high temperatures, humidity, vibration, fluid contamination and electro-
    magnetic compatibility. The safety-critical nature of automotive systems will require extreme
    reliability and long life time, measured in parts per billion instead of today's parts per million.
o   Cost of high performance logic for assisted driving systems must be reduced for a widespread
    adoption, while reducing energy consumption and increasing frequency capability through
    development of advanced CMOS logic technology.

Conditions for success
Regarding the technological competences and market positions, Europe has very good chances for
keeping leadership in the domain of (Nanoelectronics for) Automotive and Transport. However, there is
still a huge need for specific R&D work, which will represent thousands of person-years and hundreds of
M€ per year. In addition to the described specific technological innovations, a few very general points
shall be mentioned:
    o   Successful introduction of really energy efficient (like full electrical car) and of safe
        transportation media needs world-wide standardisation and interfaces
    o   It also needs a very high degree of trust in robustness and reliability of the electronic devices –
        especially under harsh conditions (like close to the engines)
    o   The new developments must be affordable (only moderate cost allow market penetration)
    o   The introduction of energy efficient and safe transportation must be supported by the
        governments by regulations and by public procurement.

Note: Research/Prototyping/Deployment means for mass production. Some of these options are partially

                                              Speed control;, brake assistance, adaptive lighting, lane control

                                       Car radar and optical, night vision, car-to-car/car-to-road communication, obstacle recognition

                                     Advanced combustion engines, exhaust control, fuel adaptive engines

                                      Hybrid car engine management, energy storage control, power management

                                      Full electric car, battery power management, fast recharging, engine integration in wheels

                                    In-car sensors for weather, road conditions, chassis, tyres, lighting – wire-line

                                      Infrastructure sensors, infrastructure-to-car, car-to-car communications

                                       2010                      2015                       2020                        2025
                Research                                        Prototyping                         Deployment
available in high end cars, but their social benefits will be effective only if they can be extended to the
majority of cars.

Synergies with other SP
Possible synergy areas with other priorities are (not exhaustive):
   Basic power and power management technology will also find use in the Sub-Programme “Energy
    and Environment”.
   Safe design methodology, and Design for Reliability can profit from the results of the priority Sub-
    programme “Design Methods and Tools”
   System-in-Package technology will profit from the results of the priority “Assembling technology for
    system-in-package” in the Sub-Programme “Equipment and Materials”, even if it will require a
    dedicated effort for temperature control and heat management.

                                       Energy Efficiency

Introduction and Grand Challenges
The Grand Challenges of this Sub-programme serve both today´s certainly most important overarching
theme “Environment”. We have indentified two grand challenges, one of them is “CO2-reduction” – a
rather general target, which concerns the Automotive, the Industrial, the Lighting and the Mobile
Communication sectors. The other grand challenge is the “Smart energy grid”, targeting mainly topics
around energy distribution. Generally, the priorities of this sub-programme are reduction of power
consumption and very effective ways of power generation and distribution. Advanced Nanoelectronics
devices, especially sensor networks could give an important contribution to the monitoring of
environmental parameters and to the control of pollution, and much more.

Relevance for Europe

Market value
Coming from 3.1 million GWh in 2003, Europe will need in 2020, electrical energy of about 3.6 million
GWh according to a study by IEA (International Energy Association). By using intelligent, innovative
electronic components and systems, 0.7 million GWh can be saved, thereby helping the energy policy
and industry competitiveness in Europe significantly. A few examples for the energy saving potential in
different applications are:
       Lighting      - potential savings 22%
       Drive System - potential savings 18%

       Power Supply - potential savings 20%
The World market for power semiconductors is in the range of 10–15 B€/year, not including the control
market and also not including the replacement market for breakthrough technology for power-saving
equipment. Market penetration is more or less guaranteed due to legal requirements and the evident
demand by consumers for “Co2-reduced” products. In most of the addressed topics (industrial, lighting,
control and management of energy), Europe has a #1 position.

Societal Benefits
The impacts on the European society are multifarious and will affect all domains (private, industry and
public). The goal is to protect the natural resources and the environment in Europe in a sustainable
manner. The overall target is to prevent the waste of energy (and thereby the reduction of CO2-emission)
by using obsolete equipment and carelessness. An efficient use of energy is the political, social and
technical challenge of the next decade. Focusing on micro-/ nanoelectronics approaches in particular the
challenge to save electrical energy consumption in Europe in the range of more than 20% until 2020 is
feasible. This will reduce CO2 emission in the same order of magnitude in order to achieve the Kyoto
protocol targets and will limit the energy cost increase. The usage of efficient power supply and

intelligent energy control in new products could save up to 30% of the power consumption by
simultaneous increase of safety, functionality and convenience.
The European microelectronic research and development sector is requested to provide innovative
technologies as basis for new energy efficient products and intelligent power management. Through
consequent and combined efforts at European level there is the historical opportunity to extend the
technological leadership of the European industry in this field and to strengthening its competitiveness.
This will also have an enormous impact on high-qualification jobs in Europe.
Another important benefit for the European economics and welfare is the reduced dependence from
foreign and from fossil energy sources.

Application Areas and Technology Challenges
The societal benefits as described above can be realised if technological innovations are introduced in
those applications, where energy generation, transmission and consumption can be reduced without
losing functionality, performance and comfort. There is a long list of “candidates”, from which the most
relevant will be described shortly.
    a) Power generation
       o   In many cases, power generation – often from alternative sources – produces “raw” energy
           in a form, which cannot be transmitted or used without conversion. Examples are non-
           continuous energy sources like wind-mills and like solar cells. Using old-fashioned electronics
           for rectifying, transforming or converting (AC/DC or DC/AC) the currents, only about half of
           the energy could be used. New components will partially be based on SOI technology.
       o   Recuperation of energy (energy scavenging) will play an increasing role.
    b) Power transmission/distribution
       o   An up to now totally underestimated potential for energy saving is the management and
           distribution of (electrical) energy. The availability of European wide energy distribution
           networks is today only realised in case of problems producing large area “black-outs”. The
           challenge here is to bring intelligence into the power distribution system. The “smart energy
           grid” – being identified as one of the grand challenges – will combine management of
           incoming power, of distribution of power and of outgoing power.
       o   This could include also a network of (at this moment) un-used batteries of millions of
           electrical cars.
       o   The smart energy grid will only work, if it is not only a power-network, but at the same time
           a communication network, which contains security features, grid monitoring and payment
       o   For efficient energy transmission over long distances, very high voltage lines will be needed
           (e.g. 800 kV). Highly effective AC/DC/AC conversion will be needed for entry and exit of

c) Power consumption – which is to a very high degree linked to the grand challenge “CO2
   o   The most visible example is lighting. Most of the actual illumination systems have a rather
       limited conversion rate from electrical power to light power; large parts still are converted
       into heat. There is a huge potential for energy saving in the private domain, in industry and
       in the public domain.
   o   Another type of applications, which has still a very large potential for energy saving is the
       conversion of electrical power into movement, be it in industrial machines, in cars or in
       motors as used in private households, like in washing machines, motors for pumps etc.
   o   The third large energy consumer is the “in-situ” supply and conversion of electrical energy.
       Examples are power supplies as used for portable computers and mobile phones and stand-
       by switches for TV, recorders and computers.
   o   Also the electronic equipment itself still uses many components, which are only optimized
       with respect to performance and price, but not to energy saving.
   o   Medical applications are a still relative new and small field, but they depend very much form
       very good energy efficiency - guaranteeing a long lifetime and low weight for the portable
       units. Improved energy management is also key for cost-effective imaging systems in
d) Technological requirements:
   o   Innovative systems and architectures for power electronics in order to optimize the
       coefficient of efficiency. These technology challenges on system level refer directly to the
       first three described consumer-applications: controlled drives, lighting and intelligent power
       supplies and stand-by management.
   o   Heterogeneous system integration technologies for high power modules and System-in-
       package technologies taking into account highest currents, voltages, temperature as well as
       ESD, EMC and robustness aspects (from high power module to high power system in package
       - SiP). The challenge here is to make the power electronic devices useable for industrial
       applications and/or for applications under harsh conditions like in transportation (e.g. at the
       engine of a car or a high-speed train)
   o   Completely new or improved semiconductor technologies, using leading edge technology
       knowledge for low power consumption and extended lifetime (e.g. high-frequent and low-
       loss switching, digital power conversion)
   o   New semiconductor materials, such as SiC or GaN, and device architectures, thin substrates
       and interconnect materials to improve performance and reduce cost
   o   All new devices have to be robust and reliable – also under harsh conditions

Conditions for success
Regarding the technological competences and market positions, Europe has very good chances for
becoming leader in the domain of (Nanoelectronics for) Energy Efficiency. However, there is still a huge
need for specific R&D work, which will represent thousands of person-years and hundreds of M€ per
year. In addition to the described specific technological innovations, a few very general points shall be
    o   Effective energy management needs European wide (or even world-wide) standardisation and
    o   It also needs a very high degree of data security (e.g. for payment features)
    o   It must be affordable (only moderate cost allow market penetration
    o   The introduction of energy efficient goods must be supported by the governments by regulations
        and by public procurement.


                             intelligent drive control, intelligent switches and plugs, stand-by solutions

                             smart power management for industrial, consumer, medical appliances

                             daylight linked dimming systems, solid-state lighting devices, HID lamps

                             energy distribution and transformation systems

                             digital power conversion

                             efficient power supplies , AC/DC & DC/DC converter, switching power supplies, intelligent stand-by

                             regenerative energy (solar, wind, water) , energy recuperation

                              2010                        2015                         2020                   2025

              Research                                   Prototyping                           Deployment

Synergies with other SP
Possible synergy areas with other priorities are (not exhaustive):

   Basic power and power management technology will also find use in the Sub-programme:
    “Automotive and Transport”.

   New materials, which allow tailored power parameters for power switches will also be evaluated in
    the Sub-programme “Equipment, Materials and Manufacturing”.
   Low power devices, very often being used in safety or health relevant applications, will need specific
    design methodology and Design for Reliability” as developed in Sub-Programme “Design Methods
    and Tools”
   Failure analysis and reliability procedures related to high temperature, high current/voltage
    operation will also be an issue for Sub-programme: “Automotive and Transport”

                                                    Design Methods and Tools
Design is the key link between technology and the world of applications, but design capabilities and
design cost are also seen as limiting factors for the future technological development. ITRS roadmap is
evidencing the increasing gap between the technological transistor density at a give technology node
and the practical density achieved by design.

                                       Source: ITRS 2007

Improving design efficiency with proper methodologies and tools can therefore give the same gain in
device area, and therefore cost, as the move to next generation technology node, with a smaller
Moreover specific high tech sectors, which are among the strong point of Europe, like Automotive,
Telecom and Security, are increasingly requiring specific performances, like reliability, low power
consumption and immunity to tampering that can be achieved only through a tight integration between
design and technology.
The increasing impact of design on device development with new technology generations is clearly
shown by the decreasing number of new product start at each technology node.

         Number of new designs

                                         180               150        130         90   65

                                                    1st year     2nd year   3rd year

Innovations in Nanoelectronics are driven by the leading edge companies, accompanied by high
investments in new technologies. Due to the very high benefit for the fast/slow industrial
followers which use these technologies and thus for the whole society the support by public
funding is more than adequate.


The largest economical impact of design efficiency is on chip area and especially time-to-market. Price
drop for semiconductor devices is in the order of 27%/year. A delay of a few months in designing a new
product can have a significant impact in profit margins.
There is no clear data about the weight of design resources spent in Europe. Some information can be
deduced from the existing data on the market of EDA tools. Total sales (licenses plus assistance) for EDA
tools in Europe was around 1 B$ in 2007. Assuming an average investment of 20-25K$ per designer, it
gives a total of 40-50 thousand IC designers in Europe, distributed between semiconductor companies,
fabless design houses and IP providers, and system companies. With a ratio 1:3 between EDA tool
investment and other costs (salary plus design hardware), we can assume that total investment in design
by European companies has been around 3.5-4 B$, or 2.5- 2.8 B€ in 2007, which represents an
investment of more than 10% of the sales of European semiconductor industry.
The role of SME’s in the sector is important, both as pure design houses and IP providers, and as
developer of design tools for specific requirements of European industry. Even if the most successful
ones are afterward incorporated into the major leading companies, they can be considered to have
successfully achieved two objectives: transfer of university know-how into industrial applications, and
coverage of the specific needs of European industry.

Design gap
    As discussed above increasing device complexity, and the need to compensate for parasitic effects
    related to the nanometer scale are increasing the gap between technology potential and design
    capability. Improvement in design methods and tools is required to take full profit from the huge
    investment in technology development.
Diversification by design
    With the increasing trend towards standardization of basic CMOS technology, and the business
    model based on fab-less or fab-lite product companies supported by Silicon foundries, design
    becomes the main differentiating factor. Tools and methods must be developed to adapt standard
    technologies to specific applications, implementing reliability and manufacturability requirements by

Role of heterogeneous integration
   The inclusion of new functions, integrated on silicon on in package, on top of the basic logic
   and memory functions, like analogue, RF, power, sensing and optoelectronics, is adding a
   novel degree of complexity. Not only design tools are needed to model properly these
   functions, but also their integration with control and communication logic requires tools to
   support the proper system partitioning at high level

ITRS distinguish two basic types of complexity—silicon complexity and system complexity—that
follow from roadmaps for ITRS manufacturing technologies.
   System complexity refers to exponentially increasing transistor counts enabled by smaller
    feature sizes and to forms of diversity that arise with respect to system-level SOC or SiP
    integration. Heterogeneous integration is adding a new layer of physical complexity,
    introducing devices with novel physical properties. Design specification and validation
    become extremely challenging, particularly with respect to complex operating contexts.
   Silicon complexity refers to the impact of process scaling and the introduction of new
    materials or device/interconnect architectures. Many previously ignorable phenomena now
    have great impact on design correctness and value, such as non-ideal scaling of device
    parasitics, coupled high-frequency devices and interconnects manufacturing variability,
    process variability and decreased reliability.

European high tech industry has a strong position in the fields of Automotive and Aerospace, Mobile
Communications, Security and Industrial, while promising areas, strongly dependent however from
Public Procurement for the creation of markets, are in the field of Health, Ambient Assisted Living and
Energy Efficiency.

All these segments have strongly specific requirement that require the integration of logic with other
functions, like RF or optoelectronic links, power devices, sensors and analogue interfaces. Most of them
have also severe reliability and power efficiency requirements.
Therefore 4 “grand challenges” have been identified for research on Design Methods and Tools:
1. Design efficiency for functional complexity
   The main target is to organize tools and methodology in order to improve the efficiency of design of
   the complex devices needed for critical applications, often requiring the integration of
   heterogeneous logic components (microprocessor cores, DSP, memories, dedicated logic) and
   heterogeneous functions (RF, analogue, power) on chip or in package.
    Key topics are:
       i.   Tools for Architecture Exploration and Optimization of Heterogeneous Systems
      ii.   Behavioral models for high level design of heterogeneous functions.
     iii.   Design for New Heterogeneous and Homogeneous Architectures and 3-D integration
     iv.    Hardware-software partitioning and verification.

2. Reliability and yield by design
   Applications in the field of Automotive and Aerospace, Security and Health require very high levels of
   reliability, often for limited production volumes. At the same time, integration of different functions
   and increasing weight of parasitic effects is introducing new causes of malfunctioning, while the
   possibility to finely tune the process is decreasing with the use of foundries. Therefore reliability and
   yield must be inserted by design. Main topics are:
       i.   EMC and Signal integrity
      ii.   Modeling of reliability effects (aging, soft errors, electro-migration, ESD, EM coupling,
            temperature and hot spots)
     iii.   Redundancy and ECC for memories and regular structures.
     iv.    Layout processing for yield optimization.
      v.    Statistical design for yield optimization.
3. Energy efficient design
   The introduction of electronic controls, associated with distributed networks of sensors can
   significantly increase the efficiency of energy utilization. The most impressive example is perhaps the
   success of Automotive industry in reducing the fuel consumption by kilometre, even in the presence
   of increased car weight. However semiconductor devices themselves are a source of power
   consumption that can be dramatically felt in battery powered devices for communications and
   health, but is impacting also critical components of the information society, like the servers. Proper
   design can significantly contribute to power reduction through:
       i.  Energy modelling and estimation at different abstraction levels for heterogeneous
      ii.  Dynamic and static energy management for heterogeneous systems
     iii.  Thermal and variation-aware design under tight energy constraints
4. Diversification for application specific technology
   The strength of European industry is in a few application specific fields. Diversification of technology
   with the integration of different functions on chip or in package is a key factor for more competitive,
   less expensive, more power efficient and safer products. The added value is in the capability to
   integrate diversified functions with analogue interfaces and control logic in the most efficient way.
   Main topics are:
       i.   Tools for mixed analogue/digital/RF linked to system simulation, including SiP integration
      ii.   Substrate noise analysis and modeling
     iii.   TCAD tools for MEMS, actuators/sensors, bio-chip
     iv.    Tools for package-IC co-design, multi-chip and 3-D integration, PCB-interfaces, including
            thermal and mechanical effects.

In order to have a real impact on European semiconductor industry and on the related application
segments, large scale project are needed that can effectively integrated the design methods and tools

with the need the system companies that are manufacturing the applications. A project scale of around
200-400 manyear is needed in order to put together research capability in academia with design
experience in semiconductor companies and the requirements of system houses.

As an order of magnitude it can be given that the present investment in existing design tools in Europe is
already in the order of 1B$, while the total investment in design is probably 3-4 times as much. Assuming
a 10% funding for research would require around 200-250 million Euro/year. The present economical
crisis is making the need of investing in design efficiency even more urgent:
       Only those companies that are able to put new products on the market and to renew radically
        their product portfolio will survive the crisis.
       Investment in design tools and methodologies are more modular then investment in technology;
       They put more emphasis on the manpower side than on pure equipment side
       They create a know-how base, strictly connected to design community that can hardly be
        transferred elsewhere.

Assigning a relative weight to the above grand challenges is difficult. However the partitioning of present
investment in EDA tools, reported below, can give an idea of where design efforts are concentrated in
The IP tools and VHDL areas correspond to design efficiency and power efficiency, while the PCB/MCM is
related to diversification, and the physical design tools are more related to reliability and yield and
analogue design.



                PCB/MCM                                            IP & tools
                  13%                                                 15%



     Wireless Communications

        Working Group
             July 2009



We are now in a highly moving world where mobility, connectivity and data processing are ubiquitous.
The strong position of Europe today in wireless communications needs to be reinforcing in the future to
guarantee its competitiveness and make sure the industry based on nanotechnology, and all the value
                                                   chain relying on it, will remain a substantial source
                                                   of value and employment. On top of this,
                                                   emergence of new challenges such as global
                                                   warming, energy saving, population aging, will need
                                                   more and more nanotechnologies to address these
                                                   issues efficiently. The strong need for “Machine to
                                                   Machine” communication (M2M) as well as the
                                                   “Internet of Things” ranging from actuators, sensors
                                                   to controllers makes wireless communications and
                                                   nanotechnologies key technology assets to master.
 The wireless communication paradigm is expanding far beyond the pure voice communication systems
in becoming multimedia bringing audio, video, data in the picture. The pervasion of wireless
communication beyond telecommunication is now a reality, which needs to be taken into account. This
has a strong effect of making system definition and development extremely complex as more conflicting
parameters have to be very carefully managed,
making trade off much more difficult than ever.
The connectivity and the number of new
devices, on top of standards PC’s, now
accessing internet with a wireless link brings as
well another dimension in complexity. The large
amount of data, and the various types of data
with very different levels of confidentiality that
can now be stored or exchange with a mobile
device makes consistency, confidentiality and
authentication among the major issues that
security technologies have to address.
The Silicon technology evolution and the progress in embedded SW technology are the cornerstones for
the development of mobile terminals adequate for these application domains. Regarding silicon
technology, either on the “more Moore” (32nm, 22nm, etc silicon process) or in the “more than Moore”
direction” (3D Integration, etc) new areas of investigation in term of architecture and products design
open. Likewise, for what concerns embedded SW components, low footprint, high performance, and low
power, trust-worthy SW blocks are becoming a necessity.

Based on the outcomes of a document issued by a core group of partners and in line with the
recommendations expressed by the Public Authorities, the Core Group proposes three Grand
collaborative Challenges requesting a long range planning effort and close cooperation along the
whole value chain. The objective is to spur development of innovative and cost effective technologies
enabling designing and manufacturing in high volume silicon systems solutions for the wireless
communication market. The three Grand Challenges are namely:

I) Front End & Back End heterogeneous 3D integration Infrastructure:

II) Technologies for “Green” Wireless Communication:
III) Cognitive radio

I) Front End & Back End heterogeneous 3D integration Infrastructure:

Objective: Enable the development of Materials, design tools and design methodology, Manufacturing
equipments and manufacturing process for Heterogeneous integrations.

  I.1) Heterogeneous technologies integration

The integration of functions, e.g. sensing, storing, processing, actuation, communication and energy
scavenging is one of the most promising techniques for smart Microsystems in volume applications with
huge economical and social impact. But the heterogeneous integration, the multiple integration of a
variety of technological options is one of the biggest challenges semiconductor industry is facing today.
                                                             Novel tuneable metamaterial-based phase-
                                                             shifter structures utilizing active circuits are
                                                             another innovative forward-looking building
                                                             block for heterogeneous integration. MEMS
                                                             in combination of switches, varactors and
                                                             resonators with active building blocks are

another one. The integration of tuneable pre-select and post-select filters providing high Q and
simultaneously tuning over a wide range e.g. for reconfigurable radios is another challenge. Another
example is Ultra Wide Band Radar as high-resolution short range sensing technique with a variety of
application fields like alerting or non-contact measurement of human body attributes. The study of
antenna designs suitable for heterogeneous module integration is another important aspect.

The integration of very heterogeneous blocks of IP makes interconnection issues very critical
In terms of power consumption, frequency limitation, signal integrity and thermal management.
In this perspective three-dimensional (3D) approaches addressing materials issues and processes
solutions including measurement and test have to be developed in close collaboration with the
equipment makers.

I.2) Design Methodology and tools

All the new technologies needed to address issues related to the design of modern wireless
communication systems have a strong impact on design methodology and tooling. Globally the trends in
“more Moore” and in “more than Moore” have the effect of coupling domains in term of complexity
which were almost disjoints before. For instance moving to 3D packaging techniques tightly link together
thermal management system/die partitioning, power management, performance management and
hardware/software partitioning. The benefit brought by such technology in term of flexibility has to be
supported by the tooling in allowing deep investigation of the new architectural space. For example,
                                                            these    new      technologies   allow     the
                                                            cohabitation and co-existence of digital and
                                                            RF parts, the integration of power amplifiers
                                                            and of RF MEMs. It is expected that in the
                                                            near future embedded passives will be part of
                                                            the landscape. In any case, more than ever, in
                                                            order to design a coherent system, the level of
                                                            abstraction has to be raised in order to
                                                            guarantee a match between productivity of
                                                            available design resources and system
                                                            complexity. The evolution foreseen in the
                                                            memory domain, interconnection area and
packaging technology will open new opportunities in term of architecture. In order to take benefit of this
it is important that CAD tools allow efficient investigation of these new territories. On top of the large
number of additional features needed to support new design techniques, EDA vendors will have as well
to address the cost and business model issues attached with new technologies. The explosion of
complexity in the design space is as well visible in the EDA space making needs for computing power
even more crucial. In such conditions it will be important for EDA firms to think differently in providing

their customers with solution optimizing computing resources through a better usage of existing
hardware(cloud computing, GPU computing,) in order to avoid skyrocketing IT costs at their customer
As a result of the analysis of this grand challenge, the two following areas appear as a primary
importance for fostering stronger position of the European industry in designing and manufacturing
silicon systems solution for the wireless communication market:

                   Processes manufacturing for heterogeneous/3D integration
                   CAD -Tools methodology/partitioning for heterogeneous/3D integration

The expected impact is to position
Europe as a major player in the
design and production of complex
silicon systems. This objective will be
achieved by placing a priority on the
integration technologies of the
future, and by encouraging intensive
collaborations between ICs industry,
CAD tools vendors and equipments
makers .In addition, by intensifying
the research efforts and by involving
all the players throughout the value chain, it will be possible to spur the development of innovative
silicon solutions and to strengthen the position of European firms in the global market. This 3D initiative
will also be instrumental to keep and foster on the European soil advanced manufacturing facilities..

II) Technologies for “Green” Wireless Communication:

The convergence scenario of consumer, computer and communication electronic systems requires an
exponential growth of code and data in all electronic systems. This is because more communication
protocols should be supported by a single device, more multimedia operations should be executed in the
embedded processors, more bandwidth should be allocated to wired/wireless communication channels,
more security checks should be performed on the fly, etc. The paradox is that in order to cope with a
green policy, the required power dissipation for operating these devices should feature a sub-linear

dependence on their complexity, or in other words, the number of operations to be executed per Joule
should increase.
In order to attain this target, a holistic approach is required and three R&D priorities are essential:

 II.1- System power profiling.

  At system level, well before the realization of the platform, the power consumption profile of the
 elementary HW and SW components should be estimated and the system architecture should be fine-
 tuned in order to make the very best balance between performance and power consumption. The Si
 process to be used for implementing the HW components should be compatible with lower power
 supply voltages and should feature reduced leakage currents. The design flow should support well-
 known power saving techniques. To some extend, the introduction of asynchronous features should be
 also supported. The firmware should be of reduced power and the SW development environment
 should allow the comparison of SW components in terms of power consumption and performance
 (power aware SW).

 II.2-Ultra Low power technologies

Because of power consumption, and flexibility, size and cost, the next generations of wireless systems
will require new technologies and architectures that combine adaptability and performances in a novel
Technologies to be developed have to cope with the never-ending list of new functions to be
embedded in a mobile .The only mandatory limitations are the decrease of the cost per function
and the consumption per function. For the digital parts the requirements will still be the increase
in density and speed but with a decrease of power consumption. High-k metal gate (HKMG)
Technologies will certainly be the best choice further pushing down MOS gate length to 20 nm
and lower and to produce high-speed signal processing with very low power consumption.
HKMG technologies will be instrumental to extend battery life for the new generations of handset
devices. The other key active elements at the forefront of microelectronics end product
functionality are the memory chips. This is true for cell phone handsets, broadband devices, and
 The memory system, with his implications in terms of densities, technology performance, packaging and
interfacing, becomes more and more of interest in order to improve the overall electronic system
performance. At high-level “convergent” electronic system performance are measured in term of
bandwidth, to speed up Internet connection, and power consumption reduction, to enhance the
nomadic use. Improvement of Non-volatility solid state is the best way to reduce power consumption.

II.3- Energy harvesting

This holistic approach would be of reduced efficiency without the proper management of the battery
system. It is expected that energy harvesting will enhance substantially the autonomy of handheld
communication devices and will make them much friendlier to the environment. In fact the emerging of
more and more wireless autonomous devices will require a lot of improvement in power consumption
but as well in energy scavenging and energy storage technology. For examples, RF, thermal or vibration
energy harvesting could be an option. This will be strongly reinforced by the various environmental
regulations on going about energy management that devices will have to be compliant with, in order to
efficiently address the global warming problem.

Topics to be addressed:

             System power profiling
             More Bits per Joule
             Low leakage process
             Ultra low power design techniques
             Power aware SW
             Energy harvesting.

III) Cognitive radio:

Objective: to demonstrate the feasibility single chip cognitive baseband and Application Processor ICs.
Co-habitation in a single package of a baseband and Application Processor IC with the RF/IF stage, LNAs,
Power Amplifiers, and SAW filters, Antenna Switch and the Antenna via a 3D integration scheme.

The next generations of wireless communication systems will be able to communicate with various
heterogeneous systems, in this perspective cognitive radio architectures have to be implemented for
both RF front end and digital baseband.

III-1 RF Front end
                                                                           All- Communicating
In the past 10 years the wireless connectivity has really          Bluetooth   GPS
exploded as devices are now connected to a large number of
systems and networks with very different properties. The                                      GPR
                                                                  UWB                        DVB-H
                                                                                              E,      34
                                                                 NFC                          MA,
main driving factors in this domain are the mobility, continuity/quality of service and the data exchanged
Convergence requires that connectivity links developed, targeting originally fixed or pedestrian terminals
(802.11 a/b/g W-LAN), can be extended to mobility, e.g. 802.11p Wireless Access in Vehicular
Environment. The increased demand for data traffic, for file transfer or Internet application, is driving the
need for high data rate, high spectral efficient and low power connectivity. Latest Connectivity
technology is moving toward the exploitation of new spectrum region, in the range of mmWave (i.e.
across 60GHz), as recently addressed in IEEE 802.11ad or other consortia (Wireless HD, …) with the
challenge to develop RF components capable to handle 2GHz bandwidth that could be allocated to each
single link. Further consolidated trend is the adoption of Multiple Antennas Transmitting and Receiving
(MIMO) with the aim of increasing robustness and or throughput of the link such as recently addressed
by IEEE W-LAN 802.11n. The number of antennas or transmitting/receiving nodes in a mobile device is
already very important like cellular network, WLAN, GPS, Blue tooth, FM Radio, mobile TV, High data
rates are also addressed by wired in house connectivity links as Power Line communications, the next
generation addressing from 200MBit/s up to 1GBit/s for Multimedia contents distribution.

Due to the number of interfaces to integrate in a low volume device, the RF problem is becoming a real
headache in mobile systems. The increasing data throughput linked to multimedia and Internet browsing
is making the situation even worst. New solutions are absolutely needed. SDR (Software Defined Radio)
are very important, as it is a way to manage diversity in term of radio interfaces while maximizing
hardware and software resources. It is also an interesting solution to cope with not yet fully stable
standards or standards variants for specific markets. The emergence of new wireless devices on top of
mobile phone makes mandatory a better utilization of radio spectrum. This means that wireless devices
have to be aware of their environment in order to use at best available resources. Cognitive radios
techniques are then crucial, as it is a way to sense the environment and to optimize the quality of service
parameters in a crowdie RF spectrum. The increasing complexity of radio sub systems makes their
manufacturing very tricky. In order to keep acceptable figures in term of performance and cost, it is
mandatory to have systems capable to compensate imperfect radio interface in order to maximize
manufacturing yields.

Topics to be addressed:

             Wireless sensors
             MIMO 802.11n, 802.16
             802.11ad/WirelessHD mmWave technology for high bit-rate communication (multiple
             802.11p Wireless Access in Vehicular Environment (WAVE)
             HSPA, LTE, LTE Advanced
             Seamless transition between radio’s
             Multiple wireless interfaces in UICC cards or modules (Zigbee, UWB,..)

III.2 Digital baseband

Towards cognitive radio the digital baseband processing of such an extremely agile system is a highly
challenging task. In fact agility is a key factor in a rapid moving world and more especially in wireless
communication. If agility starts to be understood in software or hardware development methodologies,
it needs a strong support at architecture level to be able to fully express its efficiency. The new
technologies either in term of packaging or on the memory front for instance are adding much more
capabilities to be agile. It must be possible to explore much more rapidly the architectural space
independently of hardware/hardware portioning (3D integration,), hardware/software partitioning
(trade off in power consumption, flexibility, …) or software/software partitioning (heterogeneous
multiprocessors systems, ..).
 The new ways to develop hardware, through
reconfigurable hardware or processors arrays to cope               All-achieving
with the constraints brought by new silicon process                          TV
                                                          Modem                     MP3
nodes in addition to new memory technology in term of               Phone
speed, power consumption and non volatility are
opening new territories to architecture investigation                              Radio
and then agility. On the software side it is now
mandatory to preserve as much as possible the                                        Web
software assets as their development cost is overtaking
                                                          Gaming                 er
hardware development ones. To do so it is fundamental                             GPS
to reduce as much as possible hardware dependency
for the software. All the techniques such as
virtualization, late binding with dynamic compilation, components based design, constrained
programming (power consumption, memory footprint, performance,..), higher programming languages
are potential solutions to this problem.
The emergence of heavily multiprocessors based systems brings as well additional needs in term of tools,
covering development, application parallelization, debugging, profiling, …To ensure Europe
competitiveness in wireless communication, the following topics will need to be addressed in the scope
of collaborative projects.

Topics to be addressed:

            Dynamic hardware, software partitioning
            Virtualization, Dynamic compilation
            Components based software re-use and associated specific description language
            Hardware and software re-configurability
            Multiprocessing

                “Evolutive” 3D architecture (at packaging level)
                Memories (speed, power, retention) – new kinds of volatile and non-volatile e.g. SSD PCM,
                External secure storage

III.3 Security

As part of the Cognitive radio challenge, a new security paradigm is requested by more and more
communicating applications, more mobile users and more distributed data. Thus securing services or
data and providing proper protection evidences is becoming increasingly important and difficult in
advanced, open wireless and fully mobile devices. End-users, OEMs, ISVs, content owners, service
providers and operators have different, sometimes diverging needs and should have differentiated
privileges towards terminal resources. Robust stakeholders’ segregation, security policy enforcement
and mutual assets isolation is a challenge in increasingly open “computing” devices exposed and
vulnerable to everyday new malware, software and hardware attacks. Increasing interoperability, trust
and flexibility requirements are bringing standardization and security evaluation challenges. Finally the
ever-increasing security complexity should remain transparent to the end-user, which is stressing the
security performance and efficiency dimensions.

Addressing these security challenges involves

                Open trusted platforms, with flexible secure boot, securing run time integrity. Logic
                 security plus highly secure peripherals such secure smart cards. Trusted execution
                 environments in hardware and software with trust zone for application processors. Secure
                 access to I/O facilities including radio links
                Identification and authentication
                Secure storage, file system encryption
                Adaptable security features, flexible enough to allow new counter measures and
                 algorithms deployed over time. Multi-factor attack management and prevention
                Incremental certification, software quality measures, formal tools for security and
                 embedded SW test verification

                                 Silicon Process and Integration4

Michel, pls. insert your text here.
I reproduced your slides for this version.

    As a suggestion the workgroup on Wireless Communication has formulated their needs for Silicon Process

                                                    09-08-04 Silicon for
                                                    wireless communications.doc
Improvement. It is embedded here for information.

Association for E uropean NanoE lectronics ActivitieS

                           Si process &
                        process integration
                                  Grand challenges

      Si process and process integration
       Nanoelectronic technologies: a key asset for Europe
  • many societal challenges can’t be addressed
            without mastering nanoelectronic technology developments, e.g.:
                 − ubiquitous communication
                 − “green” economy (transportation, energy, ICT…)
                 − energy-efficiency and smart grid
                 − technical textiles
                 − etc.
  • the microelectronic technologies enable applications driving 10% of the GDP
  • a global market of ca. $250B with an European market share of ca. 15%
  • a highly innovative industry (ca. 20% in R&D) cooperating in enabling technologies
  • this industry is mostly driven by big companies
            which generate a substantial value chain (incl. SME’s) across Europe
  • this industry is heavily subsidized in other regions (Asia, US)

             need for an European industrial policy in nanoelectronics

                                                            R&D is a part of this policy

 2       Sources: ESIA 2008 Competitiveness Report & market data

    Si process and process integration
                             Overarching challenge:
                            generic process platforms for
                      more functions / volume at affordable cost

                           More Moore          More-than-Moore
                             scaling             diversification
                           more Tr/mm²          more functionality

                                   more functions/mm3


    Si process and process integration
             More Moore (MM) landscape & needs
For advanced CMOS
• some European companies going fablite or fabless
     → need to understand & specify the next generation CMOS in foundries
• some European companies keep in-house manufacturing capability
     → development & qualification made in European facilities
           using an early CMOS R&D mostly done in the IBM cluster
           ⇒ need CMOS R&D in Europe for technology appropriation in Europe
• emergence of a Western foundry producing in Europe
     → new opportunity to compete with Asia
• significant microprocessor production in Europe (Dublin & Dresden)
     but a risk to move more production outside of Europe
     → enhance the CMOS expertise to attract more production in Europe
• best in class European R&D centers which don’t exist elsewhere in the world
     → need to maintain the viability and expertise of these centers
• few leading regions / clusters with a spill-over effect all over Europe (supply chain)
• transition to the 450mm platform for advanced CMOS technologies
     → develop CMOS processes capable at 450mm
           to maintain Europe at the leading edge of CMOS R&D
4                These trends are accelerated by the crisis

        Si process and process integration
              More Moore (MM) landscape & needs
    For advanced memory technologies

    Industrial landscape
    •    memories are 25% of overall semiconductor market, almost equally
         divided between DRAM and Flash.
    •    Memories are critical components in all communication systems.
    •    Stand-alone DRAM industry disappeared from Europe
    •    Innovative NVM companies active in Europe
    Research Opportunities
    •    Conventional memory technology (Flash and DRAM) is reaching its
         physical limits in the next year.
    •    Strong European leadership on research in time of disruptive changes:
           R&D centers which don’t exist elsewhere in the world
           The only company on the market with next generation PCM memory


        Si process and process integration
                 More Moore (MM) grand challenge

                     Maintain through R&D leadership
                the ability of the European industry to define
          the development and manufacturing of advanced CMOS

        Expected benefit:
           • Control the access for Europe to advanced CMOS
               which enables innovation in electronics-enhanced systems & applications
           • Maintain & expand the supply chain existing in Europe


       Si process and process integration
                                   More Moore (MM) strategy
        • technology push enabling high value-added applications
        • need to maintain R&D and expertise in Europe
        • critical size obtained only at the European level
        • in other regions strong involvement of PA’s for supporting this industry

                                     Europe-wide public initiative on…

                            core CMOS                                            NVM

                  one project every 2-3 yrs.(*)                      few projects every 2 yrs.(*)
                  typ. size 1,000+ p.y                               typ. size ca. 400 p.y

        (*)   in line with the pace of technology generations in the ITRS

       Si process and process integration
                         More-than-Moore (MtM) landscape
    MtM = concept and domain where
            Europe leads &
            disruptive technologies are likely to enable new applications
    Diversified technologies
              driven by societal needs & applications
              operating through different business models and supply chains
                 • rf devices (rf interfaces, antennas…)
                 • power / high voltage devices
                 • imaging devices
                                                                    development of
                                                                    processes & devices
                 • photonics on Si
                                                                    applicable to many applications domains
                 • sensors & actuators
                 • biochips

    Historical synergy in Europe between system / application companies
              and device suppliers (incl. SME’s)

    Strong R&D and manufacturing base widely spread all over Europe

                 Si process and process integration
                          More-than-Moore (MtM) grand challenge

                                        Grand challenge: make Europe lead
                                     the worldwide R&D in More-than-Moore

                  Expected benefit:
                     • Set the pace of MtM R&D worldwide
                          as US (and recently Asia) did through ITRS in the MM domain
                     • Maintain the synergy between technology and applications
                          all over Europe and expand the industrial base


               Si process and process integration
                                More-than-Moore (MtM) strategy
                   • strong involvement of PA’s in setting the landscape
                        (regulations, standards, lead markets…)
                   • more synergy along the value chain at the European level
                   • generic technologies developed for a broad range of applications
                        to leverage the high product development cost

                               Europe-wide PPP on generic technologies(*) for…
                                                     • rf devices
                                                     • power / high voltage devices
                                                     • imaging devices
                                                     • sensors & actuators
                                                     • biochips
                                                                                          few projects / domain every 2 yrs.
                                                                                          typ. size ca. 250 p.y
                                                                                          with a wide participation over Europe

           application-specific technologies will be developed in the lead applications of ENIAC
10                                   or through other R&D programs

     Si process and process integration
     3D/SiP Heterogeneous Integration (HI) landscape
• integrated complex systems need more and more
          high performance computing and information storage (MM)
          along with dedicated devices (MtM) [interfaces and energy / power]
           integrated in a single package
• in many cases integration on a single chip doesn’t bring any competitive advantage
          e.g. advanced CMOS with high cost / mm² integrated with large area sensors
• components will be supplied from many sources, part of them outside of Europe
• integration technologies driven by classes of applications
• historical synergy in Europe between system / application companies
          and technology suppliers (incl. SME’s)
• leading R&D centers in Europe
• standards for SiP are underdeveloped
• the supply chain of 3D/SiP is not firmly established yet worldwide

     opportunity for Europe to take a significant position as a SiP leader worldwide

     Si process and process integration
            3D/SiP Heterogeneous Integration (HI)
                      grand challenge

              Grand challenge: develop an European SiP supply chain
                               for innovative systems
                  integrating advanced CMOS & European MtM

      Expected benefit:
         • Put Europe as one of the few worldwide leaders
              for heterogeneous integration of complex systems
         • Synergize the European leadership on MtM and
              the expertise on MM


     Si process and process integration
     3D/SiP Heterogeneous Integration (HI) strategy

      Many technologies to be addressed in an holistic approach

         • system-level co-design (*)
         • wafer-level integration
         • module integration
                                                        development of generic processes
         • 3D integration
                                                        and 3D / SiP standards
         • interconnection & interposers
                                                        applicable to many applications domains
         • assembly & packaging
         • test (incl. KGD)
         • reliability

                                                             few projects / domain every 2 yrs.
                                                             typ. size ca. 200 to 300 p.y
                                                             with a wide participation over Europe

       (*)   addressed in the ENIAC chapter on “Design methodologies and tools”


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