ARM_architecture by zzzmarcus

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ARM architecture

ARM architecture
ARM Designer Bits Introduced Version Design Type Encoding Branching Endianness Extensions Registers 16 ARM Limited 32-bit 1983 ARMv7 RISC Register-Register Fixed Condition code Bi NEON

world.[3][4][5] The ARM architecture is used in about 3/4 of all 32 bit processors sold.[6]

History

A Conexant ARM processor used mainly in routers The ARM design was started in 1983 as a development project at Acorn Computers Ltd to build a compact RISC CPU. Led by Sophie Wilson and Steve Furber, a key design goal was achieving low-latency input/output (interrupt) handling like the MOS Technology 6502 used in Acorn’s existing computer designs. The 6502’s memory access architecture allowed developers to produce fast machines without the use of costly direct memory access hardware. The team completed development samples called ARM1 by April 1985,[7] and the first "real" production systems as ARM2 the following year. The ARM2 featured a 32-bit data bus, a 26-bit (64 Mbyte) address space and sixteen 32-bit registers. Program code had to lie within the first 64 Mbyte of the memory, as the program counter was limited to 26 bits because the top 6 bits of the 32-bit register served as status flags. The ARM2 was possibly the simplest useful 32-bit microprocessor in the world, with only 30,000 transistors (compare with Motorola’s six-year older 68000 model with around 70,000 transistors). Much of this simplicity comes from not having microcode (which represents about one-quarter to one-third of the 68000) and, like most CPUs of the day, not including any cache. This simplicity led to its low

The ARM architecture (previously, the Advanced RISC Machine, and prior to that Acorn RISC Machine) is a 32-bit RISC processor architecture developed by ARM Limited that is widely used in embedded designs. ARM CPUs are dominant in the mobile electronics market. As of 2007, about 98 percent of the more than a billion mobile phones sold each year use at least one ARM CPU.[1] According to the manufacturer, the ARM family accounts for approximately 90% of all embedded 32-bit RISC CPUs as of April 2009.[2] ARM CPUs are found in most corners of consumer electronics, from portable devices (PDAs, mobile phones, iPods and other digital media and music players, handheld gaming units, and calculators) to computer peripherals (hard drives, desktop routers). However, since the decline of ARM Ltd’s former parent company Acorn Computers, it no longer designs chips oriented towards desktop functions, and has never been used in a supercomputer or cluster. Prominent branches in this family include Marvell’s (formerly Intel’s) XScale, the ST-Ericsson’s (formerly ST Microelectronics) NOMADIK series and the Texas Instruments OMAP series. The ARM architecture is the most widely used 32-bit CPU architecture in the

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power usage, while performing better than the Intel 80286.[8] A successor, ARM3, was produced with a 4KB cache, which further improved performance. In the late 1980s Apple Computer and VLSI Technology started working with Acorn on newer versions of the ARM core. The work was so important that Acorn spun off the design team in 1990 into a new company called Advanced RISC Machines Ltd. For this reason, ARM is sometimes expanded as Advanced RISC Machine instead of Acorn RISC Machine. Advanced RISC Machines became ARM Ltd when its parent company, ARM Holdings plc, floated on the London Stock Exchange and NASDAQ in 1998.[9] The new Apple-ARM work would eventually turn into the ARM6, first released in early 1992. Apple used the ARM6-based ARM 610 as the basis for their Apple Newton PDA. In 1994, Acorn used the ARM 610 as the main CPU in their Risc PC computers. DEC licensed the ARM6 architecture (which caused some confusion because they also produced the DEC Alpha) and produced the StrongARM. At 233 MHz this CPU drew only 1 watt of power (more recent versions draw far less). This work was later passed to Intel as a part of a lawsuit settlement, and Intel took the opportunity to supplement their aging i960 line with the StrongARM. Intel later developed its own high performance implementation known as XScale which it has since sold to Marvell. The ARM core has remained largely the same size throughout these changes. ARM2 had 30,000 transistors, while the ARM6 grew to only 35,000. ARM’s business has always been to sell IP cores, which licensees use to create microcontrollers and CPUs based on this core. The most successful implementation has been the ARM7TDMI with hundreds of millions sold in almost every kind of microcontroller equipped device. The idea is that the Original Design Manufacturer combines the ARM core with a number of optional parts to produce a complete CPU, one that can be built on old semiconductor fabs and still deliver substantial performance at a low cost. ARM licensed about 1.6 billion cores in 2005. In 2005, about 1 billion ARM cores went into mobile phones.[10] As of January 2008, over 10 billion ARM cores have been built, and iSuppli predicts that 5 billion a year will ship in 2011.[11]

ARM architecture
The common architecture supported on smartphones, Personal Digital Assistants and other handheld devices is ARMv4. XScale and ARM926 processors are ARMv5TE, and are now more numerous in high-end devices than the StrongARM, ARM925T and ARM7TDMI based ARMv4 processors.

ARM cores Design notes
To keep the design clean, simple and fast, it was hardwired without microcode, like the much simpler 8-bit 6502 processor used in prior Acorn microcomputers. The ARM architecture includes the following RISC features: • Load/store architecture • No support for misaligned memory accesses (now supported in ARMv6 cores, with some exceptions related to load/store multiple word instructions) • Uniform 16 × 32-bit register file • Fixed instruction width of 32 bits to ease decoding and pipelining, at the cost of decreased code density. (Later, "Thumb mode" increased code density.) • Mostly single-cycle execution To compensate for the simpler design, compared with contemporary processors like the Intel 80286 and Motorola 68020, some unique design features were used: • Conditional execution of most instructions, reducing branch overhead and compensating for the lack of a branch predictor • Arithmetic instructions alter condition codes only when desired • 32-bit barrel shifter which can be used without performance penalty with most arithmetic instructions and address calculations • Powerful indexed addressing modes • A link register for fast leaf function calls. • Simple, but fast, 2-priority-level interrupt subsystem with switched register banks An interesting addition to the ARM design is the use of a 4-bit condition code on the front of every instruction, meaning that execution of every instruction is optionally conditional. Other CPU architectures typically only have condition codes on branch instructions. This cuts down significantly on the encoding bits available for displacements in

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Family ARM1 Architecture Core Version ARMv1 ARM1 Feature Cache (I/ D)/MMU None

ARM architecture
Typical MIPS @ MHz

I

A te fo 4 MIPS @ 8 MHz 0.33 DMIPS/MHz

ARM2

ARMv2

ARM2

Architecture 2 None added the MUL (multiply) instruction Integrated None, MEMC1a MEMC (MMU), Graphics and IO processor. Architecture 2a added the SWP and SWPB (swap) instructions. First use of a processor cache on the ARM. 4K unified

A C

ARMv2a

ARM250

7 MIPS @ 12 MHz

A

ARM3

ARMv2a

ARM2a

12 MIPS @ 25 MHz 0.50 DMIPS/MHz

A

ARM6

ARMv3

ARM60

v3 architecture None first to support addressing 32 bits of memory (as opposed to 26 bits) As ARM60, 4K unified cache and coprocessor bus (for FPA10 floating-point unit). As ARM60, cache, no coprocessor bus. 4K unified

10 MIPS @ 12 MHz

3 p R

ARM600

28 MIPS @ 33 MHz

ARM610

17 MIPS @ 20 MHz 0.65 DMIPS/MHz 40 MHz 40 MHz 40 MHz 0.68 DMIPS/MHz 18 MHz

A A s

ARM7

ARMv3

ARM700 ARM710 ARM710a ARM7100 As ARM700 As ARM700 As ARM710a, integrated SoC. As ARM710a, integrated SoC. As ARM7500, "FE" Added

8 KB unified 8 KB unified 8 KB unified 8 KB unified

A ty

A

A A

P

ARM7500

4 KB unified

40 MHz

A

ARM7500FE

4 KB unified

56 MHz 0.73 DMIPS/MHz

A

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FPA and EDO memory controller. ARM7TDMI ARMv4T ARM7TDMI(-S) 3-stage pipeline, Thumb none

ARM architecture

15 MIPS @ 16.8 MHz

G N L A N L

ARM710T

As ARM7TDMI, 8 KB unified, cache MMU As ARM7TDMI, 8 KB unified, cache MMU with Fast Context Switch Extension As ARM7TDMI, MPU cache 5-stage none pipeline, Thumb, Jazelle DBX, Enhanced DSP instructions 16 KB/16 KB, MMU

36 MIPS @ 40 MHz

P P D

ARM720T

60 MIPS @ 59.8 MHz

Z g o

ARM740T ARMv5TEJ ARM7EJ-S

StrongARM ARMv4

SA-110

203 MHz 1.0 DMIPS/MHz

A s R N C

SA-1110

As SA-110, integrated SoC

16 KB/16 KB, MMU

233 MHz

L A B S 7 s

ARM8

ARMv4

ARM810[12]

5-stage 8 KB unified, pipeline, static MMU branch prediction, double-bandwidth memory

84 MIPS @ 72 MHz 1.16 DMIPS/MHz

A ty

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ARM9TDMI ARMv4T ARM9TDMI 5-stage pipeline, Thumb none

ARM architecture

ARM920T

As ARM9TDMI, 16 KB/16 KB, cache MMU

200 MIPS @ 180 MHz A (f Z M H S g E S (H F

ARM922T ARM940T

As ARM9TDMI, 8 KB/8 KB, MMU caches As ARM9TDMI, 4 KB/4 KB, MPU caches

N L

G M e

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From Wikipedia, the free encyclopedia
ARM9E ARMv5TE ARM946E-S

ARM architecture
Thumb, Envariable, tightly hanced DSP in- coupled memorstructions, ies, MPU caches Thumb, Enhanced DSP instructions no cache, TCMs

N G S 8

ARM966E-S

S c

ARM968E-S ARMv5TEJ ARM926EJ-S

As ARM966E-S no cache, TCMs Thumb, Jazelle variable, TCMs, DBX, Enhanced MMU DSP instructions

N L

220 MIPS @ 200 MHz, M E S s T O O O O L M M M M M M M F i. A c G F C S c w u S u D N F M

ARMv5TE

ARM996HS

Clockless processor, as ARM966E-S

no caches, TCMs, MPU

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ARM10E ARMv5TE ARM1020E

ARM architecture
6-stage 32 KB/32 KB, pipeline, MMU Thumb, Enhanced DSP instructions, (VFP) As ARM1020E 16 KB/16 KB, MMU

ARM1022E ARMv5TEJ ARM1026EJ-S

Thumb, Jazelle variable, MMU DBX, Enhanced or MPU DSP instructions, (VFP)

W M E

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XScale ARMv5TE 80200/IOP310/ I/O Processor, IOP315 Thumb, Enhanced DSP instructions 80219 IOP321 IOP33x IOP34x PXA210/ PXA250

ARM architecture

400/600 MHz 600 BogoMips @ 600 MHz 1-2 core, RAID 32K/32K L1, Acceleration 512K L2, MMU Applications processor, 7-stage pipeline 32KB/32KB, MMU PXA210: 133 and 200 MHz, PXA250: 200, 300, and 400 MHz

T

Iy

Z H N

PXA255

400 BogoMips @ G 400 MHz; 371-533 n [18] E MIPS @ 400 MHz M d

PXA263 PXA26x PXA27x Applications processor 32 KB/32 KB, MMU

200, 300 and 400 MHz S N default 400 MHz, up to 624 MHz

P

800 MIPS @ 624 MHz G U Z 3 A s B G M A A E R F N G Z 1000 MIPS @ 1.25 GHz

PXA800(E)F Monahans PXA900 32KB/32KB L1, TCM, MMU

B B (8 Control Plane Processor

IXC1100

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IXP2400/ IXP2800 IXP2850 IXP2325/ IXP2350 IXP42x ARM11 ARMv6 ARM1136J(F)S[19]

ARM architecture

N 8-stage variable, MMU pipeline, SIMD, Thumb, Jazelle DBX, (VFP) 740 @ 532-665 MHz (i.MX31 SoC), 400-528 MHz

T O E N Z N a (w A c in T F (u Z G M E 5 N N M th to

ARMv6T2

ARM1156T2(F)- 9-stage variable, MPU S pipeline, SIMD, Thumb-2, (VFP) ARM1176JZ(F)- As variable, S ARM1136EJ(F)- MMU+TrustZone S

ARMv6KZ

A iP C R R G

ARMv6K

ARM11 MPCore

As variable, MMU ARM1136EJ(F)S, 1-4 core SMP

N

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Cortex ARMv7-A Cortex-A8

ARM architecture
Application variable (L1+L2), profile, VFP, MMU+TrustZone NEON, Jazelle RCT, Thumb-2, 13-stage superscalar pipeline up to 2000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1 GHz)

T O S S O O A i. B

Cortex-A9

Application MMU+TrustZone 2.0 DMIPS/MHz profile, (VFP), (NEON), Jazelle RCT and DBX, Thumb-2, Outof-order speculative issue superscalar As Cortex-A9, 1-4 core SMP MMU+TrustZone 2.0 DMIPS/MHz

Cortex-A9 MPCore

T O " (p

ARMv7-R

Cortex-R4(F)

Embedded pro- variable cache, file, Thumb-2, MPU optional (FPU) Microcontroller no cache, MPU profile, Thum- optional b-2 only.

600 DMIPS @ ~375MHz 125 DMIPS @ 100 MHz

B T In

ARMv7-M

Cortex-M3

E E c fa tr S L T

ARMv6-M

Cortex-M0

Microcontroller No cache. profile, Thumb-2 (16-bit Thumb instructions & BL, MRS, MSR, ISB, DSB, and DMB). FPGA targeted, None, tightly Microcontroller coupled memory profile, Thum- optional. b-2 (16-bit Thumb instructions & BL, MRS, MSR, ISB, DSB, and DMB). Feature Cache (I/ D)/MMU

0.9 DMIPS/MHz

N L S

Cortex-M1

Up to 136 DMIPS @ 170 MHz[22] (0.8 DMIPS/MHz,[23] MHz achievable FPGAdependent)

A P F te F a S

[2

Family

Architecture Core Version

Typical MIPS @ MHz

I

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From Wikipedia, the free encyclopedia
memory access instructions, but on the other hand it avoids branch instructions when generating code for small if statements. The standard example of this is the Euclidean algorithm: In the C programming language, the loop is:

ARM architecture

two-byte quantity, thus, strictly speaking, for them it’s not possible to generate code that would behave the way one would expect for C objects of type "volatile int16_t" The ARM7 and earlier designs have a three stage pipeline; the stages being fetch, decode, and execute. Higher performance designs, such as the ARM9, have a five stage while (i != j) pipeline. Additional changes for higher per{ formance include a faster adder, and more if (i > j) extensive branch prediction logic. i -= j; The architecture provides a non-intrusive else way of extending the instruction set using j -= i; "coprocessors" which can be addressed using } MCR, MRC, MRRC and MCRR commands from software. The coprocessor space is diIn ARM assembly, the loop is: vided logically into 16 coprocessors with numbers from 0 to 15, coprocessor 15 (cp15) being reserved for some typical control funcloop CMP Ri, Rj ; set condition "NE" if (i != j) tions like managing the caches and MMU op; "GT" if (i > j), eration (on processors that have one). ; or "LT" if (i < j) In ARM-based machines, peripheral SUBGT Ri, Ri, Rj ; if "GT", i = i-j; devices are usually attached to the processor SUBLT Rj, Rj, Ri ; if "LT", j = j-i; by mapping their physical registers into ARM BNE loop ; if "NE", then loop memory space or into the coprocessor space or connecting to another device (a bus) which which avoids the branches around the then in turn attaches to the processor. Coproand else clauses. cessor accesses have lower latency so some Another unique feature of the instruction peripherals (for example XScale interrupt set is the ability to fold shifts and rotates into controller) are designed to be accessible in the "data processing" (arithmetic, logical, both ways (through memory and through and register-register move) instructions, so coprocessors). that, for example, the C statement a += (j << 2); Thumb could be rendered as a single word, single cycle instruction on the ARM. ADD Ra, Ra, Rj, LSL #2 This results in the typical ARM program being denser than expected with fewer memory accesses; thus the pipeline is used more efficiently. Even though the ARM runs at what many would consider to be low speeds, it nevertheless competes quite well with much more complex CPU designs. The ARM processor also has some features rarely seen in other RISC architectures, such as PC-relative addressing (indeed, on the ARM the PC is one of its 16 registers) and pre- and post-increment addressing modes. Another item of note is that the ARM has been around for a while, with the instruction set increasing somewhat over time. Some early ARM processors (prior to ARM7TDMI), for example, have no instruction to store a To improve compiled code-density, processors from the ARM7TDMI on have featured the Thumb mode. When in this mode, the processor executes 16-bit instructions. Most of these 16-bit-wide Thumb instructions are directly mapped to normal ARM instructions. The space-saving comes from making some of the instruction operands implicit and limiting the number of possibilities compared to the full ARM mode instruction. In Thumb, the smaller opcodes have less functionality. For example, only branches can be conditional, and many opcodes are restricted to accessing only half of all of the CPU’s general purpose registers. The shorter opcodes give improved code density overall, even though some operations require extra instructions. In situations where the memory port or bus width is constrained to less than 32 bits, the shorter Thumb opcodes allow increased performance compared with 32-bit

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ARM code, as less program code may need to be loaded into the processor over the constrained memory bandwidth. Embedded hardware, such as the Game Boy Advance, typically have a small amount of RAM accessible with a full 32-bit datapath; the majority is accessed via a 16 bit or narrower secondary datapath. In this situation, it usually makes sense to compile Thumb code and hand-optimise a few of the most CPU-intensive sections using full 32-bit ARM instructions, placing these wider instructions into the 32-bit bus accessible memory. The first processor with a Thumb instruction decoder was the ARM7TDMI. All ARM9 and later families, including XScale, have included a Thumb instruction decoder.

ARM architecture
set. Other chips in the Cortex and ARM11 series support both "ARM instruction set mode" and "Thumb-2 instruction set mode".[26][27][28]

Thumb Execution Environment (ThumbEE)
ThumbEE, also known as Thumb-2EE, and marketed as Jazelle RCT (Runtime Compilation Target), was announced in 2005, first appearing in the Cortex-A8 processor. ThumbEE provides a small extension to the Thumb-2 extended Thumb instruction set, making the instruction set particularly suited to code generated at runtime (e.g. by JIT compilation) in managed Execution Environments. ThumbEE is a target for languages such as Limbo, Java, C#, Perl and Python, and allows JIT compilers to output smaller compiled code without impacting performance. New features provided by ThumbEE include automatic null pointer checks on every load and store instruction, an instruction to perform an array bounds check, access to registers r8-r15 (where the Jazelle/DBX Java VM state is held), and special instructions that call a handler.[29] Handlers are small sections of frequently called code, commonly used to implement a feature of a high level language, such as allocating memory for a new object.

DSP Enhancement Instructions
To improve the ARM architecture for digital signal processing and multimedia applications, a few new instructions were added to the set.[25] These are signified by an "E" in the name of the ARMv5TE and ARMv5TEJ architectures. E-variants also imply T,D,M and I. The new instructions are common in digital signal processor architectures. They are variations on signed multiply-accumulate, saturated add and subtract, and count leading zeros.

Jazelle
Jazelle is a technique that allows Java Bytecode to be executed directly in the ARM architecture as a third execution state alongside the existing ARM and Thumb-mode.

Advanced SIMD (NEON)
The Advanced SIMD extension, marketed as NEON technology, is a combined 64 and 128 bit SIMD (Single Instruction Multiple Data) instruction set that provides standardized acceleration for media and signal processing applications. NEON can execute MP3 audio decoding on CPUs running at 10 MHz and can run the GSM AMR (Adaptive Multi-Rate) speech codec at no more than 13 MHz. It features a comprehensive instruction set, separate register files and independent execution hardware. NEON supports 8-, 16-, 32- and 64-bit integer and single precision floatingpoint data and operates in SIMD operations for handling audio/video processing as well as graphics and gaming processing. In NEON, the SIMD supports up to 16 operations at the same time.

Thumb-2
Thumb-2 technology made its debut in the ARM1156 core, announced in 2003. Thumb-2 extends the limited 16-bit instruction set of Thumb with additional 32-bit instructions to give the instruction set more breadth. The resulting stated aim for Thumb-2 is to achieve code density similar to Thumb with performance similar to the ARM instruction set on 32-bit memory. Thumb-2 also extends both the ARM and Thumb instruction set with yet more instructions, including bit-field manipulation, table branches, and conditional execution. All ARMv7 chips support the Thumb-2 instruction set. Some chips, such as the CortexM3, support only the Thumb-2 instruction

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ARM architecture
controlling the use of media on ARM-based devices,[30] and preventing any unapproved use of the device. In practice, since the specific implementation details of TrustZone are proprietary and have not been publicly disclosed for review, it is unclear what level of assurance is provided for a given threat model.

VFP
VFP technology is a coprocessor extension to the ARM architecture. It provides low-cost single-precision and double-precision floating-point computation fully compliant with the ANSI/IEEE Std 754-1985 Standard for Binary Floating-Point Arithmetic. VFP provides floating-point computation suitable for a wide spectrum of applications such as PDAs, smartphones, voice compression and decompression, three-dimensional graphics and digital audio, printers, set-top boxes, and automotive applications. The VFP architecture also supports execution of short vector instructions allowing SIMD (Single Instruction Multiple Data) parallelism. This is useful in graphics and signal-processing applications by reducing code size and increasing throughput. Other floating-point and/or SIMD coprocessors found in ARM-based processors include FPA, FPE, iwMMXt. They provide some of the same functionality as VFP but are not opcode-compatible with it.

ARM licensees
ARM Ltd does not manufacture and sell CPU devices based on their own designs, but rather, licenses the processor architecture to interested parties. ARM offers a variety of licensing terms, varying in cost and deliverables. To all licensees, ARM provides an integratable hardware description of the ARM core, as well as complete software development toolset (compiler, debugger, SDK), and the right to sell manufactured silicon containing the ARM CPU. Fabless licensees, who wish to integrate an ARM core into their own chip design, are usually only interested in acquiring a ready-to-manufacture verified IP core. For these customers, ARM delivers a gate netlist description of the chosen ARM core, along with an abstracted simulation model and test programs to aid design integration and verification. More ambitious customers, including integrated device manufacturers (IDM) and foundry operators, choose to acquire the processor IP in synthesizable RTL (Verilog) form. With the synthesizable RTL, the customer has the ability to perform architectural level optimizations and extensions. This allows the designer to achieve exotic design goals not otherwise possible with an unmodified netlist (high clock speed, very low power consumption, instruction set extensions, etc.). While ARM does not grant the licensee the right to resell the ARM architecture itself, licensees may freely sell manufactured product (chip devices, evaluation boards, complete systems, etc.). Merchant foundries can be a special case; not only are they allowed to sell finished silicon containing ARM cores, they generally hold the right to remanufacture ARM cores for other customers. Like most IP vendors, ARM prices its IP based on perceived value. In architectural terms, the lower performance ARM cores command a lower license cost than the higher performance cores. In terms of silicon implementation, a synthesizable core is more

Security Extensions (TrustZone)
The Security Extensions, marketed as TrustZone Technology, is found in ARMv6KZ and later application profile architectures. It provides a low cost alternative to adding an additional dedicated security core to a SoC, by providing two virtual processors backed by hardware based access control. This enables the application core to switch between two states, referred to as worlds (to reduce confusion with other names for capability domains), in a manner such that information can be prevented from leaking from the more trusted world to the less trusted world. This world switch is generally orthogonal to all other capabilities of the processor and so each world can operate independently of the other while using the same core. Memory and peripherals are then made aware of the operating world of the core and may use this to provide access control to secrets and code on the device. Typical applications of TrustZone Technology are to run a rich operating system in the less trusted world, and smaller security-specialized code in the more trusted world (known as TrustZone Software, a TrustZone optimized version of the Trusted Foundations(TM) Software developed by Trusted Logic), allowing much tighter Digital Rights Management for

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expensive than a hard macro (blackbox) core. Complicating price matters, a merchant foundry who holds an ARM license (such as Samsung and Fujitsu) can offer reduced licensing costs to its fab customers. In exchange for acquiring the ARM core through the foundry’s in-house design services, the customer can reduce or eliminate payment of ARM’s upfront license fee. Compared to dedicated semiconductor foundries (such as TSMC and UMC) without in-house design services, Fujitsu/Samsung charge 2 to 3 times more per manufactured wafer. For low to mid volume applications, a design service foundry offers lower overall pricing (through subsidization of the license fee). For high volume mass produced parts, the long term cost reduction achievable through lower wafer pricing reduces the impact of ARM’s NRE (Non-Recurring Engineering) costs, making the dedicated foundry a better choice. Many semiconductor or IC design firms hold ARM licenses; Analog Devices, Atmel, Broadcom, Cirrus Logic, Energy Micro, Faraday technology, Freescale, Fujitsu, Intel (through its settlement with Digital Equipment Corporation), IBM, Infineon Technologies, Nintendo, NXP Semiconductors, OKI, Qualcomm, Samsung, Sharp, STMicroelectronics, Texas Instruments and VLSI are some of the many companies who have licensed the ARM in one form or another. Although ARM’s license terms are covered by NDA, within the IP industry, ARM is widely known to be among the most expensive CPU cores. ARM believes that its base of 200+ semiconductor licensees gives it a chance to succeed in the ongoing controversies regarding the use of ARM or Intel architectures in mobile computers.

ARM architecture
processor licenses were signed,[33] an average of 1 million GBP (1.84 million USD) per license. Again, this is averaged across both new and old cores. Given that ARM’s 2006 income from processor cores was approximately 60% from royalties and 40% from licenses, ARM makes the equivalent of 0.06 GBP (0.11 USD) per unit shipped including both royalties and licenses. However, as one-off licenses are typically bought for new technologies, unit sales (and hence royalties) are dominated by more established products. Hence, these figures above do not reflect the true costs of any single ARM product.

References
[1] "ARMed for the living room" by Tom Krazit 2006; "Intel has ARM in its crosshairs" by Tom Krazit 2007. [2] "ARM Products and Solutions". Arm.com. http://www.arm.com/miscPDFs/3823.pdf. Retrieved on 2009-04-18. [3] "ARM Cores Climb Into 3G Territory" by Mark Hachman, 2002 [4] "The Two Percent Solution" by Jim Turley 2002 [5] "Actel: ARM" "The industry standard ARM® architecture is the most widely used 32-bit microprocessor architecture ever" [6] "Production PCB Combinational Tester" [7] "Some facts about the Acorn RISC Machine" Roger Wilson posting to comp.arch, Nov 2 1988, Accessed 25 May 2007. [8] Patterson, Jason. The Acorn Archimedes", The History Of Computers During My Lifetime - The 1980’s by (accessed 12 March 2008)] [9] "ARM Corporate Backgrounder", ARM Technology [10] "ARMed for the living room" by Tom Krazit 2006 [11] "ARM Achieves 10 Billion Processor Milestone", ARM Technology, 22 January 2008 [12] "ARM810 - Dancing to the Beat of a Different Drum" ARM Limited presentation at Hot Chips 8, 1996 [13] "Neo1973: GTA01Bv4 versus GTA02 comparison". http://wiki.openmoko.org/ wiki/ Neo1973:_GTA01Bv4_versus_GTA02_comparison. Retrieved on 2007-11-15.

Approximate licensing costs
ARM’s 2006 annual report and accounts state that royalties totalling 88.7 million GBP (164.1 million USD) were the result of licensees shipping 2.45 billion units.[31] This is equivalent to 0.036 GBP (0.067 USD) per unit shipped. However, this is averaged across all cores, including expensive new cores and inexpensive older cores. In the same year ARM’s licensing revenues for processor cores were 65.2 million GBP ($119.5 million),[32] in a year when 65

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ARM architecture

[14] "Rockbox Samsung SA58xxx series". [28] "ARM Information Center". http://www.rockbox.org/twiki/bin/view/ Infocenter.arm.com. Main/SamsungSA58. Retrieved on http://infocenter.arm.com/help/ 2008-02-22. index.jsp?topic=/com.arm.doc.ddi0290g/ [15] "Rockbox Meizu M6 Port - Hardware I1005458.html. Retrieved on Information". http://www.rockbox.org/ 2009-04-18. twiki/bin/view/Main/MeizuM6Port. [29] "Arm strengthens Java compilers: New Retrieved on 2008-02-22. 16-Bit Thumb-2EE Instructions Conserve [16] "STR9 - STR912 - STR912FW44 System Memory" by Tom R. Halfhill 2005 microcontroller - documents and files [30] "ARM Announces Availability of Mobile download page". Mcu.st.com. Consumer DRM Software Solutions http://mcu.st.com/mcu/ Based on ARM T". News.thomasnet.com. modules.php?name=mcu&file=devicedocs&DEV=STR912FW44&FAM=101. http://news.thomasnet.com/ Retrieved on 2009-04-18. companystory/476887. Retrieved on [17] Starlet 2009-04-18. [18] "Benchmarks - Albatross". Albatross[31] "Business review/Financial review/IFRS", uav.org. 2005-06-18. p. 10, ARM annual report and accounts, http://www.albatross-uav.org/index.php/ 2006. Retrieved May 7, 2007 Benchmarks. Retrieved on 2009-04-18. [32] Based on total 110.6 million GBP (202.5 [19] "ARM1136J(F)-S - ARM Processor". million USD) divided by "License Arm.com. http://www.arm.com/products/ revenues by product"; "Business review/ CPUs/ARM1136JF-S.html. Retrieved on Financial review/IFRS" and "Key 2009-04-18. performance indicators" respectively, p. [20] "GoForce 6100". Nvidia.com. 10 / p. 3 ARM annual report and http://www.nvidia.com/page/ accounts, 2006. Retrieved May 7, 2007 goforce_6100.html. Retrieved on [33] "Key performance indicators", p. 3, ARM 2009-04-18. annual report and accounts, 2006. [21] Segan, Sascha (2009-04-09). "ARM’s Retrieved May 7, 2007 Multicore Chips Aim for Netbooks News and Analysis by PC Magazine". Pcmag.com. http://www.pcmag.com/ • AMULET - a family of asynchronous ARMs article2/0,2817,2341032,00.asp. • Armulator, ARM Instruction Set Simulator Retrieved on 2009-04-18. • ARMware, a virtual machine that emulates [22] "ARM Extends Cortex Family with First an ARM-based PDA. Processor Optimized for FPGA", ARM • DirectBand press release, March 19 2007. Retrieved • Inferno April 11, 2007. • NXP/Philips LPC2000 ARM7TDMI-S [23] "ARM Cortex-M1", ARM product website. Microcontrollers Retrieved April 11, 2007. • SkyEye simulator - an open source ARM [24] ARM Extends Cortex Family with First Instruction Set Simulator Processor Optimized for FPGA • Texas Instruments OMAP - an ARM core [25] "ARM DSP Instruction Set Extensions". plus DSP and application acceleration Arm.com. http://www.arm.com/products/ cores CPUs/cpu-arch-DSP.html. Retrieved on 2009-04-18. [26] "ARM Processor Instruction Set Architecture". Arm.com. • ARM Ltd. http://www.arm.com/products/CPUs/ • ARM Documentation architecture.html. Retrieved on • ARM Assembler Programming; tutorial, 2009-04-18. resources, and examples [27] "ARM aims son of Thumb at uCs, ASSPs, • ARM architecture opcode map, for SoCs". Linuxdevices.com. ARMv4T and ARMv5TE http://www.linuxdevices.com/news/ • TrustZone(TM) Technology NS7814673959.html. Retrieved on

See also

External links

2009-04-18.

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From Wikipedia, the free encyclopedia
• ARM Microcontroller Development Resources - header files, schematics, CAD files, etc.. • Arm Architecture • ARM ISA Reference Manual

ARM architecture
• ARM Instruction Set Quick Reference Card • ARM and Thumb-2 Instruction Set Quick Reference Card • ARM Architecture Procedure Call Standard

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