specs - PDF

							                Audio Recorder Specifications
      VLSI Systems Design and CAD (VSDCAD) Laboratory,
      Dept. of Electrical Engineering and Computer Science,
                        Syracuse University,
                       Syracuse, NY - 13244.


1     Objectives
The Objectives of this project are as follows:
    • Learn how to synthesize from high-level specifications to layout a digital
      circuit using Cadence and/or Synopsys design tools.
    • Learn how to design analog and mixed-signal integrated circuits in CMOS
      deep fabrication process.
    • Learn how to integrate analog, mixed-signal and digital circuits in same
      silicon.
    • Learn how to design memory cores.
    • Evaluate the noise in mixed-signal integrated circuits.
    • Evaluate the power consumption in SoCs.


2     Introduction
This document describes the design specifications of a System-On-Chip (SoC)
that will be designed, implemented, fabricated and tested as a research project
in the VLSI Systems Design and CAD Laboratory at Syracuse University during
summer 2004. The SoC we intend fabricating is an audio recorder. The input
to our System-On-Chip will be an audio signal. This signal will be amplified,
filtered, and digitized. Then the digitized signal will be encoded using a stan-
dard encoding technique such as MP3. The encoded audio will be stored on an
SRAM. To reproduce the audio at the output, it will be decoded, converted to
an analog signal, and amplified.

    The general specifications will be as follows:
    • Audio Bandwidth: 0-3 Khz
    • Word size: 4-bit


                                        1
                                                       ROM


                                               Addr         Data



VDD

                                                      Control                    DAC &             Vout
Vin                Signal Conditioning
                                                      Unit                       Audio amplifier
                   & ADC
                                                      (Microcontroller)

                                                                                                   Record
GND_Digital

GND_Analog
                                                                                                   Play
                                                      Memory

CLK



Reset



                                     Test in                              Test out


                      Figure 1: Block Diagram: System Architecture



        • Memory size (RAM): TBD

        • Compression Algorithm: TBD

    Figure 1 shows the block diagram of the SoC. The basic blocks will be as
follows:

        • Analog Interface:

              – A-to-D Converter
              – D-to-A Converter
              – Audio Amplifier
              – Low-Pass Filter
              – Sample-and-Hold
        • Memory:

              – Cell array
              – Sense Amplifier
              – Decoder

        • Control Unit:


                                                      2
        – Micro-controller
        – Control Logic
    • Firmware:
        – Encoding Algorithm
        – Decoding Algorithm
        – Record and Play Functions


3     Team
 Member Name                   Contact Info          Task/Responsibility

 Benson                        tchiang@syr.edu       Cell Array/Decoder
 Dipti Sanghvi                 ddsanghv@syr.edu      Sample-and-Hold
 Jeff Lemay                     jmlemay@syr.edu       Audio Amplifier
 Jerille Lowe                  jerillel@yahoo.com    Firmware (Decoding Algorithm, Rec/Play Fns)
 Preetham Lakshmikanthan       plakshmi@syr.edu      A-to-D Converter
 Ravi Renganathan              rrengana@syr.edu      Low-Pass Filter
 Rima Mitra                    rmitra@syr.edu        Firmware (Encoding Algorithm)
 Sameer Wasson                 swasson@syr.edu       Control Unit
 Siddharth Mulchandani         ssmulcha@syr.edu      D-to-A Converter
 Shweta Shah                   srshah01@syr.edu      Sense Amplifier

4     Schedule
5     Design Alternatives
5.1    Fabrication Process
Now, we have three fabrication process that we can use:
    • AMI 0.5µm: This is a 5 Volt process technology
    • TSMC 0.25µm: This is a 2.5 Volt process technology
    • TSMC 0.18µm: This is a 1.8 Volt process technology
We will try to use the most advanced fabrication process. However we need to
make sure that we can have the following:
    • Cadence CMOS Library for the process technology chosen.
    • Cadence Design Rules.
    • Transistor Models (Spectre or Hspice).
    • We can fabricate Capacitors and Resistors. Needed for the analog circuits.


                                       3
   • We have I/O pads and the pad-frame for the final layout.

   Links to some process technologies & standard cell libraries are as follows :

   • MOSIS :
     http://www.mosis.org/products/fab/vendors
     http://www.mosis.org/Technical/Designsupport/artisan mep.html

   • OPEN SOURCE LINKS :
     http://www.vlsitechnology.org/html/libraries.html

   • UNIV. TENNESSEE (AMI0.6 Library) :
     http://vlsi1.engr.utk.edu/ece/bouldin courses/ut-lp-ami06.html

   • VIRGINIA TECH (TSMC-0.25 Library) :
     http://www.ee.vt.edu/˜ha/cell library/distribution.html

   • ILLINOIS INST. OF TECH (TSMC-0.25 & TSMC-0.18 Libraries) :
     http://www.ece.iit.edu/˜vlsi/scells

5.2    Packaging
We need to define the package that we are going to use. This will depend on
required I/O, the die size, and testing constraints.
    We also have decided to fabricate several chips. We will fabricate one chip
for each module of the SoC and one chip for the whole system.

5.3    I/O definition
      Name      Description        Width    I/O    Type      Pin Number
      VDD       Power Supply       3        -      -         -
      GND A     Analog Ground      3        -      -         -
      GND D     Digital Ground     3        -      -         -
      VIN       Audio In           1        In     Analog    -
      VOUT      Audio Out          1        Out    Analog    -
      CLK       Global Clock       1        In     Digital   -
      RST       Reset              1        In     Digital   -
      REC       Record Start       1        In     Digital   -
      PLAY      Play Start         1        In     Digital   -
      TI        Test inputs        10       In     Digital   -
      TO        Test out           10       Out    Digital   -




                                       4
5.4    Frequency of operation
5.5    Power Supply

6     Block Diagrams
6.1    Signal Conditioning and ADC
6.2    Control Unit
6.3    Memory
6.4    DAC and audio amplifier
6.5    ROM and Firmware

7     Floor-planning and Layout
8     Tools
9     Useful Links
    • Cadence Tutorials :

      http://www.icsl.ucla.edu/aagroup/ee115d/jeff/help/schematic.html
      http://www.ece.virginia.edu/˜mrs8n/cadence/Cadencetutorials.html
      http://turquoise.wpi.edu/cadence/
      http://www.ee.washington.edu/class/cadta/index.html

    • Analog Integrated Circuit Design :

      http://www2.elen.utah.edu/˜harrison/ee5720.html
      http://www.ee.siue.edu/˜cdsadmin/tutorials/cadence mixed-signal/ams tutorial.html
      http://www.ee.cooper.edu/ice/resources/cadtutor.htm#layout

    • PAD Frame :

      http://vlsi1.engr.utk.edu/ece/bouldin courses/smartframe.html
      http://www.ee.vt.edu/˜ha/cadtools/cadence/steps for chip submission.html

    • Circuit Archive :

      http://www.ee.washington.edu/circuit archive/circuits

    • Memories :

      http://turquoise.wpi.edu/aries/5.html#5.3



                                      5