Fiber optic transceivers, is a short distance from the twisted pair electrical signals and optical signals for long-distance exchange of Ethernet transmission media conversion unit, in many places is also known as Fiber Converter. Products are generally used in an Ethernet cable can not be covered, must be used to extend the transmission distance of optical fiber actual network environment, and usually located in the broadband MAN access layer applications; the same time helping the last-mile fiber optic lines connected to the city area network and more on the outer layer of the network also played a huge role.
A Dual-Mode Direct-Conversion CMOS Transceiver for Bluetooth and 802.11b Yeon-Jae Jung, Hoesam Jeong, Eunseok Song, Jungho Lee, Seung-Wook Lee*, Donghyeon Seo*, Inho Song*, Sanghun Jung*, Joonbae Park*, Deog-Kyoon Jeong, and Wonchan Kim Seoul National University, Seoul 151-742, Korea * GCT Semiconductor Inc., 2121 Ringwood Avenue San Jose CA 95131, USA Abstract DC-offset Cancellation A dual-mode direct-conversion transceiver integrates the transmitter of 0dBm output power and the receiver ~ ~ ~ PGA PGA for both Bluetooth with -87dBm sensitivity and 802.11b LNA Dual-mode PGAs with -86dBm sensitivity in a single chip with all building blocks shared for low cost and low power solution. ~ ~ PGA ~ PGA Fabricated in 0.25µm CMOS process, die size is 8.4mm2 Dual-mode Filter including pads and current consumption in RX is 50mA for Bluetooth and 65mA for 802.11b. ~ ~ Filter Tuning ~ PGA PA 1. Introduction ~ As the need for a short-range wireless personal PGA ~ ~ Serial Interface networking rapidly increases, numerous efforts has been Channel & Registers focused on implementing a low power, low cost, and POLY- DOU- PFD LOOP Setting highly integrated RF IC, especially in the areas of PHASE BLER VCO PRE- FILTER Reference CLK SCALER Bluetooth (BT) and 802.11b. Since both two standards are Clock GEN. targeted for the same 2.4GHz ISM band, a good deal of various building blocks of the two radios could be shared, Fig. 1. Dual-mode transceiver architecture in principle. Dual-mode transceivers [1-2], with the same motivation, have previously been proposed. However, mode programmable gain amplifier (PGA) in order to these exploited the partial commonality partly due to mitigate the low noise requirement of the succeeding filter different receiver architecture adoption in each mode. The stage. Rejection of out-of-channel interferers is done by an proposed transceiver implements the dual-mode capability active low-pass dual-mode filter, which is implemented by with a direct-conversion architecture for both modes and a Butterworth filter of 6th-order. Then, three cascaded both transmit/receive (TX/RX) operations. Thus, a little PGA stages provide sufficient gain to accommodate the area overhead is required since the transceiver can share signal range required by the A/D converters in the baseband blocks as well as RF stages. Furthermore, since baseband IC. DC-offset caused by various sources is the two standards differ considerably in their bandwidth removed by the DC-offset cancellation block coupled with and dynamic characteristics, the power consumption of the PGAs. dual-mode transceiver is optimized separately for each In TX path, the transmitter takes the analog I/Q inputs mode. from the baseband IC. The transmit spectrum shaping is The proposed dual-mode RF IC is a low power and low performed by the TX filter. The following PGA linearly cost solution, which works in stand-alone with each controls the amplitudes of the filtered I/Q signal in order commercial baseband chip and even does simultaneous to guarantee the TX mixer against the dynamic range loss. operation of Bluetooth and 802.11b with a dual-mode The TX baseband signal is directly up-converted to baseband chip. 2.4GHz by a single-sideband mixer and then, delivered to 50Ω load by the pre-amplifier (PA) with a nominal 2. Architecture power level of 0dBm and 18dB gain control, achieved by Fig. 1 shows the block diagram of the dual-mode the gain control in PGA and PA. transceiver. A direct-conversion architecture includes RF A 1.2GHz fractional-N frequency synthesizer is used receive and transmit sections, clock generation, filtering, for the generation of the LO signal at half the desired and linear amplification. frequency. Since the raster frequency is as small as In RX path, the single-ended low-noise amplifier first 20kHz, the industry standard reference crystal oscillators amplifies the received signal with high/low gain settings can be used. The fractional-N synthesizer offers low in- . Then, the amplified signal is directly down-converted band rms phase error due to wide loop bandwidth of to the baseband with 2.4GHz LO signals. The baseband 200kHz. The possible low frequency spur is suppressed signal is first amplified by a high-linear, low-noise dual- by using the charge-averaging charge pump scheme . The loop filter is also integrated in IC to minimize the coupling from the external noise sources. The Gilbert- cell type frequency doubler and 2nd-order active polyphase filter produces the 2.4GHz LO signals in order to minimize VCO pulling by PA and avoid possible interference by the RF signal. 3. Circuit Design 3.1. Pre-amplifier The pre-amplifier, shown in Fig. 1, is a single-ended CMFB circuit, blocking the use of an external element such as outb in inb out balun. The PA uses a cascode structure to assure the isolation from the PA output to its input, and to maintain the stability. The output of open-drain type needs an external RF choke as a load, that also provides the DC mode control current path. The nominal 0dBm output power is controlled in six steps of 3dB by changing the bias Fig. 2. Dual-mode PGA current of the cascode transistor through a bias control circuitry in PA and by the gain control in the baseband by the analog channel selection filter to nullify the PGA. dependence on the digital filtering, thus not to confine the An optional off-chip power amplifier further boosts the baseband chip to a specific one. A low pass filter of 6th- radio output to a maximum of 16dBm at antenna output. order Butterworth features both a maximally flat in-band magnitude response and good group delay response with a cutoff frequency of 700kHz in BT and 5.5MHz in 802.11b RFC mode, respectively. Among numerous filter structures Off-chip Matching including gmC and switched capacitor techniques, the Network active RC filter is chosen because it has the superior bias linearity performance. Fig. 3 shows the dual-mode filter implementation. The in 6th-order characteristic is achieved by cascading two 3rd - order filters with different filter Qs. The filter stages are Fig. 1. pre-amplifier arranged with low Q in front and high Q at the output to maximize the available dynamic range. The 3rd-order filter schematic is also shown in detail. The same opamp in 3.2. Programmable Gain Amplifier PGA is used to share similar benefits. The 3rd-order filter Fig. 2 shows the simplified schematic of the dual-mode is composed of a biquad and a passive pole – R4 and C3. PGA. Amplifier using switchable resistor array and While using simple multiple feedback topology, no stop- differential opamp exhibits excellent linearity performance. band zero is added to reduce the required opamp counts, Gain control is realized by switching the feedback thus to keep the current consumption low. The capacitor resistors and the resistors in the forward path to optimize C2 and C3 are split into a differential and a single-ended the noise and linearity characteristics at different gain part to save chip area and to also achieve common mode settings. A fully differential opamp features one-stage selectivity. amplification through a differential pair equipped with common-mode feedback and buffering through source 3rd-order 3rd-order follower stages. Low output impedance of source follower Butterworth Q=0.5412 Butterworth Q=1.3065 is extremely useful to drive the resistive load and to mitigate the high frequency roll-off possibly caused by ~ ~ ~ ~ large parasitic capacitance including the succeeding stage, ~ ~ which is in order to lower signal-to-noise ratio (SNR) degradation due to the flicker noise especially in narrow R2 bandwidth, BT application. C1 Since the bandwidth requirement is greatly differ for BT and 802.11b, the current in opamp is halved in BT mode R1 R3 R4 compared to 802.11b mode in order to reduce the overall inb out current consumption. This is achieved by switching the C2 C3 in outb current source in differential opamp according to each R1 R3 R4 mode. The total gain range of four PGA stages in baseband C1 chain is 60dB in 3dB steps. R2 3.3. Channel Selection Filter The rejection of out-of-channel interferers is done wholly Fig. 3. Dual-mode filter PGA BT 802.11b Gm (a) BT tuning[4:0] Fig. 5. DC-offset cancellation Cm/2 Cm/2 16Cu 8Cu Cu 4. Experimental Results The transceiver IC was fabricated in 0.25µm CMOS process. The die area is 2.9mm x 2.9mm including pads, (b) and the die micrograph is shown in Fig. 6. The IC is Fig. 4. (a) mode control using switchable resistors and packaged in a 40-pin QFN package with an exposed (b) mode control and frequency tuning bottom pad. Fig. 7 shows the receiver bit-error rate (BER) using switchable capacitor arrays and packet-error rate (PER) versus the input signal power for both BT and 802.11b modes. In BT, the minimum Fig. 4 shows the mode control for dual-mode support detectable signal (MDS) is -87dBm at 0.1% BER, which and the frequency tuning method. If only capacitor is 17dB better than the sensitivity required by the BT switching is used for the dual-mode control, the required standard. The sensitivity in 802.11b mode is -86dBm at capacitor area could be prohibitively large. Thus, the 8% PER and 11Mb/s data rate. This sensitivity level also resistor is allocated to each one for each mode as shown in exceeds the required MDS by 10dB. The measured filter Fig. 4(a) . Since the capacitor dominates the area, the response of the dual-mode filter is shown in Fig. 8. The switchable capacitor array is intended for the maximum discrepancy of the corner frequency from the target value sharing as in Fig. 4(b). The only non-shared capacitor is a is reduced within 3% due to the on-chip tuning loop. The capacitor of the value of Cm/2 for BT mode. Other unit measured I/Q imbalance, the difference in amplitudes and capacitor arrays controlled by tuning[4:0] signals, are phases of the two channels over the pass-band, is not more included to automatically tune the corner frequency of the than 0.3dB and 0.5o, respectively. Fig. 9 shows the filter against the process spreads and temperature transmitter output spectrum at 2.442 GHz. The output variations. The on-chip tuning circuit provides the power at nominal condition is about 0dBm for both modes. tuning[4:0] signals by measuring the RC time constant Applying 1Mb/s pseudorandom data with GFSK and comparing it with the fixed clock reference, in idle modulation, the BT output spectrum is shown in Fig. 9(a). time. Since the main capacitor in 802.11b mode is halved The 802.11b output spectrum with 11Mb/s data applied to compared to BT mode, the tuning[4:0] signals are right- its input is shown in Fig. 9(b). An adjacent channel power shifted by 1-bit and zero-padded in 802.11b case. rejection (ACPR) of better than 60dBc is achieved for both modes. 3.4. DC-offset Cancellation Table I summarizes the dual-mode transceiver IC Although there are several obstacles in a direct- performance characteristics. The receiver IIP3 with the conversion transceiver implementation, the DC-offset high gain setting at LNA is measured as -15dBm. The problem is the most serious one. While the AC coupling phase noise measured at PA output is typically 2 degrees. method may be regarded as an intuitive solution, it Final output DC-offset is less than 20mV with all gain requires the huge capacitor area and accompanies the settings in both BT and 802.11b modes. unavoidable in-band loss . The alternative one is to use the DC-coupled stage with a feedback configuration as depicted in Fig. 5. The Gm block proportionally converts the output offset voltage into the respective offset current RF RX RF RX RF TX RF TX fed into the MOS capacitor through a variable resistor. The integrated error voltage is subtracted from the input signal in the summer, which is embodied with an Doubler & Poly-phase Doubler & Poly-phase additional input pair in PGA. The DC-offset cancellation scheme is effective in that it does not incur any in-band loss and it is able to use the MOS capacitor which needs Filters Filters Frequency & & several times smaller area than the floating counterpart. PGAs PGAs Synthesizer Synthesizer The variable resistor is introduced to alter the corner frequency of the high pass filter characteristics, since this corner frequency is directly related with the SNR fc-tuning fc-tuning degradation and settling time. In BT mode, the corner is Serial Interface Serial Interface reduced to 1kHz for the minimal performance loss . On the contrary, in 802.11b mode, the corner is changed to ten times smaller one compared to the nominal 100kHz. Fig. 6. Die micrograph 802.11b BT (a) Fig. 7. Measured receiver sensitivity 802.11b (b) BT Fig. 9. Transmitter output spectrum with (a) Bluetooth data and (b) 802.11b data Table I Performance Summary Bluetooth 802.11b Fig. 8. Dual-mode filter response RX Current 50mA 65mA TX Current 45mA 60mA 5. Conclusion Sensitivity -87dBm -86dBm A highly integrated low power dual-mode transceiver in IIP3 -15dBm 0.25µm CMOS intended for use in Bluetooth and 802.11b TX Output Power 0dBm@nominal applications is reported. A direct-conversion architecture enables the maximum reuse and the optimal current Phase noise 2 deg RMS(10kHz – 10MHz) consumption of the various building blocks in each mode, Output DC-offset < 20mV thus low power and low cost solution with the minimal Supply Voltage 2.7V external components required. This CMOS transceiver Die Size 2.9mm x 2.9mm(including pads) with the dual-mode capability offers the extreme flexibility for the short-range wireless personal area Package 40 pin QFN network applications. References  H. Darabi, et al., “A dual mode 802.11b/Bluetooth  T. Hollman, S. Lindfors, M. Länsirinne, J. Jussila, and radio in 0.35µm CMOS,” ISSCC Digest of Technical K. A. I. Halonen, “A 2.7-V CMOS dual-mode Papers, pp. 86-87, Feb. 2003. baseband filter for PDC and WCDMA,” IEEE Journal  T. Cho, D. Kang, S. Dow, C.-H. Heng, and B. Song, of Solid-State Circuits, vol. 36, pp. 1148-1153, July “A 2.4GHz dual-mode 0.18µm CMOS transceiver for 2001. Bluetooth and 802.11b,” ISSCC Digest of Technical  R. Harjani, J. Kim, and J. Harvey, “DC-coupled IF Papers, pp. 88-89, Feb. 2003. stage design for a 900-MHz ISM receiver,” IEEE  K.-Y. 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