Duke ECE 163 Notes

Integrated Electronic Circuits Lecture Notes for ECE 163 Jeff H. Derby Dept. of Electrical and Computer Engineering Duke University ii Copyright © 2005, 2004, 2002 by Jeffrey H. Derby. All rights reserved. DRAFT 09:28 on 17 October 2006 iii Table of Contents 1 Review of Device Models ........................................................................ 1-1 1.1 Classification of Device Models ................................................................1-1 1.1.1 Linear, Nonlinear, and Incremental Models .......................................1-1 1.1.2 Static and Dynamic Models ...............................................................1-3 1.1.3 Notation ..............................................................................................1-4 1.1.4 An Example — The pn Diode ...........................................................1-4 1.1.5 A second example — the CMOS inverter .........................................1-9 1.2 MOS Transistor Models ..........................................................................1-11 1.2.1 Enhancement and Depletion Mode Devices ....................................1-12 1.2.2 Regions of Operation .......................................................................1-12 1.2.3 Nonlinear Model ..............................................................................1-13 1.2.4 Output Characteristics ......................................................................1-14 1.2.5 Second-Order Effects .......................................................................1-14 1.2.6 Incremental Model ...........................................................................1-16 1.3 Bipolar Transistor Models ......................................................................1-18 1.3.1 Nonlinear Model ..............................................................................1-18 1.3.2 Regions of Operation .......................................................................1-19 1.3.3 Simplified Nonlinear Model ............................................................1-20 1.3.4 Output Characteristics ......................................................................1-21 1.3.5 Second-Order Effects .......................................................................1-21 1.3.6 Piecewise Linear Model ...................................................................1-24 1.3.7 Incremental Model ...........................................................................1-25 2 Elementary Electronic Circuits ............................................................. 2-1 2.1 BJTs and MOSFETs as Two-Terminal Elements ...................................2-1 2.1.1 The “Diode-Connected” BJT .............................................................2-1 2.1.2 The “Diode-Connected” Enhancement-Mode MOSFET ..................2-5 2.1.3 The Depletion-Mode MOSFET as a Two-Terminal Element ............2-8 2.2 Simple Current Sources ............................................................................2-9 2.2.1 BJT Current Mirror ............................................................................2-9 2.2.2 MOS Current Mirror ........................................................................2-13 2.2.3 Additional Remarks .........................................................................2-15 2.3 Some Graphical Techniques ...................................................................2-16 2.3.1 Load Lines and Load Curves ...........................................................2-16 2.3.2 Transfer Characteristics ...................................................................2-18 2.4 MOS Inverters .........................................................................................2-20 2.4.1 MOS Inverter with Enhancement Load ...........................................2-20 2.4.2 MOS Inverter with Depletion Load .................................................2-22 2.4.3 CMOS Inverter .................................................................................2-25 2.5 The Differential Pair ...............................................................................2-28 2.5.1 BJT Differential Pair ........................................................................2-29 2.5.2 MOS Differential Pair ......................................................................2-32 2.5.3 A Practical Example ........................................................................2-34 3 Introduction to Amplifier Circuits ........................................................ 3-1 3.1 Some Amplifier Characteristics ...............................................................3-1 DRAFT 09:28 on 17 October 2006 iv 3.2 Biasing ........................................................................................................ 3-3 3.2.1 Discrete-Circuit Biasing .................................................................... 3-5 3.2.2 Integrated-Circuit Biasing ................................................................. 3-7 3.2.3 Additional Comments on Biasing ..................................................... 3-9 3.3 Classification and Modeling of Amplifiers ........................................... 3-10 3.3.1 Voltage Amplifiers ........................................................................... 3-10 3.3.2 Current Amplifier ............................................................................ 3-11 3.3.3 Transconductance Amplifier ........................................................... 3-12 3.3.4 Transresistance Amplifier ................................................................ 3-13 3.3.5 Amplifier Models Independent of Source and Load ....................... 3-13 3.3.6 Additional Comments ...................................................................... 3-15 3.4 Amplifier Bandwidth Considerations ................................................... 3-16 3.5 Amplifier Gains as Transfer Functions ................................................. 3-18 3.6 Device Capacitances and Bandwidth Limitations ................................ 3-21 3.6.1 BJT Capacitances ............................................................................ 3-21 3.6.2 MOSFET Capacitances ................................................................... 3-22 3.6.3 BJT Gain-Bandwidth Product ......................................................... 3-23 3.6.4 MOSFET Gain-Bandwidth Product ................................................ 3-25 4 Single-Stage Amplifier Circuits ............................................................. 4-1 4.1 The Common-Emitter Stage at Midband ............................................... 4-1 4.2 The Common-Emitter Stage with Active Load at Midband ................. 4-4 4.3 The Common-Source Stage at Midband ................................................. 4-8 4.4 The Common-Source Stage with Active Load at Midband ................. 4-10 4.5 The Common-Collector Stage at Midband ........................................... 4-12 4.6 The Common-Drain Stage at Midband ................................................. 4-15 4.7 The Degenerated Common-Emitter Stage at Midband ....................... 4-16 4.8 The Degenerated Common-Source Stage at Midband ........................ 4-19 4.9 The Common-Base and Common-Gate Stages at Midband ............... 4-21 4.10 The Differential Pair at Midband ........................................................ 4-23 4.10.1 The BJT Differential Pair with Resistive Load ............................. 4-24 4.10.2 The MOS Differential Pair with Resistive Load ........................... 4-29 4.10.3 The BJT Differential Pair with Active Load ................................. 4-31 4.10.4 The MOS Differential Pair with Active Load ............................... 4-39 4.10.5 Additional Remarks ....................................................................... 4-42 4.11 Analysis of Amplifier Stages at High Frequencies ............................. 4-42 4.12 The CE and CS Stages at High Frequencies ....................................... 4-42 4.12.1 Exact Analysis for the CE Stage ................................................... 4-42 4.12.2 Exact Analysis for a Common Source Stage ................................. 4-44 4.12.3 Miller’s Theorem ........................................................................... 4-45 4.12.4 The Miller Approximation for CE and CS Stages ......................... 4-45 4.13 The CC and CD Stages at High Frequencies ...................................... 4-47 5 Multistage Amplifiers ............................................................................. 5-1 5.1 Incremental Analysis of Multistage Amplifiers ...................................... 5-1 5.1.1 Midband Analysis .............................................................................. 5-1 DRAFT 09:28 on 17 October 2006 v 5.2 A Simple BJT Op Amp .............................................................................5-4 5.2.1 Biasing analysis .................................................................................5-5 5.2.2 Incremental analysis at midband ........................................................5-8 5.2.3 Incremental analysis at high frequencies .........................................5-10 6 Introduction to Feedback Amplifiers .................................................... 6-1 6.1 A Feedback System Model ........................................................................6-1 6.2 Effects of Feedback ....................................................................................6-2 6.2.1 Gain variability ..................................................................................6-2 6.2.2 Bandwidth ..........................................................................................6-3 6.3 Stability Considerations ............................................................................6-4 6.3.1 T(jw) and stability ..............................................................................6-4 6.4 Feedback Amplifier Configurations ........................................................6-7 6.5 Op Amps with Feedback ...........................................................................6-8 6.6 The Op Amp with Non-Inverting Mode Feedback ................................6-9 6.6.1 Closed-loop gain ..............................................................................6-10 6.6.2 Input resistance ................................................................................6-11 6.6.3 Output resistance ..............................................................................6-12 6.6.4 Summary ..........................................................................................6-13 6.7 The Op Amp with Inverting Mode Feedback .......................................6-14 6.7.1 Closed-loop gain ..............................................................................6-15 6.7.2 Input resistance ................................................................................6-16 6.7.3 Output resistance ..............................................................................6-18 6.7.4 Summary ..........................................................................................6-18 7 CMOS Gates ............................................................................................ 7-1 Structure of basic CMOS logic gates .......................................................7-1 A “Rule of Thumb” ...................................................................................7-2 A CMOS NOR gate ...................................................................................7-2 Noise Margins ............................................................................................7-3 Switching threshold of the CMOS NOR gate .........................................7-4 Switching Analysis of the CMOS Inverter ..............................................7-6 7.6.1 Input low-to-high transition ...............................................................7-7 7.6.2 Input high-to-low transition .............................................................7-10 7.7 Power Dissipation ....................................................................................7-13 7.8 A More General Switching Analysis ......................................................7-15 7.1 7.2 7.3 7.4 7.5 7.6 DRAFT 09:28 on 17 October 2006 vi DRAFT 09:28 on 17 October 2006 vii Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 1-5. Figure 1-6. Figure 1-7. Figure 1-8. Figure 1-9. Figure 1-10. Figure 1-11. Figure 1-12. Figure 1-13. Figure 1-14. Figure 1-15. Figure 1-16. Figure 1-17. Figure 1-18. Figure 1-19. Figure 1-20. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. Figure 2-9. Figure 2-10. Figure 2-11. Figure 2-12. Figure 2-13. Figure 2-14. Figure 2-15. Figure 2-16. Figure 2-17. Figure 2-18. Figure 2-19. Figure 2-20. Figure 2-21. Figure 2-22. Figure 2-23. Figure 2-24. A “black box” with one input and one output 1-1 An incremental model for a nonlinear system about an operating point 1-2 A pn-diode 1-4 Incremental model of a pn-diode 1-5 Piecewise-linear model of a pn-diode 1-6 A simple diode circuit 1-7 Use of the piecewise-linear diode model 1-7 A simple diode circuit with an ac voltage source 1-8 The incremental representation of a simple diode circuit 1-8 A CMOS inverter 1-9 Typical transfer characteristic for the CMOS inverter in Figure 1-10 1-11 Circuit symbols for MOS transistors 1-12 MOSFET common-source output characteristics 1-14 Common-source output characteristics of an NMOS transistor taking channel-length modulation into account 1-15 Static incremental model for a MOS transistor 1-17 Nonlinear hybrid-p circuit models 1-19 BJT common-emitter output characteristics 1-21 Variation of forward beta with collector current 1-22 Common-emitter output characteristics of an npn BJT taking base-width modulation into account 1-23 Static incremental hybrid-p model for a BJT 1-25 A “diode-connected” BJT 2-1 Nonlinear V-I characteristic of a diode-connected BJT 2-2 Incremental analysis of a diode-connected BJT 2-3 A “diode-connected” enhancement-mode NMOS transistor 2-6 Nonlinear V-I characteristic of an enhancement-mode NMOS transistor with gate and drain connected 2-7 Incremental analysis of a “diode-connected” enhancement-mode MOSFET. 2-7 A depletion-mode NMOS transistor connected as a two-terminal element 2-8 Nonlinear V-I characteristic of a depletion-mode NMOS transistor with gate and source connected 2-9 A simple BJT current mirror 2-10 Incremental analysis to find the output resistance of a BJT current mirror 2-12 The BJT current mirror as a current amplifier 2-13 A simple MOS current mirror 2-14 Incremental analysis to find the output resistance of the MOS current mirror 2-15 Example v-i characteristics for elements X and Y 2-16 A series connection of elements X and Y 2-17 The graphical solution 2-17 An NMOS transistor loaded by a resistor 2-18 Graphical solution for the MOS circuit 2-18 Transfer characteristic for the MOS circuit example 2-19 An NMOS inverter with enhancement load 2-21 Graphical description of the NMOS inverter with enhancement load 2-21 An NMOS inverter with depletion load 2-22 Graphical description of the NMOS inverter with depletion load 2-23 SPICE-generated transfer characteristic for the NMOS depletion-load inverter 2-25 DRAFT 09:28 on 17 October 2006 viii Figure 2-25. Figure 2-26. Figure 2-27. Figure 2-28. Figure 2-29. Figure 2-30. Figure 2-31. Figure 2-32. Figure 2-33. Figure 2-34. Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. Figure 3-7. Figure 3-8. Figure 3-9. Figure 3-10. Figure 3-11. Figure 3-12. Figure 3-13. Figure 3-14. Figure 3-15. Figure 3-16. Figure 3-17. Figure 3-18. Figure 3-19. Figure 3-20. Figure 3-21. Figure 3-22. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 4-8. Figure 4-9. Figure 4-10. Figure 4-11. Figure 4-12. Figure 4-13. Figure 4-14. Figure 4-15. Figure 4-16. Figure 4-17. A CMOS inverter 2-25 Obtaining solution points graphically for the CMOS inverter 2-26 Obtaining solution points graphically for the CMOS inverter 2-27 Transfer characteristic of the CMOS inverter 2-27 A generic differential pair 2-29 A BJT differential pair with resistive load and using npn transistors 2-29 Transfer characteristics of a BJT differential pair 2-31 An NMOS differential pair with resistive load 2-32 Transfer characteristics of a MOS differential pair 2-34 A practical MOS differential pair circuit with resistive load 2-35 A stylized representation of an amplifier 3-1 A simple circuit with the “stylized amplifier” of Figure 3-1 3-1 Biasing a BJT 3-3 “Constant-current” biasing of a BJT 3-5 A discrete common-emitter stage with practical biasing 3-5 DC equivalent circuit for the practical common-emitter stage in Figure 3-5 3-6 DC and AC load lines for the practical discrete common-emitter stage 3-7 Incremental model for the discrete common-emitter stage in Figure 3-5 3-7 A practical BJT differential pair circuit 3-8 The discrete common-emitter stage with a capacitively coupled load 3-10 Model of a voltage amplifier 3-11 Model of a current amplifier 3-11 Model of a transconductance amplifier 3-12 Model of a transresistance amplifier 3-13 Possible model of a voltage amplifier 3-14 Possible model of a current amplifier 3-15 Model of a voltage amplifier 3-16 Log-magnitude plot for a typical amplifier-gain characteristic 3-17 The dynamic incremental hybrid-pi model for a BJT 3-22 The dynamic incremental MOSFET model 3-23 Calculation of short-circuit common-emitter current gain for a BJT 3-23 Log magnitude of b versus frequency 3-24 A common-emitter stage and its incremental model at midband 4-1 Equivalent circuit at midband for the CE stage as a voltage amplifier 4-2 Finding the output resistance of the CE stage 4-2 Alternate midband equivalent circuit for the CE stage as a voltage amplifier 4-3 Common emitter stage with an active load 4-5 An “almost real” CE stage with active load 4-5 Model of a transconductance amplifier 4-7 Incremental model of the CE stage with active load 4-7 “Intrinsic” model for a transconductance amplifier 4-8 A common-source stage and its incremental model at midband 4-9 An “almost real” CS stage with active load 4-10 A common-collector stage and its incremental model at midband 4-12 Finding the output resistance of the CC stage 4-13 A common-drain stage and its incremental model at midband 4-15 A degenerated CE stage, and its incremental model at midband 4-16 Incremental model for the degenerated CE stage to find the short-circuit transconductance 4-17 Finding the output resistance of the CE stage with emitter resistance 4-18 DRAFT 09:28 on 17 October 2006 ix Figure 4-18. Figure 4-19. Figure 4-20. Figure 4-21. Figure 4-22. Figure 4-23. Figure 4-24. Figure 4-25. Figure 4-26. Figure 4-27. Figure 4-28. Figure 4-29. Figure 4-30. Figure 4-31. Figure 4-32. Figure 4-33. Figure 4-34. Figure 4-35. Figure 4-36. Figure 4-37. Figure 4-38. Figure 4-39. Figure 4-40. Figure 4-41. Figure 4-42. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 5-6. Figure 5-7. Figure 5-8. Figure 5-9. Figure 5-10. Figure 5-11. Figure 6-1. Figure 6-2. Figure 6-3. Figure 6-4. Figure 6-5. Figure 6-6. Figure 6-7. Figure 6-8. Figure 6-9. Figure 6-10. A degenerated CS stage, and its incremental model at midband 4-20 The common-base stage and its incremental model at midband 4-21 Equivalent circuit of a current amplifier 4-21 A common-gate stage and its incremental model 4-23 A BJT differential pair with resistive load 4-24 Incremental model for the BJT differential pair with resistive loads 4-25 “Half-circuit” equivalents for the BJT differential pair with resistive load 4-29 An MOS differential pair with resistive load 4-30 Incremental model of the MOS differential pair with resistive load 4-30 A BJT differential pair with active load 4-31 Incremental model for the BJT differential pair with active load 4-34 Incremental model for the BJT differential pair with active load 4-35 Transconductance model of the differential pair with active load 4-37 Circuit for Example 4.8 4-38 An MOS differential pair with active load 4-40 Incremental model of the MOS differential pair with active load. 4-40 Dynamic incremental model of a CE stage 4-42 Log magnitude of the voltage gain for a CE stage 4-44 Dynamic incremental model of a CS stage 4-44 The equivalence provided by Miller’s theorem 4-45 Application of Miller’s theorem to the base-collector capacitance 4-46 Incremental model at high frequencies of the CC stage in Figure 4-12 4-47 Incremental model at high frequencies of the CD stage in Figure 4-14 4-48 A generalized “follower” circuit model 4-48 Log magnitude of the gain of the CC stage 4-51 A three-stage amplifier 5-1 Analysis of the three-stage amplifier 5-2 A voltage-amplifier model 5-2 A CE-CC cascade 5-3 Incremental model of the CE-CC cascade 5-3 A stylized picture of an op amp 5-5 A simple BJT op amp 5-6 Norton and Thevenin models of the differential-pair stage 5-8 Incremental model at midband of the three-stage BJT op amp 5-9 Incremental model of the simple BJT op amp showing the capacitances associted with the CE stage 5-11 The circuit in Figure 5-10 transformed using the Miller approximation 5-11 Block diagram of a feedback system 6-1 Log magnitude and phase of the open-loop gain and loop gain for Example 6.2 6-7 The two basic op amp feedback configurations 6-8 Op amp model to be used for analysis of the feedback configurations 6-9 Incremental model of the op amp with non-inverting feedback 6-9 The circuit of Figure 6-5(b) with the feedback network replaced by a Thevenin equivalent circuit 6-10 Finding the input resistance of the op amp with non-inverting mode feedback 6-11 Output resistance of the op amp with noninverting feedback 6-12 An op amp with inverting mode feedback 6-14 Incremental model of the op amp with inverting mode feedback 6-14 DRAFT 09:28 on 17 October 2006 x Figure 6-11. Figure 6-12. Figure 6-13. Figure 7-1. Figure 7-2. Figure 7-3. Figure 7-4. Figure 7-5. Figure 7-7. Figure 7-6. Figure 7-8. Figure 7-9. Figure 7-10. Figure 7-11. The inverting-mode circuit of Figure 6-10(b) with a Norton equivalent of the feedback path 6-15 Finding the input resistance of the op amp with inverting mode feedback 6-16 Input resistance of the op amp with inverting mode feedback driven by a Norton equivalent source (a) and a Thevenin equivalent source (b) 6-17 Basic structure of a CMOS logic gate 7-1 A 2-input CMOS NOR gate and its truth table 7-2 Inverter transfer characteristic showing voltages that define the noise margin 7-4 A CMOS inverter with a load capacitance 7-7 A low-to-high transition of the inverter input voltage 7-7 A high-to-low transition at the inverter input 7-10 Inverter output voltage for Example 7.1 7-11 A generic CMOS logic gate with a load capacitance 7-14 A periodic output waveform 7-14 A linear equivalent circuit for approximate switching analysis of the CMOS inverter 7-15 A linear equivalent circuit for approximate switching analysis of the CMOS 2-input NOR gate 7-16 DRAFT 09:28 on 17 October 2006 1.1 Classification of Device Models 1-1 1 Review of Device Models In this chapter, we review the models we will be using for BJTs and MOSFETs. We begin by characterizing different classes of models, including: • linear, nonlinear, and incremental models • static and dynamic models We then summarize the static models for BJTs and MOSFETs, indicating how we will employ them for hand analysis. 1.1 Classification of Device Models Models for BJTs and MOS devices are often classified as being either large-signal or small-signal. These terms, while in common use, are imprecise. How large is “large”? How small is “small”? In what follows, we will define some terms that will be used to describe different classes of device models. Linear, Nonlinear, and Incremental Models We begin by considering a “black box” with an input x and output y, as shown in Figure 1-1. The output is some function of the input, i.e. y = f ( x ) . y = f (x) x Figure 1-1. 1.1.1 f() y A “black box” with one input and one output. The “black box” may be a BJT, with the input being base-emitter voltage and the output being collector current. It may be a very complex circuit with a large number of BJTs or MOS devices. It may be an interconnection of mechanical rather electrical components. Such a “black box” is generally referred to as a “system”. The relation y = f ( x ) describes the operation of the system and thus is in some sense “models” the operation of the system. A system is linear if the following conditions hold: 1. If the input is scaled by a constant a, the output is a times the output due to the unscaled input. That is: f ( ax ) = af ( x ) (1.1a) 2. If the input is the sum of two components, say x 1 and x 2 , the output is equal to the sum of the outputs due to each component individually. That is: f ( x1 + x2 ) = f ( x1 ) + f ( x2 ) (1.1b) A system that is not linear is nonlinear. A nonlinear system may be linear about some point x = X and y = Y . This will be the case if the two equations above are satisfied with x, x 1 , and x 2 replaced by f ( x – X ) , f ( x 1 – X ) , and f ( x 2 – X ) , respectively, and with Y = f ( X ) . DRAFT 09:28 on 17 October 2006 1-2 1 Review of Device Models A nonlinear system can be linearized about some point x = X and y = Y , with Y = f ( X ) . Consider theTaylor series expansion of f ( x ) about this point. With ∆x ≡ x – X , we have: df 1d f 2 - y = f ( X ) + ----( ∆x ) + -- ------( ∆x ) + … dx x = X 2 dx 2 x=X and keep in mind that Y = f ( X ) and that y – f ( X ) = y – Y = ∆y . If the contribution of the quadratic and higher power terms in ∆x is sufficiently small compared to that of the first term on the right hand side, we have the following “linearized model” of the system about the point x = X and y = Y , ∆y = A∆x (1.3) 2 (1.2) where A is the first derivative of f with respect to x evaluated at the point x = X and y = Y , and is thus a constant that depends on the values of X and Y. This equation is said to represent an incremental model of the system about the operating point x = X and y = Y . The operating point is also referred to as the quiescent condition (or Q-point) for the system. The model is called “incremental” because it relates an increment ∆y in the output y (from Y) to an increment ∆x in the input x (from X). It is easily seen that Equation (1.3) represents a linear input-output relationship, with ∆x as the input and ∆y as the output. An example is shown in Figure 1-2. y y = f(x) Y X Figure 1-2. tangent line to f(x) at the point ( X,Y) x An incremental model for a nonlinear system about an operating point. The incremental model is characterized by the tangent to the nonlinear system equation y = f ( x ) at the operating point x = X and y = Y . Before we proceed further, we note that the discussion so far is easily extended to systems with several inputs and several outputs. For example, we view BJTs as “systems” with two inputs and two outputs. The equations describing the operation of BJTs are such that the “inputs” (independent variables) are voltages and the “outputs” (dependent variables) are currents. Electronic devices are inherently nonlinear. A BJT is sometimes referred to as an exponential law device, because the current in each junction is related to the exponential of the voltage across thejunction. A MOSFET is sometimes called a square law device, because the drain current is related to the square of the gate-source or drain-source voltage. To accurately describe device operation for arbitrary terminal voltages and currents, the nonlinear device equations must be employed. These equations represent mathematical models for particular physical systems, namely semiconductor devices, and are therefore referred to as nonlinear models for the devices. In some cases, we can draw circuit models, using simpler nonlinear devices, that satisfy these same nonlinear relationships between terminal voltages and currents. The so-called nonlinear DRAFT 09:28 on 17 October 2006 1.1 Classification of Device Models 1-3 hybrid-π model for the BJT, shown in Figure 1-16 on page 1-19, is an example of such a nonlinear circuit model (or nonlinear equivalent circuit). However, it is important to keep in mind that for nonlinear models, the nonlinear equations (i.e., the mathematical model) represent the real nonlinear model; any equivalent nonlinear circuit model we can draw is just a convenience. Clearly, it is possible to linearize the nonlinear equations describing a BJT or MOSFET about some appropriate operating point. Following the discussion above, what results is an incremental model for the device about the operating point. This incremental model is a linear model that relates changes from the operating-point values of the outputs to changes from the operating-point values of the inputs. As noted above, the incremental model is an accurate representation of device operation for changes from the operating-point input and output values only as long as these changes are sufficiently small. Also, because the incremental model is linear, it’s mathematical form is completely equivalent to a linear circuit model, which is also called the “incremental model”. We see immediately, then, that an incremental model is a small-signal model, and that we have at least some idea how to go about determining how small is “small”. By the same token we would say that a nonlinear model is a large-signal model. The term “incremental” may on occasion be applied to certain circuit properties of an incremental model. For example, the incremental resistance seen between two nodes in a circuit is the equivalent resistance seen between these nodes with all devices replaced by their incremental models at the circuit’s operating point. Finally, it is important to remember that obtaining the incremental model of a device at an operating point requires finding the operating point itself. The operating point is a solution point of the nonlinear equations for the device as connected with other circuit components. Thus, these nonlinear equations must be solved to find the operating point. While this can often be done for MOS devices without too much difficulty, it is often impossible for BJTs without a computer. However, an approximate solution for the operating point can be obtained using a piecewise linear model. This differs from the incremental model in that it is constructed so as to apply over a wide range of device voltages and currents. An example of a piecewise linear model is shown below in Figure 1-5 on page 1-6. As can be seen from the figure, a piecewise linear model may represent a fairly coarse approximation to the nonlinear device characteristic. However, such models are often useful in estimating device operating points, and also in obtaining approximate solutions to problems in which incremental models cannot be used. We will see examples of such problems later on. Static and Dynamic Models BJTs and MOS devices incorporate charge storage mechanisms. In BJTs, there is charge stored in the junction depletion regions; the injected minority carriers resulting from forward biased junctions also represents stored charge. In MOSFETs, the conductor-oxide-channel “sandwich” represents an explicit capacitance; in addition, there are a variety of parasitic charge storage elements associated with junction depletion regions (e.g., between the substrate and the source and drain contact regions), and with overlap of the gate oxide with the source and drain contact regions. The charge stored in any one of these BJT and MOSFET elements is a nonlinear function of device voltages and currents. Device models that do not take device charge stores into account are static models. They are typically valid for voltages and currents with frequencies up 10kHz or so, depending on the type of device and type of circuit. Device models that do take device charge stores into account are dynamic models. Even dynamic 1.1.2 DRAFT 09:28 on 17 October 2006 1-4 1 Review of Device Models models have upper frequency limits for which they are valid, because of approximations involved in modeling the real physical processes that take place in semiconductor devices. The incremental model that results from linearization of a static nonlinear model is a static incremental model. Similarly, the incremental model that results from from linearization of a dynamic nonlinear model is a dynamic incremental model. A static incremental model includes no capacitances associated with device charge stores. A dynamic incremental model does include such capacitances. These capacitances are incremental capacitances, which result from linearization of the nonlinear charge vs. voltage relationships for the charge stores, evaluated at the device operating point. 1.1.3 Notation In Eqn. (1.2), we find the following categories of quantities: 1. x and y, which may represent the terminal voltages and/or currents of a device; x and y may vary with time. 2. X and Y, which represent the values of x and y, respectively, at an operating point; when we consider an operating point, we take the values X and Y at the operating point to be fixed and not changing with time. 3. ∆x and ∆y , which represent changes of x and y from their operating point values; ∆x and ∆y may vary with time. For voltages and currents in a circuit containing electronic devices, we use a particular convention to distinguish between these categories. We describe it here for voltage, but it applies identically for current. • Lower-case v, upper-case subscript: This represents a “total” voltage, i.e. in the first category listed above. This voltage is generally a function of time. • Upper-case V, upper-case subscript: This represents the value of voltage at an operating point. • Lower-case v , lower-case subscript: This represents the incremental voltage, generally a function of time, about some operating point. The use of this notation, as well as the application of the modeling concepts outlined above, are indicated in the example that follows. An Example — The pn Diode Figure 1-3 shows the circuit symbol for a pn-diode. In this example we consider static nonlinear, incremental, and piecewise linear models for the diode. The voltage across the diode (from p-side to n-side) is shown in the figure as v D , and the current through the diode in the direction of this voltage is shown as i D . Following the convention defined above, v D and i D are “total” quantities; that is, they are quantities associated with the nonlinear diode model: iD = IS ( e qv D ⁄ ηkT 1.1.4 – 1) (1.4) vD p n iD Figure 1-3. A pn-diode. DRAFT 09:28 on 17 October 2006 1.1 Classification of Device Models 1-5 In Eqn. (1.4), I S is the scale current (sometimes called the reverse saturation current) of the diode, q is – 19 – 23 the magnitude of charge on an electron ( 1.602 × 10 C ), k is Boltzmann’s constant ( 1.381 × 10 J ⁄ °K ), T is absolute temperature (in °K ), and η is the so-called ideality factor of the diode (dependent on the junction material; η ≈ 2 for silicon). The quantity ( kT ⁄ q ) is sometimes called the volt equivalent of temperature, and is approximately 25mV at room temperature (295 °K ). We can consider an operating point at which the diode voltage is V D and the diode current is I D , with these quantities of course being related by Eqn. (1.4). Such an operating point could be established by by connecting a DC voltage source equal to V D or a DC current source equal to I D across the device. We construct an incremental model at this operating point by differentiating Eqn. (1.4): di D qv ⁄ ηkT q  --------- = ---------  I S e D  ηkT  dv D (1.5) To evaluate the derivative at the operating point as in Eqn. (1.2), we set v D = V D in Eqn. (1.5). Comparing the result with I D , we find di D --------dv D q = --------- ( I D + I S ) ηkT (1.6) vD = VD By definition, the incremental diode current i d and the incremental diode voltage v d , at the specified operating point ( V D, I D ) , satisfy vD = VD + vd iD = ID + id Now, following Eqns. (1.2) and (1.3), we can relate the incremental diode current i D to the incremental diode voltage v D at the specified operating point, as follows: id = gd vd with q g d = --------- ( I D + I S ) ηkT (1.7) It is clear from this relation that the incremental model represents the diode as a linear resistor with resistance 1 ⁄ g d , for sufficiently small changes from the operating point. This is shown in Figure 1-4. iD r = g d–1 vd id VD Figure 1-4. slope = g d ID vD Incremental model of a pn-diode. The incremental conductance gd is the slope of the tangent line at the operating point. DRAFT 09:28 on 17 October 2006 1-6 1 Review of Device Models Finally, note with respect to Eqn (1.7) that this model is most often employed when the diode is forward biased, so that I D » I S , for example as shown in Figure 1-4. Thus we generally neglect I S when computing gd . We can also construct a piecewise linear model of the diode, as shown in Figure 1-5. We do so based on the observation that the diode has two regions of operation: an off region, in which the diode current remains approximately zero; and an on region, in which the diode current increases exponentially with the diode voltage. That there is an apparent boundary between these two regions can be seen in the plot of the diode characteristic in Figure 1-4 (repeated on the left in Figure 1-5(a)). This voltage is called the cut-in voltage, usually denoted by V γ , and is equal to about 0.5V for a silicon diode at room temperature. In the piecewise linear model, as shown on the left in Figure 1-5(a), the diode characteristic is approximated in the on region by a straight line with steep slope and in the off region by a straight line whose slope is approximately zero. The model is constructed so that the lines intersect at v D = V ON and i D = 0 , with V ON perhaps 100mV above V γ . The parameters of the model, namely V ON and the resistances R f and R r , can be chosen so that the piecewise linear approximation is a reasonably good fit to the nonlinear diode characteristic. However, since the approximation is at best rather coarse, it is often sufficient to take R f = 0 and R r → ∞ , with V ON equal to about 0.6V for a silicon diode at room temperature. From an equivalent circuit perspective, each of the two line segments in the piecewise linear approximation in Figure 1-5(a) corresponds to a linear circuit model consisting of a resistor and a voltage source. The circuit model for the on region is shown in Figure 1-5(b) while that for the off region is shown in Figure 1-5(c). Note that both circuit models are valid at the intersection point of the two line segments, i.e. at the boundary between the on and off regions. Note also that this boundary, which is slightly fuzzy in the nonlinear model (i.e. “in the real world”), is defined very precisely in the piecewise linear approximation as follows: v D ≥ V ON v D ≤ V ON and and iD ≥ 0 ; iD ≤ 0 ; diode on diode off (1.8) iD iD slope = R f–1 (a) Vγ Rf vD iD Figure 1-5. vD slope = R r–1 VON (b) (c) Vγ Rr VON VON vD iD vD Piecewise-linear model of a pn-diode. The approximation is shown graphically in (a). The circuit model for the approximation in the on region is shown in (b), and the model for the approximation in the off region is shown in (c). DRAFT 09:28 on 17 October 2006 1.1 Classification of Device Models 1-7 vD VS = 5V RS = 1k iD Figure 1-6. A simple diode circuit. We can illustrate some of the concepts discussed above using the circuit shown in Figure 1-6. The diode – 14 in the figure has I S = 10 A and η = 1 . A reasonable piecewise linear approximation is found to have V ON = 0.6V , R f = 10Ω , and R r → ∞ . The only excitation in the circuit is the DC voltage source V S = 5V . We are to find the resulting DC diode voltage V D and current I D , and the incremental model for the diode at this operating point. We can write a simple loop equation for the circuit and then substitute in the nonlinear volt-ampere relationship for the diode from Eqn. (1.4). We would obtain VS = VD + IS RS ( e qv D ⁄ ηkT – 1) It turns out that this equation cannot be solved in closed form. We can use a computer to solve it iteratively, or to solve the circuit directly using SPICE (or the equivalent). We can, however, obtain an approximate solution by hand analysis using the piecewise linear model for the diode. The only problem now is that there are two possible circuits in Figure 1-5; which is the right one to use here? The technique we employ proceeds as follows: 1. Assume the diode is operating in a particular region. 2. Solve the circuit using the corresponding model for the diode. 3. Verify that the solution is consistent with all the operating conditions for the diode in the assumed region, i.e. as given in Eqn. (1.8). To see how this works, let’s assume that the diode in Figure 1-6 is off. The circuit is redrawn in Figure 1-7(a) with the diode replaced by the off model from Figure 1-5(c). Solving the circuit, we quickly see that, because R r → ∞ , I D = 0 and V D = V S = 5V . Clearly, V D > V ON , and the condition in Eqn. (1.8) for the diode to be off is violated. Consequently, our assumption that the diode is off must be wrong. So, let’s assume instead that the diode is on. Writing a loop equation, we find (a) Rr vD iD VON VS = 5V RS = 1k (b) Rf vD iD VON VS = 5V RS = 1k Figure 1-7. Use of the piecewise-linear diode model. . In (a), the diode is assumed to be off; in (b), the diode is assumed to be on. The original circuit is in Figure 1-6. DRAFT 09:28 on 17 October 2006 1-8 1 Review of Device Models vD VS vs Figure 1-8. A simple diode circuit with an ac voltage source. . RS iD V S – V ON I D = ---------------------- = 4.36mA ; RS + Rf V D = V ON + I D R f = 644mV This solution is consistent with the condition in Eqn. (1.8) for the diode to be on. Thus the solution is correct and the diode is indeed on. The solution found using the nonlinear model (for example, using SPICE) is I D = 4.33mA and V D = 670mV . The solution can also be obtained graphically, using techniques to be described in the next chapter. The incremental model for the diode is a conductance g d as in Eqn. (1.7). Using I D = 4.33mA in this equation, we find g d = 0.173A/V ; the corresponding resistance is r d = 1 ⁄ g d = 5.77Ω . Consider now the addition of an ac voltage source to the circuit of Figure 1-6, as shown in Figure 1-8. We will assume that the magnitude of the ac source is sufficiently small for the incremental model to be valid in finding the circuit’s response to this source. The linearization process summarized in Eqns. (1.2) and (1.3) implies that the circuit in Figure 1-8 can be represented in two different ways: 1. as a circuit with only constant excitations, whose solution represents what we have called the operating point (or quiescent conditions) and is found using the nonlinear model or the piecewise linear model for the device; 2. as a circuit with only “small” incremental excitations, whose solution is found with the device replaced by its incremental model. The total response of the circuit to all excitations is the sum (i.e. the superposition) of the responses found using these two representations. Representation (1) of the circuit in Figure 1-8 is in fact the circuit shown in Figure 1-6 that we have already solved. Representation (2) of the circuit is shown in Figure 1-9. With the incremental conductance of the diode given by Eqn. (1.7), we can easily solve this circuit: vd RS vs Figure 1-9. rd = gd–1 id The incremental representation of a simple diode circuit. . The DC source V S does not appear in this circuit because its incremental value is zero; a zero-valued voltage source is a short circuit. DRAFT 09:28 on 17 October 2006 1.1 Classification of Device Models 1-9 1 v d = v s  --------------------   1 + R S g d Continuing the example above, let’s take v s to be a sinusoid with a frequency of 1kHz and an amplitude 3 of 500mV; i.e. v s ( t ) = 0.5 sin 2π10 tV . Substituting the values from the example above: v d ( t ) = 0.576 sin 2π10 t mV and v D ( t ) = V D + v d ( t ) = 670mV + 0.576 sin 2π10 t mV A second example — the CMOS inverter The circuit shown in Figure 1-10 is a CMOS inverter. “CMOS” here refers to the use of a technology in which NMOS and PMOS transistors of approximately equal quality can be built. The circuit is commonly used as an “inverter” in the sense of logic inversion, as will be described shortly. Note first that the circuit consists of two MOS transistors, one NMOS (M1 in the figure) and one PMOS (M2 in the figure), along with a DC power supply voltage (shown as 5V in the figure) and an input voltage source v I that in applications of interest may take on values between 0V and 5V (the DC power supply voltage); there is also an output voltage v O that is taken from the connection of the drains of the two MOS transistors as shown. This circuit is perhaps the simplest useful circuit that can be built with at least one MOS transistor. The circuit is also the basis of logic gates (NAND, NOR, exclusive-OR, etc., in addition to inverters) used for combinatorial logic (e.g. binary adders, multipliers, etc), sequential logic (registers, counters, etc.), and static random-access memory circuits. The number of copies of the CMOS inverter and circuits derived from it that are in use today in microprocessors and other digital systems is so large as to be almost uncountable; a single high-performance processor chip today may contain 106 to 107 logic-gate circuits derived from the CMOS inverter circuit. To consider the operation of the circuit as a logic inverter, it is necessary first to identify values of input and output voltage that will be associated with the binary logic values ‘0’ and ‘1’; we will take 0V to be logic ‘0’ (“low”) and the DC power supply voltage (5V) to be a logic ‘1’ (“high”). Now, an ideal logic inverter has the property that its output is a logic ‘1’ when its input is a logic ‘0’ and its output is a logic ‘0’ when its input 1.1.5 3 3 vGS2 G vGD2 iD2 iD1 S M2 D 5V vGD1 vI G D vO M1 vGS1 S Figure 1-10. A CMOS inverter. DRAFT 09:28 on 17 October 2006 1-10 1 Review of Device Models is a logic ‘1’. It is actually possible to determine without writing lots of circuit equations and using full-blown nonlinear device models that the CMOS inverter in Figure 1-10 satisfies this property. We do, however, need some information regarding operation of the MOS transistors. Recall that an MOS transistor has several regions of operation, with the region in which it is operating determined by the gate-to-source voltage ( v GS ), the gate-to-drain voltage ( v GD ), and the device parameter V T (called the threshold voltage).1 Typically, V T may be in the range of 0.5V to 1V for an NMOS transistor and in the range of -0.5V to -1V for a PMOS transistor. Consider the CMOS inverter with its input voltage corresponding to a logic ‘0’, i.e. with v I = 0 . By writing a simple loop equation we find that v GS1 = v I , so for this input condition we have v GS1 = 0 . Since V T > 0 for the NMOS device in the circuit, we have that v GS1 < V T for the NMOS device with v I = 0 , and consequently, based on the first-order device model, the NMOS device is off and its drain current i D1 is zero. Writing a node equation at the connection of the drains of the two devices, we have i D2 = – i D1 , and so i D2 , the drain current of the PMOS transistor, is also zero. However, the gate-to-source voltage of the PMOS device ( v GS2 in the figure) is equal to -5V.2 While the the threshold voltage for the PMOS device is negative, we have that v GS2 is more negative than this threshold voltage, and so the PMOS device would tend to conduct current, except that it does not conduct current because its drain current is constrained by circuit conditions to be zero. One can determine from the first-order MOS device models that when an MOS transistor’s gate-to-source voltage is such that the device would tend to conduct (i.e. v GS more positive than V T for NMOS, or v GS more negative than V T for PMOS) but the device’s drain current is constrained by circuit conditions to be zero, then the device’s drain-to-source voltage must be zero. Thus, in the CMOS inverter with v I = 0 , the drain-to-source voltage of the PMOS device is zero, and so we must have that v O = 5 ; in other words, when the input voltage is a logic ‘0’, the output voltage is a logic ‘1’. Similarly, one can show with reasoning that follows what we’ve used above that when the input voltage is a logic ‘1’, i.e. v I = 5 , then v O = 0 and the output is a logic ‘0’. Hence we have that the circuit indeed behaves as a logic inverter. In the design and application of logic circuits, however, it is not sufficient to characterize the circuit’s behavior when each input is either a logic ‘0’ or a logic ‘1’. In the case of the CMOS inverter in Figure 1-10, for example, it is important to know how the circuit behaves when it makes a transition from one state to another, i.e. when v I is varied from 0 to 5V or from 5V to 0. There are actually two scenarios that must be considered: (a) slow variation of v I ; (b) almost instantaneous step-change of v I . The first of these is reasonably amenable to hand analysis using first-order static nonlinear models for the MOS transistors. The analysis (which we will do in Section 2.4) yields a transfer characteristic, which is a plot of v O versus v I (subject to the condition that v I changes slowly). A typical transfer characteristic for the CMOS inverter in Figure 1-10 is shown in Figure 1-11. It can be seen from the transfer characteristic in the figure that the output remains high (logic ‘1’) for v I as high as about 1.25V, that the output remains low (logic ‘0’) for v I as low as about 3.75V, and that there is a fairly sharp transition between the output being high and the output being low that occurs at v I = 2.5V (halfway between the logic ‘0’ voltage and the logic ‘1’ voltage). These are all desirable characteristics of a logic inverter. The second scenario that must be considered is an almost instantaneous step-change of v I . This scenario is particularly significant because it will provide information on the speed with which the inverter switches from one state to another, e.g. from the output being high (logic ‘1’) to the output being low (logic ‘0’) in response to a step change at the input from low to high (0V to 5V in the circuit in Figure 1-10). Exact analysis here involves the use of nonlinear dynamic models and so requires the solution of nonlinear differential equations; this is essentially impossible by hand and is quite difficult even with numerical methods on a 1. It may be helpful to refer to the material on MOS device models in Section 1.2 while reading the remainder of this section. 2. Write a loop equation involving vI and vGS2 in the circuit of Figure 1-10 to convince yourself that this is true. DRAFT 09:28 on 17 October 2006 1.2 MOS Transistor Models 1-11 vO (V) vI (V) Figure 1-11. Typical transfer characteristic for the CMOS inverter in Figure 1-10. computer. Fortunately, it is possible to make some rather coarse approximations that permit one to obtain by hand estimates of switching speed using simple linear differential equations (we will do this in Section 7.8). While the approximations are indeed coarse, the estimates obtained using them are extremely useful. There is one additional point that is worth making with respect to the CMOS inverter as part of this example. Referring again to the transfer characteristic in Figure 1-11, observe that in the region where there is the sharp transition between the two output states the characterisitic has a large negative slope. The center of the transition region is found to be at v I = v O = 2.5V . Consider small variations about this point as an operating point. We can construct an incremental analysis that provides a linear approximation for the behavior of the circuit at the operating point. With the operating point defined by V I = 2.5V and V O = 2.5V , with the total input voltage written as v I = V I + v i , and with the total output voltage written as v O = V O + v o , the linear approximation is (recall Eqns. (1.2) and (1.3)) v o = Av i , where A is the slope of the transfer characteristic at the specified operating point. For the transfer characteristic shown in Figure 1-11, the slope is A = – 39.8 . Thus the circuit provides voltage amplification for small-amplitude input voltages superimposed on the the DC operating-point voltage V I . Moreover, the amplification is negative because the slope is negative; e.g. if the 3 incremental input voltage is v i ( t ) = ( 1mV ) sin 2π10 t (a 1kHz sine wave with 1mV amplitude), then the 3 incremental output voltage would be v o ( t ) = ( – 39.8mV ) sin 2π10 t , which is equivalent to a 1kHz sine wave with an amplitude of 39.8mV that is 180° out of phase with the input sine wave. Because the amplification is negative, the circuit is considered an “inverting amplifier” with respect to its linear behavior about the specified operating point; so the circuit is an “inverter” with respect to both logic applications and linear applications. Finally, it should be noted that, while the incremental analysis above based on the circuit’s transfer characterisitc seems to work for the CMOS inverter, a fully general and more complete incremental analysis relies on replacing each device in the circuit with its incremental model and then applying linear circuit analysis techniques to the resulting linear equivalent circuit. This is the approach to incremental analysis that we will use throughout the course. 1.2 MOS Transistor Models In this section, we summarize the models for MOSFETs as they will be used in this course. We focus here on static models; dynamic models will be dealt with in a later chapter. Circuit symbols for MOS transistors are shown in Figure 1-12. All models used for MOSFETs have different forms in the different regions of operation. Therefore, we first review the characteristics of these regions as well as MOS device types. DRAFT 09:28 on 17 October 2006 1-12 1 Review of Device Models 1.2.1 Enhancement and Depletion Mode Devices An enhancement mode MOSFET is a device in which there is no conducting path between the source and drain contacts with the gate at zero bias ( v GS = 0 , assuming the source is connected to the substrate). Once v GS exceeds the threshold voltage V T , an inversion layer is created under the gate oxide that acts as a conducting channel between the source and drain electrodes. For an n-channel (NMOS) device, V T > 0 , and the inversion layer exists when the voltage between gate and channel is more positive than V T . For a p-channel (PMOS) device, V T < 0 , and the inversion layer exists when the voltage between gate and channel is more negative than V T . A depletion mode MOSFET is a device in which there is a conducting path between the source and drain contacts with the gate at zero bias. This channel can be made to conduct more heavily by forward biasing the gate (positive gate-to-channel voltage for n-channel, negative gate-to-channel voltage for p-channel). The channel can be depleted by reverse biasing the gate. If the reverse gate bias “exceeds” the threshold voltage V T (gate-to-channel voltage more negative than V T < 0 for n-channel, or more positive than V T > 0 for p-channel), then the channel is “pinched off”, with its conductivity reduced to zero. We will be concerned almost entirely with enhancement mode devices, both NMOS and PMOS. Note that the transistors in the CMOS inverter in Figure 1-10 are both enhancement mode devices. Referring to Figure 1-12, the gate-to-source voltage v GS is the voltage from the gate to the source-end of the channel, while the gate-to-drain voltage v GD is the voltage from the gate to the drain-end of the channel. In addition, we note the loop equation v DS = v DG + v GS = – v GD + v GS and the fact that the gate current i G is always zero for static operation, so that i S = – i D . 1.2.2 Regions of Operation The operating region for a MOS transistor is determined by how the voltage at each end of the channel compares with the threshold voltage V T . In cutoff, v GS < V T v GS > V T v GD < V T v GD > V T (NMOS) (PMOS) (1.9) In the ohmic region, sometimes referred to as “non-saturation”, iD G (a) D B G S iD D B iD G (c) D B S iD G (d) D B S (b) S Figure 1-12. Circuit symbols for MOS transistors. (a) NMOS enhancement mode; (b) PMOS enhancement mode; (c) NMOS depletion mode; (d) PMOS depletion mode. DRAFT 09:28 on 17 October 2006 1.2 MOS Transistor Models 1-13 v GS > V T v GS < V T In saturation, v GS > V T v GS < V T v GD > V T v GD < V T (NMOS) (PMOS) (1.10) v GD < V T v GD > V T (NMOS) (PMOS) (1.11) The boundary between cutoff and saturation is taken to be v GS = V T , with v GD satisfying the conditions of Eqns. (1.9) and (1.11). The boundary between saturation and the ohmic region is taken to be v GD = V T , with v GS satisfying the conditions of Eqns. (1.10) and (1.11). 1.2.3 Nonlinear Model In cutoff, iD = 0 In the ohmic region, v DS k'W i D = ±  --------  v GS – V T – -------- v DS  L  2  In saturation, 1 k'W 2 i D = ± --  -------- ( v GS – V T ) 2 L  (1.14) (1.13) (1.12) In Eqns. (1.13) and (1.14), the plus sign is used for an NMOS device, and the minus sign is taken for a PMOS device. In these equations, W and L are the width and length, respectively, of the channel. These are nominally equal to the width and length of the gate metal and oxide. The parameter k' is the product of the effective mobility in the channel and C ox , the oxide capacitance per unit area. The latter is given by ε ox C ox = -----t ox – 11 (1.15) where ε ox is the permittivity of the oxide dielectric ( 3.45 ×10 F/m , or perhaps mor usefully –2 –8 3.45 ×10 fF/µm , for silicon dioxide) and t ox is the oxide thickness (on the order of 10 m for a typical integrated device). Since there is a different model equation for each region, we must make an assumption about the operating region for a device in order to determine which model to use. Once we have a solution based on our assumption, we check that it is consistent by verifying that the appropriate conditions for the assumed region, as given in Section 1.2.2, are satisfied. If they are not, our assumption is incorrect. DRAFT 09:28 on 17 October 2006 1-14 1 Review of Device Models iD (a) vGD = VT –iD (b) vGD = VT vDS vGS < VT Figure 1-13. vGS > VT –vDS MOSFET common-source output characteristics. (a) NMOS; (b) PMOS. The dashed line in each plot, at vGD = VT, is the boundary between the ohmic region and saturation. 1.2.4 Output Characteristics Figure 1-13 shows common-source output characteristics for NMOS and PMOS transistors, based on the nonlinear model as outlined above. Note that in saturation, the drain current is shown independent of v DS for constant gate-to-source voltage. This is consistent with Eqn. (1.14). 1.2.5 Second-Order Effects There are several important second-order effects that must be considered for the MOS model. Gate Overlap 1.2.5.1 When fabrication of an MOS transistor is complete, the semiconductor regions whose function is to contact the source and drain ends of the channel wind up extending very slightly underneath the gate oxide. As a result, the gate slightly “overlaps” the source and drain. One consequence is that the channel dimensions (width and length) as fabricated are slightly reduced from their so-called “drawn” values. A more important consequence is that an overlap capacitance is created between gate and drain; this will be discussed when we consider dynamic MOSFET models. 1.2.5.2 Channel-Length Modulation When a MOS transistor just becomes saturated ( v GD = V T ), the channel is depleted just at the drain end. As the device becomes more heavily saturated (e.g. v GD increasing beyond V T for an NMOS transistor), the depletion region extends increasingly further back from the drain end towards the source end. This in turn causes the actual length of the channel to be reduced. An approximate model of this phenomenon, called channel-length modulation, is constructed by taking L L eff ≈ -----------------------1 + λ v DS (1.16) where L eff is the operating length of the channel to be used in Eqn. (1.14), L is the effective fabricated channel –1 length taking overlap into account, and λ is a device parameter with units of V . Using Eqn. (1.16) in Eqn. (1.14), the drain current in saturation becomes: DRAFT 09:28 on 17 October 2006 more negative vGS < VT increasing vGS > VT 1.2 MOS Transistor Models 1-15 1 k'W 2 i D = ± --  -------- ( v GS – V T ) ( 1 + λ v DS )  L  2 (1.17) Thus, channel-length modulation causes the magnitude of the drain current in saturation to increase with with v DS for constant gate-to-source voltage. This is shown in Figure 1-14. Comparison of this figure with Figure 1-13 indicates that channel-length modulation results in the MOSFET’s saturation output resistance being finite. Note also that the channel-length modulation parameter λ is approximately inversely proportional to the nominal channel length L. In this course, we will generally consider channel-length modulation only with respect to the output conductance of the device, as part of the device’s incremental model (see Section 1.2.6 below). 1.2.5.3 Body Effect The nonlinear model equations in Section 1.2.3 show the operation of the device to be controlled to a large extent by the gate-to-source voltage. In fact, more fundamental than v GS is the voltage between the gate and the substrate (or body), v GB . If the source and the substrate are shorted together, then v GS = v GB and the model we have above is valid as is. Otherwise, the body effect3 causes the threshold voltage V T to depend on the difference between these two voltages, i.e. on the voltage v BS between the body and the source. The threshold voltage V T increases as v BS becomes more negative (for n-channel) or more positive (for p-channel). For an NMOS transistor, the threshold voltage is given by: V T = V TO + γ ( – 2φ p – v BS – – 2φ p ) (1.18a) where V TO is the threshold voltage at v BS = 0 , φ p is the potential of the substrate (e.g. with respect to intrinsic silicon, and γ is the body-effect parameter given by: iD (a) (b) iD increasing vGS > VT vDS Figure 1-14. vDS –1/λ Common-source output characteristics of an NMOS transistor taking channel-length modulation into account. The characteristics shown in (a), when extended linearly backward from v GD = V T , will all tend to intersect the horizontal axis at about v DS = – 1 ⁄ λ as shown in (b). 3. This effect is sometimes referred to as the backgate effect. DRAFT 09:28 on 17 October 2006 1-16 1 Review of Device Models 2qN a ε s γ = --------------------C ox (1.18b) where q is the quantum of electronic charge, N a is the concentration of acceptor dopant atoms in the p-type substrate, ε s is the dielectric permittivity of silicon, and C ox is the gate capacitance per unit area. In most of the MOS circuits that we will study in this course, each MOS transistor’s source will be shown connected to its substrate, so that v BS = 0 and the body effect can be ignored. There are some circuits for which this connection is not practical (or possible) in real-world implementations. For these circuits we will discuss in at least qualitative terms the impact of body effect on circuit behavior. 1.2.5.4 Short-Channel Effects The analysis leading to the MOS model equations in Section 1.2.3 are based on the approximation that the channel is “very long”. In currently available submicron MOS technologies (in which the drawn channel length for the smallest MOS transistor is less than 1 micron), this approximation is not completely valid, and several so-called “short-channel effects” must be taken into account. These effects are beyond the scope of this course. 1.2.5.5 Temperature Effects Temperature dependencies in the MOSFET model include: • The parameter k' decreases with temperature, because of the corresponding decrease in effective mobil–m ity in the channel. This parameter is approximately proportional to T , where the value of m is between 1.5 and 2.0. • The threshold voltage V T decreases almost linearly with temperature, at a rate between 0.5mV and 4mV per degree depending on process parameters. 1.2.5.6 Processing Tolerances MOS device parameters are strongly dependent of device fabrication processes. However, excellent matching of parameter values and geometries (W and L) is possible for adjacent or nearby devices. We will see examples of many circuits that take advantage of this matching 1.2.5.7 Weak Inversion The model summarized above assumes that there is a well-defined boundary between the range of v GS for which no channel exists (no drain current possible) and the range of v GS for which the device is in strong inversion and Eqns. (1.13) and (1.14) hold. This well-defined boundary is the threshold voltage V T . In fact, there is an intermediate region in which the the device is in so-called weak inversion, and in which a different nonlinear model must be used to characterize the relationship between drain current and terminal voltages. We will not deal with operation in weak inversion in this course. 1.2.6 Incremental Model The MOSFET incremental model is derived by applying the power-series expansion as in Eqn. (1.2) to the nonlinear saturation-region model developed above. We will start with the model in Eqn. (1.17) taking explicitly into account channel-length modulation and also implicitly including body effect through the dependence of V T on the substrate-to-source voltage v BS . We thus have the drain current in saturation as a function of three variables, namely v GS , v DS , and v BS . The power-series expansion for i D must therefore involve parDRAFT 09:28 on 17 October 2006 1.2 MOS Transistor Models 1-17 tial derivatives. However, given that we will keep only those terms that are linear in the incremental voltages ∆v GS = v gs , ∆v DS = v ds , and ∆v BS = v bs , what we require remains relatively simple. With the DC operating point defined by the DC voltages V GS , V DS , and V BS and in addition by the DC drain current I D determined using the values of the DC voltages, we can write:  ∂i D  id = iD – ID =    ∂ v GS or equivalently: i d = g m v gs + g o v ds + g mb v bs (1.19b) op. pt  ∂i D  v gs +    ∂ v DS op. pt  ∂i D  v ds +    ∂ v BS v bs op. pt (1.19a) where the identification of the quantities g m , g o , and g mb with the partial derivatives in Eqn. (1.19a) evaluated at the operating point should be clear. Eqn. (1.19b) can be viewed as a node equation, with the incremental drain current i d expressed as the sum of three currents, each of which is the output current of a linear voltage-controlled current source. A circuit that satisfies this node equation is shown in Figure 1-15; this circuit thus represents the static incremental model for a MOS transistor. One apparent difference between the circuit in Figure 1-15 and the node equation (1.19b) is that the controlled source g o v ds has been replaced by a resistor r o ; however, with r o = 1 ⁄ g o , the resistor is equivalent to the controlled source (since the source current is controlled by the voltage across it, and thus the controlled current source is in fact simply a resistance). Differentiation of the drain current i D in Eqn. (1.17) with respect to v GS and v DS is relatively straightforward, and we find for g m and g o : k'W k'W g m = -------- V GS – V T ( 1 + λ V DS ) ≈ -------- V GS – V T L L λ k'W g o = --  -------- ( V GS – V T ) 2 ≈ λ I D 2 L  (1.20) Note that the conductance g o is the result of channel-length modulation. The quantity g mb in the third term in Eqn. (1.19b) is due to body effect. Evaluation of the derivative in Eqn. (1.19a) to find g mb is somewhat difficult. It can be shown using Eqns. (1.18a) and (1.18b) that: g mb = χg m with γ χ = -----------------------------------2 – 2φ p – V BS (1.21) G id vgs gmvgs S D gmbvbs ro vds vbs B Figure 1-15. Static incremental model for a MOS transistor. The models for n-channel and p-channel, enhancement mode and depletion mode, are all identical. DRAFT 09:28 on 17 October 2006 1-18 1 Review of Device Models for an NMOS transistor. Typically, the value of χ lies between 0.1 and 0.3. 1.3 Bipolar Transistor Models In this section, we summarize the models for bipolar transistors as they will be used in this course. As with the MOS transistoe, we focus here on static models; dynamic models will be dealt with in a later chapter. 1.3.1 Nonlinear Model We use the so-called nonlinear hybrid-π model. For npn BJTs, the model equations are: i CC = I S ( e qv BE ⁄ kT –e qv BC ⁄ kT ) (1.22) I S qvBE ⁄ kT i BE = ----- ( e – 1) ; βF i C = i CC – i BC ; For pnp BJTs, the model equations are: i CC = – I S ( e I S qvBC ⁄ kT i BC = ----- ( e – 1) βR i B = i BE + i BC qv EB ⁄ kT –e qv CB ⁄ kT ) (1.23) I S qvEB ⁄ kT i BE = ----- ( e – 1) ; βF i C = i CC + i BC ; I S qvCB ⁄ kT i BC = ----- ( e – 1) βR i B = – ( i BE + i BC ) For both npn and pnp devices, we also have the following node and loop equations: iC + iB + iE = 0 ; v CE = v BE – v BC (1.24) Corresponding nonlinear circuit models are shown in Figure 1-16. The circuit models in the figure satisfy the equations above, if we take the diode shown between base and emitter to have scale current equal to I S ⁄ β F and that shown between base and collector to have scale current equal to I S ⁄ β R . As noted earlier, the circuit model is artificial; it is the mathematical model, derived from the physics of the device, that is fundamental. Referring to the model equations above, the quantity I S is the scale current of the BJT. A fundamental property of this parameter is that it is proportional to the area of the base-emitter junction. For β F and β R we find iC β F = ---iB Additionally, αF β F = --------------- ; 1 – αF αR β R = --------------1 – αR (1.26) ; v BC = 0 iE β R = ---iB (1.25) v BE = 0 DRAFT 09:28 on 17 October 2006 1.3 Bipolar Transistor Models 1-19 C iC iBC B C vBC iCC (a) B iC iB iBE vBE iE E iB iE C C iC iBC B C vCB iCC (b) B iC iB iBE vEB iE E iB iE C Figure 1-16. Nonlinear hybrid-π circuit models. . (a) shows the npn model; (b) shows the pnp model. with iC α F = – ---iE ; v BC = 0 iE α R = – ---iC (1.27) v BE = 0 The model outlined in this section is a form of the so-called Ebers-Moll model for the BJT. It is usually referred to as the Gummel-Poon model.4 1.3.2 Regions of Operation For a BJT, each of the two junctions may be either forward or reverse biased. This gives rise to four regions of operation, as indicated in Table 1-1. In the table, “BEJ” refers to the base-emitter junction, while “BCJ” refers to the base-collector junction. Table 1-1 BJT Regions of Operation Region cutoff forward active BEJ bias reverse forward BCJ bias reverse reverse 4. For the nonlinear model as outlined here, the differences between the Ebers-Moll and Gummel-Poon models are in the underlying formulation of the model and in how certain second-order effects are taken into account. DRAFT 09:28 on 17 October 2006 1-20 1 Review of Device Models Table 1-1 BJT Regions of Operation Region reverse active saturation BEJ bias reverse forward BCJ bias forward forward Recall that a junction is considered to be forward biased if the measured voltage across it (from the p-side to the n-side) is greater than its cut-in voltage V γ ; it is considered to be reverse biased if this voltage is less than or equal to zero. In the region between 0 and V γ , the junction is essentially non-conducting, but the very small current that does flow is a forward current. In our work here we will take the boundary between forward and reverse bias to be at V γ . For a silicon integrated BJT at room temperature, V γ is about 0.5V for the base-emitter junction and about 0.4V for the base-collector junction. Operation of a BJT in saturation is analogous to operation of a MOS transistor in the ohmic region (“non-saturation”). Operation of a MOS transistor in saturation is analogous to operation of a BJT in the active region. This confusion of terminology is unfortunate but unavoidable. 1.3.3 Simplified Nonlinear Model Simplification of the nonlinear model is possible in certain regions of operation. Cutoff 1.3.3.1 In the cutoff region, both junctions are reverse biased. Since the current through a reverse biased pn-junction is essentially zero, it is reasonable to use iC = iB = iE = 0 in the cutoff region. 1.3.3.2 Forward Active (1.28) In the forward active region, the base-collector junction is reverse biased. We consider first the special case v BC = 0 . Substituting this condition into the model equations (1.22) and (1.23), we find that i BC = 0 and iC = IS ( e iC = –IS ( e qv BE ⁄ kT qv EB ⁄ kT – 1 ) ≈ IS e qv BE ⁄ kT qv EB ⁄ kT ( npn ) ( pnp ) (1.29) – 1 ) ≈ –IS e iC i B = ----βF In the more general case, with non-zero reverse voltage on the base-collector junction, we take the exponentials in v BC in Eqn. (1.22) and those in v CB in Eqn. (1.23) to be approximately zero. Following through with the algebra, we would find that Eqns. (1.29) remain good approximations. The forward active region is often referred to simply as the active region. DRAFT 09:28 on 17 October 2006 1.3 Bipolar Transistor Models 1-21 1.3.3.3 Reverse Active The reverse active region is in some sense the complement of the forward active region. We could follow the reasoning outlined above to construct approximations for the reverse active region that correspond to Eqns. (1.29). 1.3.3.4 Saturation In saturation, both junctions are conducting. Since none of the exponential terms in Eqns. (1.22) and (1.23) can be neglected, a simplified set of nonlinear equations cannot be constructed. We can, however, obtain from the model equations a fundamental condition that distinguishes operation in saturation from operation in the forward active region, namely iC i B > ------βF 1.3.3.5 A Final Note (1.30) With the simplified model, we actually have a different model for each region of operation. We’re thus confronted with the need to verify that the solution obtained using a particular model is consistent with operation in the corresponding region. We will see this again for the piecewise linear model in Section 1.3.6. The criteria for verifying solution consistency are the same for both the simplified nonlinear model and the piecewise linear model; they are given in Section Section 1.3.6 below. 1.3.4 Output Characteristics Figure 1-17 shows common-emitter output characteristics for npn and pnp BJTs, based on the nonlinear (a) iC –iC (b) vCE Figure 1-17. –vCE BJT common-emitter output characteristics. (a) npn; (b) pnp. Operation in the reverse active region is not shown. The dotted lines mark the boundary between the forward-active and saturation regions according to Eqn. (1.30). model as outlined above. Note that in the active region, the collector current is shown independent of v CE for constant base current. This is consistent with Eqns. (1.29). Second-Order Effects It is implicitly assumed in the equations above that the device parameters ( I S , β F , β R ) are constant for any given device. This is in fact not the case. 1.3.5 DRAFT 09:28 on 17 October 2006 more negative iB < 0 increasing iB > 0 1-22 1 Review of Device Models 1.3.5.1 Variation of beta with current The value of β F (equal to the ratio i C ⁄ i B at v BC = 0 ) varies with I C , the value of i C at which it is measured. The behavior is depicted in Figure 1-18. At low values of I C , β F is reduced because of recombination in the base-emitter depletion region. This is the effect that gives rise to the “ideality factor” η in the diode equation (1.4). Because this effect is handled in the BJT model through variation of β F , there is no need to introduce η into the BJT model. Finally, at very high currents, β F is reduced because of high-level injection and so-called “base push-out” effects. In this course, the variation of β F with collector current will be ignored. The value of β R (equal to the ratio i E ⁄ i B at v BE = 0 ) varies with I E , the value of i E at which it is measured. Because β R is generally small to begin with,this variation is not usually of interest. 1.3.5.2 Base-Width Modulation (“Early effect”) In the forward active region, the width of the base-collector junction depletion region varies with the reverse voltage applied to the junction. This in turn causes the width of the base itself to vary. Since I S and β F depend on base width, these parameters become functions of base-collector voltage. The functional relationship is characterized by an additional parameter, the so-called Early voltage V A . For base-collector voltage V BC :  V BC  I S = I SO  1 + ---------  VA    V BC  β F = β FO  1 + ---------  VA   (1.31) where I SO and β FO are the values of I S and β F , respectively, at V BC = 0 . By convention, V A is positive for both npn and pnp devices. Eqn. (1.31) indicates that both I S and β F increase with increasing reverse voltage on the base-collector junction. The major consequence of this behavior can be seen by considering Eqns. (1.29) in the light of Eqns. (1.31), namely that in the active-region collector current increases with V BC (and thus with V CE ) for constant base current or base-emitter voltage. This is shown in Figure 1-19. Comparison of this figure with βF (a) (b) log IC log IB IC (A) Figure 1-18. VBE (V) Variation of forward beta with collector current. In (b), log I C and log I B are plotted vs. V BE . The vertical distance between the curves in (b), indicated by the arrows, is log β F at the particular V BE . Peak forward beta for this device is 200. DRAFT 09:28 on 17 October 2006 1.3 Bipolar Transistor Models 1-23 (a) iC (b) iC vCE increasing iB > 0 –VA vCE Figure 1-19. Common-emitter output characteristics of an npn BJT taking base-width modulation into account. The characteristics shown in (a), when extended linearly backwards from V BC = 0 , will all tend to intersect the horizontal axis at about V CE = – V A as shown in (b). Figure 1-17 indicates that base-width modulation results in the BJT’s active-region output resistance being finite. Additionally, it can be seen that the effects of base-width modulation show a strong similarity to the effects of channel-length modulation discussed above in Section 1.2.5.2. In both cases, a first-order model that is an ideal current source must be modified to have a finite output conductance. In this course, we will generally consider base-width modulation only with respect to the output conductance of the device, as part of the device’s incremental model (see Section 1.3.7 below). 1.3.5.3 Ohmic Resistances There is an ohmic resistance between the contact to each of the three regions in a BJT (emitter, base, collector) and the place in the region where the “action” takes place (as modeled in the equations given above). These are denoted by r b , r e , and r c for base, emitter, and collector, respectively. In this course, we will take into account only the base resistance r b , and then only as part of the BJT incremental model (see Section 1.3.7 below). 1.3.5.4 Temperature Effects There are several temperature dependencies in the BJT model. These include: • I S increases with temperature. As a rule of thumb, for a silicon device I S approximately doubles for every 5°C increase in temperature. • The V BE required to maintain the collector current at a specific constant value decreases by about 2mV to 2.5mV per degree increase in temperature. The cutin voltage V γ for a pn-junction also displays this behavior. • β F increases with temperature. A typical temperature coefficient for β F for an integrated silicon BJT is about +7000 parts per million per degree C. DRAFT 09:28 on 17 October 2006 1-24 1 Review of Device Models 1.3.5.5 Processing Tolerances BJT device parameters such as I S and β F are strongly dependent on the device fabrication processes. Process variations lead to relatively large tolerances in the absolute values of these parameters. For example, values of β F can range from one-half to twice the nominal value across a population of supposedly identical devices, fabricated on different wafers. However, matching of device parameters such as I S and β F between adjacent or nearby devices on a die is possible within very tight tolerances, perhaps a few percent. We will see examples of many circuits that take advantage of this matching. 1.3.6 Piecewise Linear Model It is often impossible to use even the simplified nonlinear model of Section 1.3.3 without recourse to a computer. We do, however, have the following coarse but useful piecewise linear model, based on the nonlinear model and the fact that the forward voltage on a pn-junction remains approximately constant. There is a different model for each region of operation. Criteria for verifying solution consistency are given along with the models. 1.3.6.1 Cutoff As in the simplified nonlinear model: iC = iB = iE = 0 To verify operation in the cutoff region, we must have both junctions reverse biased. 1.3.6.2 Forward Active v BE = ( V BE ) active ; For silicon at room temperature, ( V BE ) active = 0.6V (npn); ( V BE ) active = – 0.6V (pnp) (1.34) (1.32) iC i B = ----βF (1.33) To verify operation in the forward active region, we must have forward base current ( i B > 0 for npn; i B < 0 for pnp), and the base-collector junction reverse biased. 1.3.6.3 Saturation Because both junctions are forward biased in saturation, thebase-emitter junction voltage is slightly higher in magnitude than in the active region. We have: v BE = ( V BE ) sat ; For silicon at room temperature, ( V BE ) sat = 0.7V (npn) ; ( V CE ) sat = 0.2V (npn) ; ( V BE ) sat = – 0.7 V (pnp) ( V CE ) sat = – 0.2 V (pnp) (1.36) v CE = ( V CE ) sat (1.35) DRAFT 09:28 on 17 October 2006 1.3 Bipolar Transistor Models 1-25 B ib vbe rb rπ vπ gmvπ E ro ic vce C Figure 1-20. Static incremental hybrid-π model for a BJT. The models for npn and pnp devices are identical. To verify operation in the saturation region, we must have forward base current ( i B > 0 for npn; i B < 0 for pnp), and the inequality in Eqn (1.30) satisfied. 1.3.6.4 Reverse Active A model analogous to that for the forward active region in Section 1.3.6.2 can be constructed for the reverse active region. 1.3.6.5 Boundary Conditions Boundaries between regions are taken as follows: • Between cutoff and forward active: iC = iB = iE = 0 v BE = V γ (npn) ; v EB = V γ (pnp) • Between forward active and saturation: v BE = ( V BE ) sat ; v CE = ( V CE ) sat + 0.1V ; iC i B = ----βF (1.38) (1.37) where the polarity of v CE is positive for npn and negative for pnp. 1.3.6.6 A Final Note It is important to keep in mind that the junction voltages in the piecewise linear model represent simple approximations useful for hand calculations. The 100mV differences between v BE in forward active and saturation and between v CE in saturation and at the boundary of forward active may appear insignificant, but they can be sometimes critical in establishing the limits of a design. Computer simulation is generally required to obtain precise answers. 1.3.7 Incremental Model The BJT incremental model is derived by applying the power series expansion as in Eqn. (1.2) to the nonlinear hybrid-π model in Eqns. (1.22) and (1.23), taking into account the appropriate second-order effects mentioned in Section 1.3.5. The resulting incremental hybrid-π static model is shown in Figure 1-20. The values of the circuit elements in the incremental model depend on device parameters and the operating point as follows: q IC g m = ---------- ; kT IC g o = ------ ; VA gm g π = ----βo (1.39) DRAFT 09:28 on 17 October 2006 1-26 1 Review of Device Models where di C β o ≡ ------di B ic ≈ --ib (1.40) v ce = 0 op. pt. Note that if β F is independent of collector current, then β F = β o . We will take this to be the case throughout this course. In terms of the resistances shown in the model in Figure 1-20, we have r π = 1 ⁄ g π and r o = 1 ⁄ g o . Finally, r b is a device parameter whose value must be specified independently. DRAFT 09:28 on 17 October 2006 2.1 BJTs and MOSFETs as Two-Terminal Elements 2-1 2 Elementary Electronic Circuits In this chapter, we will look at several circuits that have the following properties: • They are simple. • They are interesting; i.e., they are useful despite being simple, and are widely used in one form or another in integrated circuits. • They can be analyzed by hand using the nonlinear models developed in the last chapter, as well as using linearized approximations such as the incremental models. These circuits will serve as vehicles for demonstrating how the models developed in the last chapter, both nonlinear and linearized, are applied. 2.1 BJTs and MOSFETs as Two-Terminal Elements 2.1.1 The “Diode-Connected” BJT In bipolar IC technologies, we often find a BJT with its base and collector connected together, as shown in Figure 2-1. With this connection, the BJT becomes a two-terminal element, often referred to as a “diode-connected” BJT for reasons that will become evident shortly. iY iB iC vY Figure 2-1. A “diode-connected” BJT. We consider the operation of the device in Figure 2-1 by characterizing it as a two-terminal element. Starting from the nonlinear model for the BJT, we can develop a relation between the terminal current i Y and the terminal voltage v Y as shown in the figure. We first recall the Eqns. (1.22) associated with the nonlinear hybrid-π model for the npn. BJT: i CC = I S ( e qv BE ⁄ kT –e qv BC ⁄ kT ) I S qvBE ⁄ kT i BE = ----- ( e – 1) βF i C = i CC – i BC as well as the loop and node equations: iC + iB + iE = 0 I S qvBC ⁄ kT i BC = ----- ( e – 1) βR i B = i BE + i BC v CE = v BE – v BC DRAFT 09:28 on 17 October 2006 2-2 2 Elementary Electronic Circuits Clearly, for the BJT in Figure 2-1 we find v BC = 0 and v Y = v BE = v CE , and also i Y = i C + i B . Substituting these conditions in the BJT model equations, we have: iC = IS ( e or qv Y ⁄ kT 1 – 1) i Y = I S  1 + -----  ( e  β  F qv BE ⁄ kT – 1) ; I S qvBE ⁄ kT i B = ----- ( e – 1) βF (2.1a) (2.1b) Comparing Eqn. (2.1b) with Eqn. (1.4), it is evident that the two-terminal device in Figure 2-1 acts like a pn-diode with scale current equal to I S ( 1 + 1 ⁄ β F ) and ideality factor1 η equal to 1. The V-I characteristic in Eqn. (2.1b) has the familiar form shown in Figure 2-2. Now, having employed the nonlinear BJT model in a very straightforward fashion to obtain the quantitative description of the BJT diode’s operation given by Eqn. (2.1b), it is worthwhile to consider its operation from a qualitative perspective. In particular, we should ask the following question: In what regions can the device in Figure 2-1 be operating? To answer this question, we observe again that v BC = 0 , so that the base-collector junction is always reverse-biased. As a consequence, the device can never operate in the saturation or reverse-active regions. Since v Y = v BE , we can make the following statements: • For v Y less than the cutin voltage V γ , the BJT in Figure 2-1 is cutoff. • For v Y greater than the cutin voltage V γ , the BJT in Figure 2-1 is in the forward-active region. Additionally, it is evident from Eqns. (2.1b) that i B = i C ⁄ β F for all values of v Y = v BE . Let’s now investigate the incremental behavior of the diode-connected BJT about an operating point. In the circuit shown in Figure 2-3(a), the device is fed by a current source consisting of a DC component I X that establishes the circuit’s operating point and a component i x representing incremental changes from the quiescent DC value. These components are shown explicitly in the figure as two individual current sources coniY (mA) vY (V) Figure 2-2. Nonlinear V-I characteristic of a diode-connected BJT. 1. Recall that the effect giving rise to the “ideality factor” η in the diode equation (1.4) is incorporated in the BJT model by the decrease of β F with collector current as the collector current becomes very small. DRAFT 09:28 on 17 October 2006 2.1 BJTs and MOSFETs as Two-Terminal Elements 2-3 nected in parallel, and we will view them this way in the analysis that follows; the two current sources together as shown are of course equivalent to a single current source i X = I X + i x . To find the circuit’s quiescent condition, we first recall that, by definition, all incremental voltages and currents are zero at the operating point. Referring to the figure and setting i x = 0 , it is easy to see that I Y , the value of i Y at the operating point, is equal to I X . From Eqns. (2.1a) and (2.1b), we find the base and collector currents at the operating point to be IC = αF IX IX I B = --------------1 + βF (2.2) where we have used the fact that α F = β F ⁄ ( 1 + β F ) . We can find the base-emitter voltage at the operating point using any of these currents and the appropriate equation from Eqns. (2.1a) and (2.1b). From the equation for i C , with i C = I C and v BE = V BE = V Y at the operating point, we have  kT I C kT  I C V Y = V BE = ----- log  ---- + 1 ≈ ----- log ---q IS  IS  q (2.3) Now that we know the quiescent values of the device currents and voltages, we can construct the incremental model at the operating point. In Figure 2-3(b), we have replaced the BJT with its incremental model, added the short circuit between base and collector, and included the incremental component i x of the current source. We’ll recall from Eqn. (1.39) that the values of the model elements are related to the device parameters and quiescent conditions by: q IC g m = ---------- ; kT VA r o = ------ ; IC βo r π = ----gm Clearly the incremental terminal current i y is equal to i x . We can find the incremental terminal voltage v y by writing the following node equation: vy vy i x = ---- + g m v π + ---------------ro r b + rπ and the following voltage-divider relationship between v y and v π : iB iC iY vY IX ix rb B C iy gmvπ rπ vπ E (b) ro v y ix (a) Figure 2-3. Incremental analysis of a diode-connected BJT. The incremental model of the circuit in (a) is shown in (b). DRAFT 09:28 on 17 October 2006 2-4 2 Elementary Electronic Circuits  rπ  v π = v y  ---------------   r b + r π Combining these equations, we obtain 1 + gm rπ 1 ix ---- = -------------------- + ---rb + rπ vy ro which, with a little algebraic manipulation, can be shown to be equivalent to vy  rb + rπ  ---- =  --------------------  || r o ix  1 + g m r π (2.4b) (2.4a) A close examination of Eqn. (2.4b) will show that it represents the equivalent incremental resistance of the diode-connected BJT. Indeed, the incremental model of this device is a two-terminal linear network containing no internal independent voltage or current sources, as can be seen in Figure 2-3(b). Any such network can be represented by a single equivalent resistance. This resistance can be found by connecting a test source to the network and evaluating (or measuring) the response; if the test source is a current source, the response is the voltage developed across the network, and the equivalent resistance is the ratio of this voltage to the test current. In Figure 2-3, the current source i x acts as a test current, the resulting voltage is v y , and so the ratio v y ⁄ i x in Eqn. (2.4b) is in fact the equivalent incremental resistance of the BJT diode. As such, we would expect it to be equal to the inverse of the slope of the nonlinear terminal characteristic given by Eqn. (2.1b) and shown in Figure 2-2 at the operating point. However, the incremental model includes at least two effects, namely base-width modulation (reflected in r o ) and the ohmic base resistance r b , that are not included in the first-order nonlinear model in Eqn. (2.1b), and is therefore likely to provide the more accurate result. Example 2.1 The npn BJT in Figure 2-3 has I S = 10 A , β F = β o = 100 , V A = 100V , and r b = 100Ω . The DC component of the current source in the figure is I X = 1mA , and the incremental component is a 1kHz –5 3 sine wave with amplitude 10µA; that is, i x ( t ) = 10 sin 2π10 t A . We assume that at 1kHz the static device model is adequate, i.e. device capacitances are open circuits and can be ignored. Finally, we take kT ⁄ q to be 25mV at room temperature. From Eqns. (2.2) and (2.3), we find the device operating point: I C = 990.1µA ; I B = 9.9µA ; V BE = 691mV – 15 The elements of the device incremental model at this operating point are: g m = 39.6mA/V ; r π = 2525Ω ; r o = 101kΩ The equivalent incremental resistance, from Eqn. (2.4b), is vy ---- = 25.99Ω || 101kΩ = 25.98Ω ix DRAFT 09:28 on 17 October 2006 2.1 BJTs and MOSFETs as Two-Terminal Elements 2-5 so that v y ( t ) = 0.2598 sin 2π10 t mV The total terminal voltage v Y is the sum of the quiescent value V Y and this incremental component; that is v Y ( t ) = 691mV + 0.2598 sin 2π10 t mV As a final note, it is evident from this example that the impact of r o on the equivalent resistance is negligible. In fact, given that in general r π » r b , g m r π » 1 , and r o » r π , we find that the equivalent resistance is approximately 1 ⁄ g m , which is 25.25Ω in this example. From the discussion above of the circuit in Figure 2-3 and the associated specific example, we can review the steps in the incremental analysis: 1. Obtain the operating point for the circuit. Because any operating-point voltage or current has zero incremental value by definition (recall the linearization process resulting from the expansion in Eqn. (1.2)), the incremental component of each source in the circuit must be set to zero when solving for the operating point. For the circuit in Figure 2-3, this requires that i x be set to zero. 2. Construct the incremental model for the circuit at the operating point, using the appropriate operating-point quantities to find the values of circuit elements where necessary (e.g., for g m , r π , and r o in Figure 2-3(b), all of which depend on I C ). Because any incremental voltage or current, and thus any voltage or current in the incremental model of a circuit, has zero DC “operating-point value” by definition (recall Eqn. (1.3)), the DC “operating-point” component2 of each source in the circuit must be set to zero in the circuit’s incremental model. For the circuit in Figure 2-3, this requires that I X be set to zero. Because a zero-valued current source is an open circuit, the I X source is replaced by an open circuit in Figure 2-3(b). 3. Once the incremental circuit has been solved, the total voltage or current at any point in the original circuit can be found by adding the operating-point value to the incremental value, in accordance with the expansion about the operating point in Eqn. (1.2). This is how the total voltage v Y is obtained from V Y (equal to V BE ) and v y in Example 2.1 above. Finally, it is worth taking a moment to observe that the results obtained in this section for the nonlinear and incremental behavior of the diode-connected BJT are readily “portable”. Whenever a diode-connected BJT appears in a circuit, its terminal voltage and current will satisfy the nonlinear equation (2.1b). More importantly, for incremental analysis it can always be replaced in the circuit’s incremental model by a single equivalent resistance whose value is given by Eqn. (2.4b). We do not need to perform time and again the circuit analysis that led to this equation. We only need to find the device’s operating point. 2.1.2 The “Diode-Connected” Enhancement-Mode MOSFET Figure 2-4 shows an enhancement mode MOSFET with its gate and drain connected together. The resulting two-terminal element is analogous in many respects to the diode-connected BJT considered above, 3 3 2. In general, we tend to think of DC voltage and current sources in a circuit as being associated with establishing the circuit’s operating point. It is clearly possible, however, for an incremental source to have a value that does not change with time and is thus really a DC source. We need to remember this possibility, even though “DC” will usually mean “operating point”. DRAFT 09:28 on 17 October 2006 2-6 2 Elementary Electronic Circuits iY iG iD vY Figure 2-4. A “diode-connected” enhancement-mode NMOS transistor. and will be referred to here as a “diode-connected MOSFET”. As shown in the figure, we have the substrate connected to the source, so that we can ignore the body effect. We can develop a nonlinear model for the MOSFET connected as shown as a two-terminal element, just as we did for the BJT diode. In this case, we will begin by asking: In what regions can the MOSFET in Figure 2-4 be operating? We can answer this question by noting from the figure that v GD = 0 . Since V T > 0 for an enhancement mode NMOS device, the transistor in the figure always operates with v GD < V T . As a consequence, the device can never operate in the ohmic region. The nonlinear models for the NMOS device in the saturation and cutoff regions are, from Eqns. (1.9), (1.11), (1.12), and (1.14): 1 k'W 2 i D = --  -------- ( v GS – V T ) ;  L  2 iD = 0 ; v GS ≤ V T v GS ≥ V T (saturation) (cutoff) For the NMOS transistor connected as in the figure, we have v DS = v GS , and the terminal voltage v Y satisfies v Y = v DS . The static gate current i G for an MOS transistor is always zero, so the terminal current i Y satisfies i Y = i D . So, from these equations, the nonlinear model for the “diode-connected” enhancement mode NMOS transistor is 1 k'W 2 i Y = --  -------- ( v Y – V T ) ; 2 L  iY = 0 ; This V-I characteristic is shown in Figure 2-5. We now proceed to investigate the incremental behavior of the NMOS transistor as connected in Figure 2-4, about an operating point. We’ll use a somewhat more abstract approach here than we did for the BJT diode. Let’s assume that an operating point in saturation is somehow established for the MOSFET at V Y , 2 with V Y > V T and I Y = 0.5k' ( W ⁄ L ) ( V Y – V T ) . We will evaluate the incremental resistance of two-terminal device in Figure 2-4 at this operating point. We show the incremental model of the MOSFET, with gate and drain connected, in Figure 2-6. We have included in the figure an incremental test source i x that we will use to evaluate the equivalent incremental resistance R eq ; referring to the figure, we have by definition that R eq is equal to v y ⁄ i x . We’ll recall that the values of the model elements are related to the device parameters and quiescent conditions by: vY ≤ VT vY ≥ VT (2.5) DRAFT 09:28 on 17 October 2006 2.1 BJTs and MOSFETs as Two-Terminal Elements 2-7 iY VT Figure 2-5. vY Nonlinear V-I characteristic of an enhancement-mode NMOS transistor with gate and drain connected. k'W g m = -------- V GS – V T ; L Referring to the figure, we write the node equation vy i x = ---- + g m v gs ro Noting that v gs = v y and employing a little algebra, we find go = λ ID vy 1 R eq = ---- =  -----  || r o  g m ix Example 2.2 (2.6) The NMOS transistor in Figure 2-4 has V T = 1V , k' = 50µA/V , W = 16µm , L = 8µm , and –1 λ = 0.03V . An operating point for the device is established at V Y = 3V . We immediately find for the operating point that V Y = V GS = 3V iy ro vy Req ix 2 G D vgs gmvgs S,B Figure 2-6. Incremental analysis of a “diode-connected” enhancement-mode MOSFET. The body-effect transconductance g mb has been left out because v bs = 0 . DRAFT 09:28 on 17 October 2006 2-8 2 Elementary Electronic Circuits Clearly, V GS > V T , so the device is in saturation. Using the appropriate equation from (2.5), we find 50 16 2 I Y = I D =  -----  ----- ( 3 – 1 ) = 200µA  2  8  The elements of the device incremental model at this operating point are: g m = 200µA/V ; The equivalent incremental resistance, from Eqn. (2.6), is R eq = 5kΩ || 166.7kΩ = 4.85kΩ We will note that, as was the case for the diode-connected BJT, the impact of r o on the equivalent resistance is very small. With g m » g o as in this example, the equivalent resistance is approximately 1 ⁄ g m . Finally, it is worth noting that we used the nominal channel length in the nonlinear model to relate I D and V GS , ignoring channel-length modulation. We then incorporated the effects of channel-length modulation in the incremental model, where it is represented by r o . This is typical of the approach we will use throughout for hand analysis. To obtain more detailed and precise results, we will resort to computer analysis. 2.1.3 The Depletion-Mode MOSFET as a Two-Terminal Element The most common connection of a depletion-mode MOSFET as a two-terminal element is shown in Figure 2-7. We will consider this connection for positive values of the terminal voltage v Y , for the NMOS device in the figure. Additionally, we again have the substrate connected to the source, so that the body effect will be ignored, and as usual we have i G = 0 . The connection in the figure is such that v GS = 0 . Since the transistor in the figure is an NMOS depletion-mode device, its threshold voltage is negative. Thus we have v GS > V T , so that the device can never be cutoff. The nonlinear model for the two-terminal element in the figure can be found by substituting v GS = 0 in the appropriate equations in Section 1.2.3. We also take into account that i Y = i D and v Y = v DS = – v GD . We have: r o = 166.7kΩ iY iD vY iG Figure 2-7. A depletion-mode NMOS transistor connected as a two-terminal element. DRAFT 09:28 on 17 October 2006 2.2 Simple Current Sources 2-9 iY –VT Figure 2-8. vY Nonlinear V-I characteristic of a depletion-mode NMOS transistor with gate and source connected. vY k'W i Y =  --------  – V T – ----  v Y ;  L  2 1 k'W 2 i Y = --  -------- ( – V T ) ; 2 L  vY ≤ –VT vY ≥ –VT (ohmic) (2.7) (saturation) A graphical representation of this V-I characteristic can be found from the the MOSFET output characteristics, as exemplified in Figure 1-13. For a depletion-mode MOSFET, one of the characteristics (i.e. a curve associated with a constant value of v GS ) would be associated with the value v GS = 0 . This curve is shown in Figure 2-8. We’ll note that when the device in Figure 2-7 is in saturation, it acts as a DC constant current source (with channel-length modulation neglected), with the output current dependent only on the device parameters. This behavior is completely different from that of the enhancement-mode two-terminal connection in Figure 2-4. The finite output resistance of the two-terminal depletion device in saturation, which is due to channel-length modulation, can be estimated by constructing an incremental model. Assume an operating point in 2 saturation with V Y ≥ – V T , so that, from Eqn. (2.7), I Y = 0.5k' ( W ⁄ L )V T . It should be evident that with v GS = 0 we must have v gs = 0 , so that the only element remaining in the incremental model is r o . 2.2 Simple Current Sources We now look at simple examples of a class of circuits variously called current mirrors or current repeaters. They employ the “diode-connected” devices we have already looked at, and they take advantage of the excellent device matching available with integrated circuit technologies. 2.2.1 BJT Current Mirror Figure 2-9 shows a simple BJT current mirror. We will assume that the transistors Q1 and Q2 are perfectly matched, i.e. their device parameters are identical. We see from the figure that v BE1 = v BE2 = v BE ; this is fundamental to the operation of the circuit. DRAFT 09:28 on 17 October 2006 2-10 2 Elementary Electronic Circuits +VCC1 iR +VCC2 RL R Q1 Q2 Figure 2-9. A simple BJT current mirror. Let’s consider the operation of the circuit using the simplified nonlinear model in Section 1.3.3, assuming that both BJTs are operating in the active region: i C1 = I S1 e qv BE1 ⁄ kT ; i C2 = I S2 e qv BE2 ⁄ kT ; i C1 i B1 = -------- ; β F1 i C2 i B2 = -------β F2 Because the devices are matched, we have I S1 = I S2 = I S and β F1 = β F2 = β F . Clearly, then, i C1 = i C2 and i B1 = i B2 . Writing a node equation at the junction of the two bases, we obtain 2 i R = i C1 + i B1 + i B2 = i C1  1 + -----   β  F (2.8) and also V CC1 – v BE i R = --------------------------R Example 2.3 The BJTs in Figure 2-9 have I S = 10 A , β F = β o = 100 , V A = 100V , and r b = 100Ω . In the circuit, V CC1 = 10V , V CC2 = 5V , and the load resistance is R L = 2.5kΩ . We are to find R such that the DC current I C2 flowing through the load resistance is 1mA. From Eqn. (2.8), I R = 1.02mA with I C1 = I C2 = 1mA . Taking ( kT ⁄ q ) = 25mV at room temperature, we find V BE1 = V BE2 = 691mV by inverting the exponential equation relating I C and V BE that is quoted above. Thus 10 – 0.691 R = ------------------------ = 9.13kΩ 0.00102 We should verify that Q2 is indeed in the active region. We have I B2 = 10µA > 0 , which is the correct polarity for an npn device. To check the bias on the base-collector junction, consider the loop equation V CC2 = I C2 R L + V CB2 + V BE2 – 15 DRAFT 09:28 on 17 October 2006 2.2 Simple Current Sources 2-11 from which we find that V BC2 , the forward voltage on the base-collector junction, is V BC2 = – V CB2 = – 1.809V < 0 The base-collector junction is indeed reverse biased, and operation in the active region is verified for Q2. Note that if the problem had been formulated differently, with R specified and the currents unknown, we would be unable to solve the circuit by hand using the exponential equation relating i C to v BE . In this case, we would use the piecewise linear model and take V BE1 = V BE2 = ( V BE ) active . If we start with R = 9.13kΩ , we would then find I C1 = I C2 = 1.01mA . It will be noted that in analyzing the current mirror circuit we once again neglected base-width modulation. In general, the transistors in the circuit of Figure 2-9 will operate with different values of V BC . If we use Eqn. (1.31) to account for base-width modulation, we would find  V BC2  I C2 = I C1  1 + ------------  VA   In the numerical example above, base-width modulation would cause the value of I C2 to be 1.8% higher than that of I C1 ; here the error due to ignoring base-width modulation is negligible. In some cases, however, the error may be significant. While computer analysis will provide precise results, it is always useful to remember that the output current of a BJT current mirror is affected by base-width modulation. Let’s continue our analysis of the circuit in Figure 2-9 by investigating its incremental behavior. We will view the circuit with respect to its output at the collector of Q2, with the output driving the load resistance R L , as shown in Figure 2-10(a). Since there are no independent incremental sources in the circuit, the incremental model of the circuit, shown in Figure 2-10(b), can be reduced to an equivalent output resistance R o seen looking into the output (between the collector of Q2 and ground). A test source i x has been added in Figure 2-10(b), to “measure” the output resistance. The load resistance R L is not included in the circuit in Figure 2-10(b), because we choose not to include it as part of the equivalent resistance to be evaluated. The incremental model of the circuit is redrawn in Figure 2-10(c) with that part of the circuit associated with the diode-connected BJT Q1 (see Figure 2-3(b)) enclosed in the shaded box. We already know from the analysis carried out in Section 2.1.1 that the subcircuit within the shaded box is completely equivalent to a resistance whose value is given in Eqn. (2.4b). In Figure 2-10(d), we have replaced the incremental model of Q1 by an equivalent resistance R eq1 , with  r b1 + r π1  R eq1 =  --------------------------  || r o1  1 + g m1 r π1 (2.9) It is clearly very useful to be able to take advantage of available results in this way. As it happens, it makes little difference in finding the output resistance of the circuit at hand. Writing circuit equations for the left-hand part of the circuit in Figure 2-10(d), we would find that all the voltages and currents there are zero; in particular, v π2 = 0 . It is then easy to show that vx R o ≡ ---- = r o2 ix (2.10) DRAFT 09:28 on 17 October 2006 2-12 2 Elementary Electronic Circuits (a) (b) +VCC1 R +VCC2 Ro RL rb1 R rπ1 B1 C1 B2 C2 gm1vπ1 vπ1 E1 rb2 ro1 rπ2 vπ2 gm2vπ2 ro2 vx ix Q1 Q2 E2 Ro (d) (c) rb1 R rπ1 vπ1 gm1vπ1 ro1 rb2 rπ2 vπ2 gm2vπ2 rb2 ro2 vx ix R Req1 rπ2 Ro vπ2 gm2vπ2 ro2 vx ix Ro Figure 2-10. Incremental analysis to find the output resistance of a BJT current mirror. Please observe that in constructing the incremental model in Figure 2-10(b) from the circuit in Figure 2-10(a), the DC voltage sources V CC1 and V CC2 have been replaced by short circuits. These voltage sources serve to establish the operating point for Q1 and Q2 and have zero incremental components. In fact, it should be evident from the notation that that they are pure DC “operating-point” quantities. They are therefore represented in the incremental model for the circuit by zero-valued voltage sources, i.e. by short circuits. As a result, the end of resistor R that is connected to V CC1 in Figure 2-10(a) is connected to ground in the incremental model. Example 2.3 (continued) Given the operating point and the device parameters, the output resistance is: VA R o = ------- = 100kΩ I C2 The incremental output resistance of the circuit in Figure 2-9 is an important quantity, because it is a key measure of how effectively the circuit behaves as a current source. An ideal current source has infinite output resistance. The higher the output resistance of a real current source, the closer its behavior to that of an ideal current source. There are in fact many variants of the circuit in Figure 2-9 in which additional devices are included in order to increase the output resistance beyond r o2 . It is also possible to view the circuit in Figure 2-9 as a current amplifier, with an incremental current source i i connected to the collector of Q1 as an input, as shown in Figure 2-11(a). The output current i o is the incremental current flowing through the load resistance R L and into the collector of Q2; i.e., it is the incremental collector current of Q2. The incremental model for the circuit is shown in Figure 2-11(b), with Q1 repre- DRAFT 09:28 on 17 October 2006 2.2 Simple Current Sources 2-13 +VCC1 R (a) +VCC2 io (b) io RL ii vi R Req1 rb2 rπ2 vπ2 gm2vπ2 ro2 RL ii Q1 Q2 Figure 2-11. The BJT current mirror as a current amplifier. sented by its equivalent resistance R eq1 as in Figure 2-10(d). We will define the incremental current amplification, or current gain, to be A I ≡ ( i o ⁄ i i ) . The following circuit equations can be written from Figure 2-11(b): v i = i i ( R || R eq1 || ( r b2 + r π2 ) ) ;  r π2  v π2 = v i  --------------------- ;  r b2 + r π2  r o2  i o = g m2 v π2  -------------------   r o2 + R L Defining R i ≡ R || R eq1 || ( r b2 + r π2 ) , we can obtain the following expression for the current gain: io g m2 r π2 r o2 R i A i = --- = ---------------------------------------------------ii ( r b2 + r π2 ) ( r o2 + R L ) Example 2.3 (continued) To evaluate A I , we need the complete set of incremental model parameters for each of the two BJTs. Because the BJTs are matched and have identical DC collector currents, the values of these parameters are identical as well. With I C1 = I C2 = 1mA , we have g m1 = g m2 = 40mA/V ; r π1 = r π2 = 2.5kΩ ; r o1 = r o2 = 100kΩ ; r b1 = r b2 = 100Ω (2.11) From Eqn. (2.9), R eq1 = 25.74Ω , and R i = 25.41Ω . Then, using Eqn. (2.11): A I = 0.954 The current gain here is slightly less than one and so is really attenuation rather than amplification. In fact, it is easily shown from Eqn. (2.11) that A I will always be less than one for the current mirror in Figure 2-11 with identical transistors. The significance of amplification in general and of values of “gain” that are less than one in particular will be discussed at length later on. For now, we have seen a non-trivial example of the use of incremental circuit analysis. MOS Current Mirror The simple current mirror circuit we have been studying can be built using enhancement-mode MOS transistors, as shown in Figure 2-12. We will assume that the transistors M1 and M2 are perfectly matched, i.e. their device parameters and geometries are identical. Fundamental to the operation of the circuit is the fact 2.2.2 DRAFT 09:28 on 17 October 2006 2-14 2 Elementary Electronic Circuits +VDD1 iR +VDD2 RL R M1 M2 Figure 2-12. A simple MOS current mirror. that v GS1 = v GS2 . Using the nonlinear saturation equation (1.14), and taking the device matching into account, it is easy to see that i D1 = i D2 . Furthermore, because the static gate current of a MOSFET is always zero, we also have i R = i D1 . Finally, i R = ( V DD1 – v GS1 ) ⁄ R . Example 2.4 The NMOS transistors in Figure 2-12 have V T = 1V , k' = 50µA/V , W = 16µm , L = 8µm , and –1 λ = 0.03V . In addition, V DD1 = V DD2 = 5V , R = 10kΩ , and the load resistance is R L = 12kΩ . We are to find the output current I D2 in the load resistance. Using the loop equation involving i R and substituting in the quadratic relationship between i D and v GS in saturation, we obtain 0.5 ( V GS1 – 1 ) = 5 – V GS1 The solution to this quadratic equation is V GS1 = ± 3V . We must choose one of the two possible solutions; the correct choice is the one that is consistent with our assumption that M1 is in saturation. Since we need V GS1 > V T , we must have V GS1 = V GS2 = 3V , so that I D1 = I D2 = 200µA . Finally, we’ll verify that M2 is also in saturation. We already know that V GS2 > V T . Now consider V DD2 = I D2 R L + V DG2 + V GS2 so that V GD2 = – V DG2 = 0.4V < V T Operation of M2 in saturation is thus verified. Of course, in the analysis above we neglected channel-length modulation. In general, the transistors in the current mirror circuit will operate with different values of : V DS . Channel-length modulation will tend to cause the drain currents I D1 and I D2 to differ. The difference can be estimated using Eqn. (1.16), or it can be evaluated more precisely using computer analysis. 2 2 DRAFT 09:28 on 17 October 2006 2.2 Simple Current Sources 2-15 (a) +VCC1 R +VCC2 Ro RL R G1,D1,G2 (b) D2 vgs1 gm1vgs1 S1,B1 ro1 vgs2 gm2vgs2 ro2 S2,B2 vx ix M1 M2 Ro (c) R Req1 vgs2 gm2vgs2 ro2 Ro vx ix Figure 2-13. Incremental analysis to find the output resistance of the MOS current mirror. The incremental analysis to find the equivalent output resistance of the MOS current mirror in Figure 2-13 follows the same steps as that for the BJT current mirror. Again, we will view the circuit with respect to its output at the drain of M2, with the output driving the load resistance R L , as shown in Figure 2-13(a). In Figure 2-13(b), we have replaced M1 and M2 with their incremental models and added the test source i x to “measure” the output resistance R o . In Figure 2-13(c), the model for diode-connected device M1 (inside the shaded box in Figure 2-13(b)) has been replaced by its net equivalent resistance R eq1 based on the analysis in Section 2.1.2, with 1 R eq1 =  --------  || r o1  g m1 As in the BJT circuit, however, all the voltages and currents in the left-hand side of the circuit are zero, so that in particular v gs2 = 0 . It is then easy to show that vx R o ≡ ---- = r o2 ix Example 2.4 (continued) Given the operating point and the device parameters, the output resistance is: 1 R o = r o2 = -------------- = 167kΩ λ I D2 2.2.3 Additional Remarks We noted with respect to the BJT current mirror that more complicated variants of the circuit have been designed that have higher incremental output resistance and are thus better current sources. The same is true for the MOS current mirror in Figure 2-12. (2.12) DRAFT 09:28 on 17 October 2006 2-16 2 Elementary Electronic Circuits A trivial modification to either the BJT mirror or the MOS mirror allows the output current flowing in the load to be scaled relative to the set-up current i R . Consider first the BJT circuit in Figure 2-9, and recall that the scale current I S of a BJT is proportional to the area of its base-emitter junction. If Q1 and Q2 in the figure are matched but with the area of the base-emitter junction of Q2 scaled by a factor of N relative to that of Q1, then i C2 = Ni C1 ≈ NI R so long as both devices remain in the active region. For MOS devices, the dependence of drain current on channel width and length is explicit in the model equations. If M1 and M2 in Figure 2-12 are matched but with the width of the channel of M2 scaled by a factor of N relative to that of M1, then i D2 = Ni D1 = Ni R so long as both devices remain in saturation. The scaling can be precisely controlled if the scale factor N is a rational number between, say, 0.1 and 10. We will see an important application of current mirrors shortly, in Section 2.5 on the differential pair. 2.3 Some Graphical Techniques At this point, we will consider some graphical analysis techniques that will assist us in understanding the operation of certain circuits that use semiconductor devices. We investigate: • Load lines and load curves • Transfer characteristics We will also look at the relationship between these techniques. 2.3.1 Load Lines and Load Curves Consider two two-terminal circuit elements: element X with v-i characteristic i X = f X ( v X ) ; and element Y with v-i characteristic i Y = f Y ( v Y ) . These elements may be linear or nonlinear. Their characteristics might be, for example, as shown in Figure 2-14. In Figure 2-15, these elements are connected in series with a iX (a) iY (b) fY(vY) fX(vX) vX vY Figure 2-14. Example v-i characteristics for elements X and Y. voltage source v S . For the circuit in this figure, we easily find that vS = vX + vY iS = iX = iY (2.13) For any value of the source v S , the device voltages and currents must satisfy these circuit equations and must also satisfy the individual device characteristics shown in Figure 2-14. We can use this fact to find the solution for the circuit graphically, by plotting both device characteristics on the same set of axes. We will arbi- DRAFT 09:28 on 17 October 2006 2.3 Some Graphical Techniques 2-17 iY Y vY iS vS iX X vX Figure 2-15. A series connection of elements X and Y. trarily choose v X and i X as our axes. We can plot the characteristic of element Y on these axes by substituting for v Y and i Y using Eqn. (2.13). Making this substitution, we have two equations relating i X and v X , namely iX = fX ( vX ) iX = fY ( vS – vX ) (2.14) These two equations are plotted individually in Figure 2-16(a) and Figure 2-16(b). You should verify for yourself how the plot in Figure 2-16(b) is obtained from that in Figure 2-14(b). Because they both involve the same pair of variables v X and i X , the two equations in (2.14) can both be plotted on the same set of axes, as shown in Figure 2-16(c). Because both equations in (2.14) must be satisfied in the circuit we are considering, the solution point for the circuit can only be at the point in Figure 2-16(c) at which the two curves intersect. If the characteristics of the two devices have been plotted carefully, we can find the solution point graphically in this way. It is evident from Figure 2-16 that if the value of v S varies, then the characteristic of device Y that is written in terms of s v X and i X moves horizontally when plotted on these axes. The graphical method described above becomes much more interesting and useful when device X is a three-terminal element, with the third terminal employed as a control input. In such cases, device X is often referred to as the driver device, and device Y is called the load device. The characteristic of the load device, when plotted on the axes associated with the driver, is the load curve. Consider as an example the circuit in Figure 2-17. In this circuit, the driver, i.e. device X, is an MOS transistor, and the load, i.e. device Y, is an ordinary resistor; the voltage source v S in Figure 2-15 is a DC voltage source ( V DD ) here, and we have a voltage source v I driving the gate of the MOS transistor. The characteristic i X = f X ( v X ) now becomes the set of outiX iX iX (a) (b) (c) fY(vS– v X) fX(vX) fY(vS – v X) fX(vX) solution vX Figure 2-16. The graphical solution. vS vX vS vX DRAFT 09:28 on 17 October 2006 2-18 2 Elementary Electronic Circuits vY RD iD VDD vDS vI Figure 2-17. vGS An NMOS transistor loaded by a resistor. The transistor is a three-terminal element X, and the resistor is element Y. put characteristics for the MOS device, relating i D to v DS with the voltage v GS as a parameter. These characteristics are plotted in Figure 2-18(a). The characteristic i Y = f Y ( v Y ) for the resistive load is linear, namely i Y = v Y ⁄ R D ; this is plotted in Figure 2-18(b). Making the substitutions corresponding to Eqns. (2.13), the characteristic of the resistive load becomes i D = ( V DD – v DS ) ⁄ R D , noting again that i X is identified with i D and v X is identified with v DS . This equation defines the load line, which is superimposed on the MOS device’s output characteristics in Figure 2-18(c). Referring to this figure, note first that for a given v GS , the iD increasing vGS > VT iY iD fY(VDD – vDS) fY(vY) (a) Figure 2-18. vDS (b) vY (c) VDD vDS Graphical solution for the MOS circuit. The MOS output characteristics are shown in (a). The plot in (b) is the straight line characteristic of the resistive load. This line is superimposed on the output characteristics as a load line in (c). values of v DS and i D are constrained to lie along the particular output characteristic corresponding to this v GS . At the same time, the equation of the load line must always be satisfied. Therefore, the solution point for the circuit must be at the intersection of the load line with the particular output characteristic of the MOS transistor corresponding to this value of v GS . In the circuit of Figure 2-17, we have v GS = v I ; thus for this circuit the process outlined here shows immediately the location of the solution point for a given v I . We will see in the following sections cases of three-terminal devices driving nonlinear loads, and we will also see circuits in which both elements, X and Y, are three-terminal devices and both are “driven”. Transfer Characteristics For circuits such as that in Figure 2-17, we are often interested in knowing the relationship between the output ( v DS in Figure 2-17) and the input ( v I in the figure), as the input varies over a relatively large range3. This relationship is referred to as the transfer characteristic of the circuit, in this case from v I to v DS . 2.3.2 3. Note that this is not the same as therelationship between incremental changes in v DS from its operating-point value and incremental changes in v I from its operating point value. DRAFT 09:28 on 17 October 2006 2.3 Some Graphical Techniques 2-19 We can evaluate the transfer characteristic for the circuit in Figure 2-17 with the aid of the output characteristics and load line in Figure 2-18(c). Consider first v I = 0 ; it should be clear from the circuit that the MOS transistor will be cut off, since v GS = 0 , so that the solution point for the circuit is at the intersection of the load line and the horizontal axis. In fact, you should see that the MOS device will remain cut off so long as v I is less than the threshold voltage V T . Moreover, when the MOS device is cut off, we have i D = 0 , so that v DS = V DD . This, then, is the first part of the transfer characteristic: v DS = V DD ; vI ≤ VT (2.15) Now, what happens as v I is increased past V T ? Since v GS > V T , the device should be conducting. Looking at Figure 2-18(c), we see that the MOS transistor will now be in saturation, because as v GS increases from zero the solution point for the circuit must move along the load line. The point at which the load line intersects the first output characteristic above the horizontal axis in Figure 2-18(c) is clearly a saturation-region operating point for the MOS device. In this region we will have: 1 k'W 2 i D = --  -------- ( v I – V T ) 2 L  again using v GS = v I . As v I is increased further, the solution point will move to the left along the load line, with i D increasing and v DS decreasing. Eventually, the point will be reached at which the MOS device is on the boundary between saturation and the ohmic region. The value of v I at which this occurs can be found by applying the condition at this boundary, namely v GD = V T (recall Section 1.2.2). For v I greater than its value at this point, the device operates in the ohmic region, with: v DS k'W i D =  --------  v I – V T – -------- v DS  L  2  v DS = V DD – i D R D (2.17) v DS = V DD – i D R D (2.16) Construction of the transfer characteristic as outlined above is illustrated in Figure 2-19. On the left side of the figure, the output characteristics and load line in Figure 2-18(c) are redrawn, with the boundary between the saturation and ohmic regions for the MOS device also shown (the dashed curve in the left-hand figure). The transfer characteritic is shown on the right in Figure 2-19. The precise shape of the transfer characteristic MOS off iD vDS VDD MOS sat MOS ohmic VDD Figure 2-19. vDS VΤ vI Transfer characteristic for the MOS circuit example. The correspondence between the transfer characteristic and the device output characteristics and load line is indicated as well. DRAFT 09:28 on 17 October 2006 2-20 2 Elementary Electronic Circuits for the ranges of v I for which the device is in saturation or the ohmic region can be determined using Eqns. (2.16) and (2.17) for particular values of v I . However, the qualitative behavior of the transfer characteristic, including identification of points where the MOS device is at a boundary (cutoff/saturation or saturation/ ohmic), can be obtained with very little effort by inspection of the output characteristics of the driver device with the superimposed load line. Several additional observations are in order at this point. • We see from Figure 2-19 that when v I is sufficiently “low”, v DS is “high”, and when v I is sufficiently “high”, v DS is “low”; this behavior is that of a logic inverter. In between these two regions (cutoff and ohmic), the device is in saturation, and the transfer characteristic has a (possibly large) negative slope about operating points in this region; this behavior is that of an inverting linear amplifier. • For simple circuits, with a single driver and a single load, we can extrapolate from the above example a procedure for finding the transfer characteristic, taking advantage of the driver output characteristics and the load curve: 1. Start with the input at a value such that the driver device is cut off. 2. Increase (or decrease) the input until the device comes out of cutoff, and identify the value of the input at which this boundary is crossed. 3. Increase the input further, following the operation of the circuit along the load curve, noting the regions of operation for the driver and load devices. 4. Each time the circuit reaches a point, according to the load curve, at which either the driver device or the load device crosses a boundary from one region of operation into another, find the value of the input at which this occurs. We will see how this generalized procedure operates when we look at circuits with MOS drivers and MOS loads in the following sections. • It is possible to define a transfer characteristic for any circuit with an input and an output. For circuits even slightly more complex than that in Figure 2-17, say with more than one driver and one load, the transfer characteristic must be obtained by computer analysis. 2.4 MOS Inverters In the last section, a circuit with an MOS transistor and a resistive load was used as an example to illustrate how a load curve and transfer characteristic are constructed. This circuit is often referred to as an MOS inverter with resistive load (see the first of the “additional observations” above on this page). In this section, we at several MOS inverter circuits that use MOS loads. MOS Inverter with Enhancement Load Figure 2-20 shows a circuit in which the driver device M1 is an enhancement-mode NMOS transistor, and the load device M2 is a “diode-connected” enhancement-mode NMOS transistor. The characteristics of the load device ( i D2 vs. v DS2 ) are given in Eqn. (2.5) and displayed in Figure 2-5. In Figure 2-21(a), we have used the technique of the preceding section to construct a load curve from the characteristic in Figure 2-5 and superimpose it on a set of output characteristics associated with the driver device M1. The transfer characteristic for the circuit, plotted as v O vs. v I , with v O = v DS1 and v I = v GS1 , is shown in Figure 2-21(b). 2.4.1 DRAFT 09:28 on 17 October 2006 2.4 MOS Inverters 2-21 VDD iD2 vDS2 M2 iD1 M1 vI vGS1 vO = vDS1 Figure 2-20. An NMOS inverter with enhancement load. We can follow the steps given on page 2-20 to see how the transfer characteristic is constructed. For v I ≤ V T1 , the driver device is clearly off, so that i D1 = i D2 = 0 . In Figure 2-21, this is at point A, with v DS1 = V DD – V T2 ; it is clear from the load curve that M2 is also off here4. The corresponding portion of the transfer characteristic is marked as region I in Figure 2-21(b). As v I increases past V T1 , we see from its output characteristics that M1 is in saturation, and from the load curve that M2 is conducting and thus also in saturation. By following the load curve, we see that v DS1 decreases as v I increases. The corresponding portion of the transfer characteristic is marked as region II in Figure 2-21(b). When v I reaches the point at which v GD1 = V T1 (say at v I = v IB at B in the figures), M1 is at the boundary between saturation and the ohmic region. As v I increases further, M1 is ohmic while M2 remains in saturation; this portion of the transfer characteristic is marked as region III in Figure 2-21(b). Here v DS1 continues to decrease with increasing v I , although much less rapidly than in region II. i D1 vGD1 = VT1 VDD – VT2 vO I A II III B B A (a) Figure 2-21. VDD – VT2 vDS1 VT1 VIB vI (b) Graphical description of the NMOS inverter with enhancement load. (a) Output characteristics of driver devcice with load curve due to load device; (b) Transfer characteristic. The dashed line in (a) at v GD1 = V T1 is the boundary between saturation and the ohmic region for M1. 4. There may appear to be a small anomaly here. It would seem from the characteristic of the load device (see Figure 2-5) that when both devices are off, v DS1 can be anywhere between V DD – V T2 and V DD . In fact, several factors will cause the output to be at V DD – V T2 when both devices are off. DRAFT 09:28 on 17 October 2006 2-22 2 Elementary Electronic Circuits We can develop a mathematical description of the transfer characteristic by using the appropriate nonlinear MOS models for M1 and M2 in each region, taking into account that i D1 = i D2 v DS2 = V DD – v DS1 = V DD – v O • For region I, we have already noted that v O = V DD – V T2 • In region II, with both devices in saturation, we have ( k' ) 2  W 2 ( k' ) 1  W 1 2 2 ----------  ------  ( v I – V T1 ) = ----------  ------  ( V DD – v O – V T2 ) 2  L1  2  L2  It can be shown that this is the equation of a straight line for v O vs. v I . • In region III, with M1 in the ohmic region and M2 in saturation, we have ( k' ) 2  W 2 vO  W 1 2 - ( k' ) 1  ------   v I – V T1 – -----  v O = ----------  ------  ( V DD – v O – V T2 ) L1   2  L2  2  This can be formulated as a quadratic equation that can be solved for v O given the value of v I . MOS Inverter with Depletion Load Figure 2-22 shows a circuit in which the driver device M1 is an enhancement-mode NMOS transistor, and the load device M2 is the two-terminal depletion MOSFET we studied in Section 2.1.3. The characteristics of the load device ( i D2 vs. v DS2 ) are given in Eqn. (2.7) and displayed in Figure 2-8. In Figure 2-23(a), we have constructed a load curve from the characteristic in Figure 2-8 and superimposed it on a set of output characteristics associated with the driver device M1. The transfer characteristic for the circuit, plotted as v O vs. v I , with v O = v DS1 and v I = v GS1 , is shown in Figure 2-23(b). 2.4.2 VDD iD2 M2 iD1 vDS2 M1 vI vGS1 vO = vDS1 Figure 2-22. An NMOS inverter with depletion load. DRAFT 09:28 on 17 October 2006 2.4 MOS Inverters 2-23 Construction of the transfer characteristic from the graph in Figure 2-23(a) begins with the observation that for v I ≤ V T1 , the driver device is clearly off, so that i D1 = 0 . In Figure 2-23(a), this is at point A, with v DS1 = V DD and v DS2 = 0 . Here, M2 is operating in the ohmic region with zero drain current and zero drain-to-source voltage5. The corresponding portion of the transfer characteristic is marked as Region I in Figure 2-23(b). As v I increases past V T1 , we see from its output characteristics that M1 is in saturation, and from the load curve that M2 remains in the ohmic region; this is marked as region II of the transfer characteristic. When v I = V IB , we have reached the point at which v GD2 = V T2 , and M2 is at the boundary between the ohmic region and saturation. For this value of v I , both devices are effectively in saturation. We can also see from Figure 2-23(a) that the slightest increase in v I beyond V IB forces the point at which the circuit operates to move all the way to point C, with M2 in saturation but M1 now ohmic. There is thus an apparent vertical jump in the transfer characteristic (region III in Figure 2-23(b)); there appears to be one single value of v I for which both devices are in saturation, with the range of values between v OB1 and v OB2 possible for v O at this one value of v I . Of course, this anomaly results from our neglecting channel-length modulation and taking the slopes of the MOSFET output characteristics to be zero in saturation; we’ll see shortly with a SPICE example that with channel-length modulation taken into account the slope of the transfer characteristic in region III is large but finite. Finally, for v I > V IB , M1 is ohmic while M2 is saturated (region IV in Figure 2-23(b)). As was the case for the circuit with enhancement load, we can mathematically relate v O and v I in each region of the transfer characteristic. Example 2.5 In the circuit of Figure 2-22., M1 has V T1 = 1V , ( k' ) 1 = 50µA/V , W 1 = 32µm , and L 1 = 8µm ; 2 M2 has V T2 = – 1 V , ( k' ) 2 = 50µA/V , W 2 = 16µm , and L 2 = 16µm . Also, V DD = 5V . We’ll find the details of the transfer characteristic in several steps, doing the easiest parts first. 1. Clearly, from the discussion above, v O = 5V for v I ≤ 1V . iD1 vGD1 = VT1 VDD VOB2 C B vGS1 = VIB vO 2 I A II IV B III A (a) Figure 2-23. VOB1 vDS1 VT1 C vI (b) VDD VIB Graphical description of the NMOS inverter with depletion load. (a) Output characteristics of driver devcice with load curve due to load device; (b) Transfer characteristic. The dashed line in (a) at v GD1 = V T1 is the boundary between saturation and the ohmic region for M1. The portion of the load curve in (a) that is between the points marked ‘A’ and ‘B’ corresponds to M2 operating in the ohmic region, with v GD2 ≤ V T2 . 5. In fact, it important to remember that any MOSFET with v DS = 0 and i D = 0 will be in the ohmic region if v GS exceeds V T with the proper polarity. Thus, for example, an NMOS transistor with v GS > V T and i D = 0 must be in the ohmic region with v DS = 0 . Similarly, a PMOS transistor with v GS < V T and i D = 0 must be in the ohmic region with v DS = 0 . DRAFT 09:28 on 17 October 2006 2-24 2 Elementary Electronic Circuits 2. From Eqn. (2.7), the drain current of M2 in saturation is fixed, namely ( k' ) 2  W 2 2 ( I D2 ) sat = ----------  ------  ( V T2 ) = 25µA 2  L2  We can easily find V IB , the value of v I at which both devices are saturated, since here we must have i D1 = 25µA ; i.e. ( k' ) 1  W 1 2 ----------  ------  ( V IB – V T1 ) = 25µA 2  L1  The solution (taking care to select that solution consistent with M1 operating in saturation) is V IB = 1.5V . 3. We can also easily find the extremes of v O for v I = V IB . At v O = V OB1 , M1 is on the boundary between ohmic and saturated operation, with v GD1 = V T1 . Since v O = – v GD1 + v GS1 , we find that V OB1 = 0.5V . At v O = V OB2 , M2 is on the boundary between ohmic and saturated operation, with v GD2 = V T2 . Since V DD = – v GD2 + v O , we find that V OB2 = 4V . 4. In region IV, M2 is saturated, so the drain current of both devices is 25µA. Since M1 is ohmic with I D1 = 25µA , we can write vO  W 1 ( k' ) 1  ------   v I – V T1 – -----  v O = 25µA 2  L1   For any given value of v I , this equation is a quadratic that can be solved for v O . We find, for example, that v I = 2V results in v O = 134mV , and v I = 5V results in v O = 31mV . 5. In region II, M1 is saturated and M2 is ohmic. The equation for the transfer characteristic is ( k' ) 1  W 1 v DS2  W 2 2 ----------  ------  ( v I – V T1 ) = ( k' ) 2  ------   – V T2 – ----------- v DS2 - 2  L1  2   L2   We can solve this for v DS2 given v I ; we then use v O = V DD – v DS2 to find v O . We use SPICE to investigate the static behavior of this circuit in more detail. In particular, we will add –1 λ = 0.03V to both device models to see the impact of channel length modulation. The transfer characteristic generated by SPICE is shown in Figure 2-24(a). The portion of this characteristic showing the high-to-low transition is expanded and compared with the results found above, neglecting channel-length modulation, in Figure 2-24(b). Close examination of the SPICE results shows that in region III, where both devices are saturated, the slope of the transfer characteristic is large but not infinite. At the midpoint of the transition, with v I = 1.5V , the slope is approximately – 70 . We also find that region III extends from v I = 1.480V to v I = 1.529V . DRAFT 09:28 on 17 October 2006 2.4 MOS Inverters 2-25 vO (V) III vO (V) hand analysis I II IV SPICE analysis vI (V) (a) Figure 2-24. vI (V) (b) SPICE-generated transfer characteristic for the NMOS depletion-load inverter. 2.4.3 CMOS Inverter We have looked at several circuits in which there is a three-terminal driver element and a two-terminal load element. We now consider a circuit consisting of two three-terminal elements, with the two devices acting as both driver and load. This is the CMOS inverter shown in Figure 2-25. In this circuit, one of the devices is NMOS and the other is PMOS; both are enhancement-mode devices. Since the input voltage is connected to both devices, they both are driven. Because both devices are driven, we cannot construct a single load curve for the circuit. We can, however, describe the operation of the circuit graphically for any particular value of v I , by superimposing the single characteristic for M1 and the single characteristic for M2 corresponding to the value of v I and determining the solution point for the circuit as the intersection of the two characteristics (recall Figure 2-16). By carrying out this construction for a sequence of values of input voltage, we can determine the shape of the transfer characteristic. VDD vGS2 M2 vDS2 iD2 vGD iD1 vI vGS1 vO = vDS1 M1 Figure 2-25. A CMOS inverter. DRAFT 09:28 on 17 October 2006 2-26 2 Elementary Electronic Circuits Before proceeding, we will note that for the CMOS inverter in Figure 2-25: i D2 = – i D1 v GS2 = v I – V DD v DS2 = v O – V DD (2.18) while we also have v I = v GS1 and v O = v DS1 . We will construct the transfer characteristic in the context of the following example. As we shall see, the behavior of the CMOS inverter is very similar to that of the inverter with depletion load, with one very important exception. Example 2.6 In the circuit of Figure 2-25., M1 has V T1 = 1V , ( k' ) 1 = 50µA/V , W 1 = 16µm , and L 1 = 8µm ; 2 M2 has V T2 = – 1 V , ( k' ) 2 = 50µA/V , W 2 = 16µm , and L 2 = 8µm . Also, V DD = 5V . For v I ≤ V T1 , M1 is off, and the drain currents of both devices must be zero. For this range of v I , given the device parameters above, we find that v GS2 < V T2 . Therefore, M2 must be either ohmic or saturated. Because i D2 = 0 , M2 must be in the ohmic region with v DS2 = 0 . Consequently, v O = V DD . As v I increases beyond V T1 , M1 will begin to operate in saturation. M2 will remain in the ohmic region until v I reaches the value such that v GD2 = V T2 . Figure 2-26(a) shows the characteristics of M1 and M2, and their use to graphically obtain the operating point of the circuit, for v I = 1.5V and v I = 2V . We may observe from Figure 2-26 that as v I is increased beyond 2V, a point will be reached at which the horizontal (saturation) portion of the characteristics for the two devices exactly overlap. Here both devices are saturated. Indeed the behavior here is exactly the same as that of the inverter with depletion load: there is exactly one value of v I for which both devices are saturated (neglecting channel-length modulation), with a vertical jump appearing in the transfer characteristic at this value. This value of v I , which we’ll call V IB , can easily be found by equating i D1 and – i D2 with both devices saturated. Using Eqn. (2.18): ( k' ) 1  W 1 ( k' ) 2  W 2 2 2 ----------  ------  ( V IB – V T1 ) = ----------  ------  ( V IB – V DD – V T2 ) 2  L1  2  L2  (2.19) 2 iD1 (mA) (a) vGS1 = 1.5V vGS2 = –3.5V iD1 (mA) (b) vGS1 = 2.0V vGS2 = –3.0V vDS1 (V) vDS1 (V) Figure 2-26. Obtaining solution points graphically for the CMOS inverter. DRAFT 09:28 on 17 October 2006 2.4 MOS Inverters 2-27 iD1 (mA) (a) iD1 (mA) (b) vGS1 = 3.0V vGS2 = –2.0V vGS1 = 3.5V vGS2 = –1.5V vDS1 (V) vDS1 (V) Figure 2-27. Obtaining solution points graphically for the CMOS inverter. Taking the square root of both sides, and being careful to select the sign for the square root that gives a solution consistent with both devices being in saturation, we find the solution to be V IB = 2.5V . As v I increases beyond V IB , M2 remains saturated while M1 now is ohmic. Figure 2-27 shows the characteristics of M1 and M2, and their use to graphically obtain the operating point of the circuit, for v I = 3V and v I = 3.5V . Finally, when v I reaches V DD + V T2 (4V in this example), M2 is cut off. Thus, for v I ≥ V DD + V T2 , M2 is off, i D1 = i D2 = 0 , and M1 is ohmic with v O = V DS1 = 0 . The transfer characteristic of the CMOS inverter is shown in Figure 2-28(a). Following the discussion in the above example, there are five regions of operation for the circuit: • In region I, M1 is off, M2 is ohmic, i D1 = i D2 = 0 , and v O = V DD . • In region II, M1 is in saturation, M2 is ohmic, and the drain currents are non-zero. Setting i D1 = – i D2 , we can write an equation for the transfer characteristic: vO VDD VOB2 (a) I II A III IV V vO (V) II III IV (b) VOB1 B VT1 Figure 2-28. VIB VDD+VT2 vI vI (V) Transfer characteristic of the CMOS inverter. DRAFT 09:28 on 17 October 2006 2-28 2 Elementary Electronic Circuits ( k' ) 1  W 1 v DS2  W 2 2 ----------  ------  ( v I – V T1 ) = ( k' ) 2  ------   v I – V DD – V T2 – ----------- v DS2 -  2  L1  2   L2  where Eqn. (2.18) has been used to relate v GS2 to v I ; this equation can be solved for v DS2 given v I , and then for v O using v O = v DS2 + V DD . • In region III, both devices are in saturation and, with channel-length modulation neglected, the transfer characteristic is vertical at v I = V IB (see Eqn. (2.19)) between points ‘A’ and ‘B’ in Figure 2-28(a). The output voltages at these points are easily found, especially when we note that v GD1 = v GD2 = v I – v O (2.20) At point ‘A’, M2 is on the ohmic/sat boundary; at point ‘B’, M1 is on the ohmic/sat boundary. Using Eqn. (2.20): V OB2 = V IB – V T2 V OB1 = V IB – V T1 • In region IV, M1 is ohmic, M2 is in saturation, and we can write: ( k' ) 2  W 2 vO  W 1 2 - ( k' ) 1  ------   v I – V T1 – -----  v O = ----------  ------  ( v I – V DD – V T2 ) L1   2  L2  2  where Eqn. (2.18) has again been used to relate v GS2 to v I . • In region V, M1 is ohmic, M2 is off, i D1 = i D2 = 0 , and v O = 0 . Comparison of Figure 2-28(a) with Figure 2-23(b) shows that the behavior of the depletion-load inverter and the CMOS inverter are qualitatively very similar. The key difference is that the CMOS circuit has two regions (regions I and V in Figure 2-28), one for v I “low” and one for v I “high”, in which one of the devices is off so that no current flows. The importance of this difference will become evident when we consider these circuits as logic elements. Finally, Figure 2-28(b) shows the transfer characteristic for the CMOS inverter with device parameters as in Example 2.6 for the range of v I for which the drain currents are non-zero, both based on hand analysis –1 and as computed by SPICE taking channel-length modulation into account with λ = 0.03V for both devices. 2.5 The Differential Pair The term differential pair is used to describe a class of circuits whose generic form is shown in Figure 2-29. A generic differential pair has two inputs and a pair of matched active elements. The sum of the currents through the active elements is constrained to remain approximately constant, given the connection of the ideal DC current source I YY as shown in the figure. The circuit is differential because, as we are about to see, to first order the circuit responds only to the difference of the two input signals. Differential pairs were built in the early days of electronics using vacuum tubes. We consider here BJT and MOSFET implementations. This section provides an initial look at these circuits. We will investigate them in more detail later on. DRAFT 09:28 on 17 October 2006 2.5 The Differential Pair 2-29 VCC LOAD ACTIVE ELEMENT 1 ACTIVE ELEMENT 2 Input 1 Input 2 IYY –VYY Figure 2-29. A generic differential pair. The two active elements are matched. 2.5.1 β F1 BJT Differential Pair Figure 2-30 shows a differential pair implemented using matched npn BJTs, with I S1 = I S2 = I S and = β F2 = β F . We will assume that Q1 and Q2 are both in the active region, so that i C1 = I S e qv BE1 ⁄ kT i C2 = I S e qv BE2 ⁄ kT Now, we can write the loop equation v I1 = v BE1 – v BE2 + v I2 Defining v IDM to be the difference between the two input voltages, called the differential input voltage6, we can rewrite this equation as VCC RC RC iC1 vC1 vC2 iC2 Q1 vI1 vBE1 IEE -VEE Figure 2-30. Q2 vBE2 vI2 A BJT differential pair with resistive load and using npn transistors. DRAFT 09:28 on 17 October 2006 2-30 2 Elementary Electronic Circuits v IDM ≡ v I1 – v I2 = v BE1 – v BE2 (2.21) We also see that the sum of the currents coming out of the two emitters must be equal to I EE . Using i C = – α F i E for a BJT in the active region, we can write i C1 + i C2 = α F I EE recalling that α F = β F ⁄ ( 1 + β F ) . What remains is a little algebraic manipulation. The key here is to take into account that, after all, we are looking for the circuit’s response to the difference between the two input quantities. If we make a linear transformation from the pair of variables (v BE1,v BE2) to the pair of variables (v BE1 – v BE2,v BE1 + v BE2) , we will be able, using Eqn. (2.21), to express the circuit’s response directly in terms of the differential input voltage v IDM . In fact, let’s define q x DM ≡ ----- ( v BE1 – v BE2 ) kT so that q 1 ----- v BE1 = -- ( x CM + x DM ) kT 2 q 1 ----- v BE2 = -- ( x CM – x DM ) kT 2 (2.23b) (2.22) q x CM ≡ ----- ( v BE1 + v BE2 ) kT (2.23a) We’ll note from Eqn. (2.21) that x DM = ( q ⁄ kT )v IDM . However, note also that x CM is not equal to ( q ⁄ kT ) ( v I1 + v I2 ) . We apply a transformation analogous to that in Eqn. (2.23a)to the two collector currents, with i CDM ≡ i C1 – i C2 i CCM ≡ i C1 + i C2 Using Eqn. (2.23b) to express the exponential relations for i C1 and i C2 in terms of x DM and x CM , we can write i CDM and i CCM as i CDM = I S ( e i CCM = I S ( e ( x CM + x DM ) ⁄ 2 –e ( x CM – x DM ) ⁄ 2 ) = IS e x CM ⁄ 2 (e x DM ⁄ 2 –e – x DM ⁄ 2 ) (2.24a) (2.24b) ( x CM + x DM ) ⁄ 2 +e ( x CM – x DM ) ⁄ 2 ) = IS e x CM ⁄ 2 (e x DM ⁄ 2 +e – x DM ⁄ 2 ) = α F I EE where we have also used Eqn. :(2.22) for i CCM in (2.24b). We can eliminate x CM from these equations in a number of ways. From Eqn. (2.24b), IS e x CM ⁄ 2 α F I EE = -----------------------------------------x DM ⁄ 2 – x DM ⁄ 2 e +e Substitution of this result in the equation for i CDM yields, with some additional algebra: 6. In the discussion that follows, the subscript ‘DM’ stands for differential mode, and the subscript ‘CM’ stands for common mode. DRAFT 09:28 on 17 October 2006 2.5 The Differential Pair 2-31 x DM i CDM = α F I EE tanh  ----------  2  or, in terms of v IDM , qv IDM i CDM = α F I EE tanh  ---------------  2kT  Finally, we can find i C1 and i C2 by taking the sum and difference of i CDM and i CCM : α F I EE qv IDM i C1 = --------------- 1 + tanh  ---------------  2kT  2 α F I EE qv IDM i C2 = --------------- 1 – tanh  ---------------  2kT  2 (2.26) (2.25) These equations are plotted in Figure 2-31. The curves in the figure are transfer characteristics of the BJT differential pair, in terms of the output currents as functions of the differential input voltage v IDM . Note that the output voltage at either collector is easily found, now that we know the collector currents. In particular, from Figure 2-30, v C1 = V CC – i C1 R C and the differential output voltage is v CDM ≡ v C1 – v C2 = – i CDM R C (2.27) v C2 = V CC – i C2 R C With the two collector resistors ( R C ) being equal, these voltages also depend only on v IDM and not on v I1 or v I2 individually. We can make the following observations from the above equations and Figure 2-31: 1. The value of the differential input voltage v IDM controls the fraction of the total emitter current I EE that flows in each device. For v IDM more negative than about – 4 ( kT ⁄ q ) , essentially all the current flows in Q2, with no current in Q1. Similarly. for v IDM greater than about 4 ( kT ⁄ q ) , essentially all the current i / α FIEE iC2 / α FIEE iC1 / α FIEE (q / kT) vIDM iCDM / α FIEE Figure 2-31. Transfer characteristics of a BJT differential pair. The axes are normalized as shown. DRAFT 09:28 on 17 October 2006 2-32 2 Elementary Electronic Circuits flows in Q1, with no current inQ2. Finally, there is a range of v IDM , namely v IDM less than about ( kT ⁄ q ) , for which the output currents i C1 , i C2 , and i CDM vary linearly with v IDM . 2. The differential output current i CDM and voltage v CDM are both zero when v IDM = 0 . 3. The transfer characteristics were derived using nonlinear models for the BJTs. The key result, that the circuit responds only to the difference between the two input voltages, follows without recourse to incremental approximations having validity only for “small” input voltages. The result is valid to the extent the nonlinear models are accurate, and given that the I EE source is ideal. We will see later on, using incremental analysis, what happens when this current source is not ideal, with a finite output resistance. 4. One assumption we did make was that both devices remain in the active region. Clearly, for v IDM sufficiently negative, Q 1 must be cutoff, and for v IDM sufficiently positive, Q 2 must be cutoff (see Eqn. (2.21)). In the first case, we must have i C1 = 0 and i C2 = α F I EE ; indeed, this is exactly what we find using Eqn. (2.26). Similarly, for the second case the equations also provide the correct result. 5. The transfer characteristics are independent to first order of device parameters. We do find α F in the equations. However, for realistic BJTs α F is generally between 0.95 and 1. 2.5.2 MOS Differential Pair Figure 2-32 shows a differential pair implemented using matched NMOS transistors, with ( k' ) 1 = ( k' ) 2 = k' , W 1 = W 2 = W , L 1 = L 2 = L , and V T1 = V T2 = V T . We will assume that M1 and M2 are both in saturation, so that 1 k'W 2 i D1 = --  -------- ( v GS1 – V T )  L  2 Now, we can write the loop equation v I1 = v GS1 – v GS2 + v I2 VDD RD RD 1 k'W 2 i D2 = --  -------- ( v GS2 – V T )  L  2 iD1 vD1 vD2 iD2 M1 vI1 vGS1 ISS –VSS Figure 2-32. An NMOS differential pair with resistive load. M2 vGS2 vI2 DRAFT 09:28 on 17 October 2006 2.5 The Differential Pair 2-33 so that v IDM ≡ v I1 – v I2 = v GS1 – v GS2 Also, since the current coming out of the source of a MOSFET is equal to the drain current, we have i D1 + i D2 = I SS (2.29) (2.28) We’ll now proceed as we did for the BJT differential pair, by transforming to sums and differences of voltages and currents. In particular, let x DM = ( v GS1 – V T ) – ( v GS2 – V T ) so that x DM = v IDM , and also 1 v GS1 – V T = -- ( x CM + x DM ) 2 Defining i DDM ≡ i D1 – i D2 i DCM ≡ i D1 + i D2 1 v GS2 – V T = -- ( x CM – x DM ) 2 (2.30b) x CM ≡ ( v GS1 – V T ) + ( v GS2 – V T ) (2.30a) and expressing the quadratic saturation-region equations for i D1 and i D2 in terms of x DM and x CM , we obtain 1 k'W 1 k'W 2 2 i DDM = --  -------- [ ( x CM + x DM ) – ( x CM – x DM ) ] = --  -------- x DM x CM 2 L  8 L  1 k'W 2 1 k'W 2 2 2 i DCM = --  -------- [ ( x CM + x DM ) + ( x CM – x DM ) ] = --  -------- ( x CM + x DM ) = I SS 4 L  8 L  where we have also used Eqn. (2.29) for i DCM . We eliminate x CM by noting from Eqn. (2.31a) that x CM = ( 2LI DDM ) ⁄ ( k'Wx DM ) . Substitution of this result in Eqn. (2.31b) yields, with some additional algebra: 2 k'W 2 k'W 2 4 i DDM = 2I SS  -------- x DM –  -------- x DM  2L   2L  (2.31a) (2.31b) Solving and writing the result in terms of v IDM , 1⁄2 k'W k'W 2 2 i DDM = v IDM  -------- I SS –  -------- v IDM  L   2L  (2.32) and finally 1 i D1 = -- ( I SS + i DDM ) 2 1 i D2 = -- ( I SS – i DDM ) 2 (2.33) DRAFT 09:28 on 17 October 2006 2-34 2 Elementary Electronic Circuits There is an additional complexity that must be dealt with here that was not an issue for the BJT differential pair (see comment 4 on page 2-32). We’ve assumed that both devices are saturated. Clearly, for v IDM sufficiently positive, i D1 = I SS and M2 must be cutoff; correspondingly for v IDM sufficiently negative. Eqns. (2.32) and (2.33) are consistent with this behavior only if the range of v IDM for which they apply is appropriately limited, namely 2LI SS v IDM ≤ ------------k'W The output voltages at the drains of M1 and M2 are v D1 = V DD – i D1 R D and the differential output voltage is v DDM ≡ v D1 – v D2 = – i DDM R D (2.35) (2.34) v D2 = V DD – i D2 R D The transfer characteristics of the MOS differential pair, in terms of i D1 , i D2 , and i DDM as functions of v IDM , I SS , and device parameters are plotted in Figure 2-33. Note that with the horizontal axis scaled as shown in the figure, the limits defined in Eqn. (2.34) occur at values of ± 2 on the horizontal axis in the figure. Qualitatively, the operation of the BJT and MOS differential pairs are almost identical. The major distinguishing feature of the MOS circuit is the dependence of the transfer characteristics on the current source I SS and the device parameters and geometry, as evidenced by Eqn. (2.32) and Figure 2-33. This was not the case for the BJT circuit, as noted in comment 5 on page 2-32. 2.5.3 A Practical Example We conclude our discussion here of differential pairs with a practical MOS example, shown in Figure 2-34. The circuit in the figure is “practical”, because we have replaced the ideal I SS current source in iD2 / ISS iD1 / ISS k'W ----------v IDM LI SS iDDM / ISS Figure 2-33. Transfer characteristics of a MOS differential pair. DRAFT 09:28 on 17 October 2006 2.5 The Differential Pair 2-35 Figure 2-32 with a real current source, namely the BJT current mirror we studied in Section 2.2.2. We take I SS to be the DC output current of the current mirror, i.e. I SS = I D4 . For the circuit in the figure, assume V DD = 5V , V SS = 5V (i.e., there is -5V DC connected between the sources of M3 and M4 and ground), R D = 20kΩ , and R = 16.5kΩ . Also, assume that the four transistors in Figure 2-34 are identical, with V T = 0.7V k' = 50µA/V 2 W = 16µm L = 2µm We can find I SS by following the DC analysis for the MOS current mirror. Writing a loop equation around the left-hand side of the current mirror including M3: 0 = I R R + V GS3 – V SS Substituting for I R using the saturation-region equation and using the values above, we obtain the quatratic: 0 = 3.3 ( V GS3 ) 2 – 3.62V GS3 – 3.383 The solution that is consistent with M3 being in saturation is V GS3 = 1.7V , so I SS = I D4 = 200µA . As usual, we have ignored channel-length modulation in the nonlinear analysis. To take this effect into account here requires knowledge of V DS4 and thus of the nominal operating-point voltage at the connection of the sources of the differential pair devices M1 and M2. This voltage may in general depend on the intended application of the particular differential-pair circuit. Of course, we do take channel-length modulation into account for incremental analysis, in determining the equivalent incremental output resistance of the current VDD RD vD1 vD2 RD iD1 iD2 M1 vI1 vGS1 ID4 M2 vGS2 vI2 R IR M3 M4 –VSS Figure 2-34. A practical MOS differential pair circuit with resistive load. DRAFT 09:28 on 17 October 2006 2-36 2 Elementary Electronic Circuits mirror circuit as a current source. We will see the impact of this on the operation of the differential pair later on (Section 4.10). There is one additional observation that is worth making at this point. From the nonlinear analysis of the MOS differential pair, we expect that for v I1 = v I2 , I SS i D1 = i D2 = ------ = 100µA 2 In fact, this is true only so long as M1 and M2 remain in the saturation and M3 and M4 continue to operate as a current mirror. For M1 and M2, the boundary between saturation and the ohmic region is at v GD = V T . For M1 we can write a loop equation V DD = i D1 R D – v GD1 + v I1 with a corresponding equation for M2. With v I1 = v I2 , we find v I1 ≤ 4V for M1 and M2 to remain in saturation. For M3 and M4 to operate properly as a current mirror, M4 must remain in the active region; i.e., we must have v GD4 ≤ V T . At this point we consider the loop equation v I1 = v GS1 – v GD4 + v GS4 – V SS and correspondingly for M2, again with v I1 = v I2 . The value of v GS4 is fixed by the operation of the left side of the current mirror, so from the results above v GS4 = V GS4 = V GS3 = 1.7V . The value of v GS1 can be found by noting again that, with v I1 = v I2 and the circuit working properly as a differential pair (i.e. with all four devices in saturation), we must have i D1 = i D2 = 100µA . Using the saturation region equation, we find that v GS1 = 1.407V . Thus M4 will remain in saturation for v I1 > – 2.59V . With v I1 = v I2 , then, these voltages must be between –2.59V and +4V for the differential pair to operate properly. This voltage range is the common-mode input voltage range for the circuit in Figure 2-34. DRAFT 09:28 on 17 October 2006 3.1 Some Amplifier Characteristics 3-1 3 Introduction to Amplifier Circuits We saw several circuits in Chapter 2 that display input-output characteristics that are approximately linear about an appropriate operating point. Examples include the BJT and MOS inverters and the differential-pair circuits. Their linear behavior can be used to provide amplification, i.e. increase in signal amplitude, and other linear signal transformations. In this chapter we begin a detailed study of amplifier circuits with a discussion of several important general characteristics of amplifiers. 3.1 Some Amplifier Characteristics Figure 3-1 shows a stylized representation of an amplifier. Because the incremental input voltage v i and output voltage v o are shown, we might consider that circuit inside the triangle is amplifying the input voltage to produce the output voltage. We might therefore talk about the amplification, or gain, as being the ratio ( v o ⁄ v i ) . If v i is specified, we can find v o as the product of v i and this gain quantity. V+ vi V– vo Figure 3-1. A stylized representation of an amplifier. The terminals labeled V+ and V– represent positive and negative power-supply voltages, each with respect to ground. These connections are not explicitly shown in the figures that follow in this section. Of course, the amplifier is useful when it is driven by a real signal source and delivers the resulting output to a load. In Figure 3-2, the stylized amplifier of Figure 3-1 is driven by the signal source v s with internal resistance R S , and it in turn drives the load resistance R L . In the circuit of Figure 3-2, we are likely to be interested primarily in the ratio ( v o ⁄ v s ) , because it is v s that defines the “true” value of the signal source behind its internal output resistance R S . If we write A VS ≡ v o ⁄ v s , then given v s we would find v o as the product A VS v s . The are a number of properties and characteristics for the amplifier circuit of Figure 3-2 that are generally desirable. These include: V+ RS vs vi V– vo RL Figure 3-2. A simple circuit with the “stylized amplifier” of Figure 3-1. DRAFT 09:28 on 17 October 2006 3-2 3 Introduction to Amplifier Circuits • The value of the gain ( v o ⁄ v s ) should be approximately constant over the range of signal frequencies appropriate for the application. Table 3-1 lists bandwidths for several classes of signals. Table 3-1 Some typical signal bandwidths. Application Telephone-quality speech High-quality audio Baseband video (NTSC) Electrocardiogram signals FM radio intermediate frequency Bandwidth 200Hz to 4kHz 20Hz to 20kHz 0Hz to about 6MHz 0Hz to about 100Hz 10.7MHz ± 75kHz • The gain should be essentially independent of temperature and variations in device parameter values. • The gain in most applications should be independent of the load resistance. In addition, there are applications in which the gain should be independent, at least to some extent, of the source resistance R S . • It is desirable in most applications that there be no DC component in the output voltage when there is no DC component in the input voltage. Note that in many (if not most) practical applications, the input signal source has no DC component, i.e. we would have its total value v S equal to its incremental value v s . We would like the same to be true of the output voltage. • The dynamic range at the input and output must be appropriate for the application. — At the output, the amplifier must be capable of delivering the required peak voltage and current to the load. For example, an audio power amplifier rated at 100W with a load of 8Ω for a single-frequency sinusoid must be capable of delivering a peak output voltage of 40V and a peak output current of 5A into the 8Ω load, all the while maintaining linear operation over the full range of this output “swing”. — At the input, the amplifier must maintain linear operation (in other words, the incremental model of the amplifier must remain a good approximation) over the full range of the input voltage “swing”, i.e. the full peak-to-peak variation of v s . A typical amplifier is an interconnection of subcircuits, or stages, each of which provides a specific function. For example, most off-the-shelf integrated operational amplifiers consist of an “input stage”, a “gain stage”, and an “output stage”. Amplifier stages are sometimes identified by their device configurations. The circuit in Figure 2-17, with the MOS transistor operating in saturation, is a simple common-source amplifier stage; the input is at the gate, the output is at the drain, and the source is “common” to both input and output. The NMOS inverter circuits in Figure 2-20 and Figure 2-22, operating with both driver and load devices in saturation, are also simple common-source amplifier stages. The BJT current mirror was shown acting as a simple current amplifier in Figure 2-11; this circuit can be thought of as a common-emitter stage (input at the base, output at the collector, emitter “common” to both input and output) with a diode-connected BJT added to the input circuit Virtually all practical amplifier circuits are multistage amplifiers, because only rarely can a single-stage circuit meet all of the requirements placed on a design. In order to understand the analysis and design of multistage amplifiers, however, it is necessary to begin by looking at single-stage circuits in isolation. DRAFT 09:28 on 17 October 2006 3.2 Biasing 3-3 VCC RC vs RS vI iB vBE vCE iC VBB Figure 3-3. Biasing a BJT. 3.2 Biasing Biasing is the process of establishing an operating point in a circuit. The operating point in an amplifier circuit must be such that the circuit has a useful, approximately linear input-output relationship for some appropriate variation about the operating point. Recall the simple BJT circuit in Figure 2-17 that was used in the discussion of load lines, load curves, and transfer characteristics in Section 2.3. We noted there that the transfer characteristic of this circuit is linear (strictly speaking, approximately linear) about operating points in the region where the BJT is active. The circuit of Figure 2-17 is redrawn in Figure 3-3, with the input voltage v I shown explicitly as the sum of a DC component and an incremental component. The DC component, shown as V BB in Figure 3-3, will be used to establish an appropriate operating point in the active region for the BJT; the incremental component, denoted by v s in the figure, is the input signal voltage, which the circuit presumably will amplify. The resistor R S is assumed here to be the internal resistance (i.e. the output resistance) of the signal source v s . We will evaluate the biasing of this simple circuit by means of a concrete example. Example 3.1 In the circuit of Figure 3-3, V CC = 10V , R S = 2kΩ , and I C , the collector current at the operating point, is to be 1mA. The BJT has β F = 100 . We need to know V CE at the operating point so that we can determine the value of R C . In the absence of any additional information, we would generally choose the operating point based on considerations related to dynamic range; in particular, a desirable condition is that the maximum positive and negative variations from the operating point of the output voltage (or current) should be equal. From the graphical analysis in Section 2.3.2 of the circuit under consideration, we see that linear operation is approximately maintained for ( V CE ) sat ≤ v CE ≤ V CC . Therefore, a reasonable choice for V CE at the operating point would satisfy V CC + ( V CE ) sat V CC V CE = ------------------------------------- ≈ --------2 2 i.e., V CE = 5V . We can now find R C : DRAFT 09:28 on 17 October 2006 3-4 3 Introduction to Amplifier Circuits V CC – V CE R C = -------------------------- = 5kΩ IC It remains only to find V BB . Since v s is an incremental voltage and thus has no DC component, the loop equation for the DC conditions in the input loop is V BB = I B R S + V BE We have that I B = ( I C ⁄ β F ) = 10µA , and we conventionally take V BE = ( V BE ) active = 0.6V , since we want an operating point with the BJT in the active region. Clearly, then, V BB = 610mV . Having worked through this example, we must now look closely at the circuit in Figure 3-3 and conclude that it simply will not work very well. One major difficulty is that the operating point is highly temperature-sensitive. Consider that in this circuit, with reasonably high β F and R S relatively small as in the example, V BE is held approximately constant at V BB , independent of temperature. On the other hand, recall from Section 1.3.5.4 the temperature dependence of the BJT device parameters. To see its impact in our circuit, we resort to use of the simplified nonlinear model for the active region. With V BE approximately constant, we would expect the increase of I S with temperature to cause I C to increase, while the decrease of ( q ⁄ kT ) would have a countervailing effect on I C . Let’s assume a rise in the junction temperature of the device of 50°C , from 25°C to 75°C ; this rise may be due to self-heating of the device resulting from its dissipating power, or it may be due to an increase of the ambient temperature at the device inside a closed piece of equipment. Whatever the value of I S for the device might be at room temperature, the rule of thumb in Section 1.3.5.4 indicates that I S will be greater by a factor of about 1000 at 75°C . At the same time, the value of the exponential is smaller by a factor of about 30 at 75°C . The apparent net result is that I C will have increased to about 30mA at 75°C . In fact, a simple calculation will show that I C = 30mA is not possible for the circuit in the example above; what must happen is that the device winds up in saturation. The analysis here is obviously simplistic; for example, we have neglected the fact that the increase in I C will be limited by the associated increase in I B and the resulting decrease in V BE . Computer simulation is needed to see precisely how the operating point of the BJT in Figure 3-3 varies with temperature. Nonetheless, we have deduced correctly that the operating point drifts into the saturation region as the temperature increases. In Figure 3-4, the biasing arrangement has been modified so that the DC bias for the base circuit is effectively in parallel with rather than in series with the input signal. The capacitor C C is necessary to prevent the signal source v s and its internal resistance R S from altering the DC conditions of the base circuit established by the connection of V CC through R B . It is easily shown that in the circuit of Figure 3-4, the DC base current I B is approximately constant with respect to temperature. Thus in this circuit the increase of β F with temperature will cause an increase in I C . In this circuit as in the previous circuit the operating point of the BJT will drift into the saturation region as the temperature increases. So, how does one establish an operating point in the active region that is stable with temperature and other sources of device parameter variation? There are two classes of practical, viable biasing techniques for BJTs and MOS transistors. One, employed in integrated circuits, takes advantage of the excellent matching that is achievable between adjacent devices on a chip. The other, employed in circuits built with discrete devices, cannot rely on device matching and so must resort to other means to maintain a stable operating point. DRAFT 09:28 on 17 October 2006 3.2 Biasing 3-5 (a) VCC RC iC RB vCE (b) VCC IB RC IC RS vs RB CC vBE VBE VCE Figure 3-4. “Constant-current” biasing of a BJT. Because the capacitor is an open-circuit at DC, the simplified circuit in (b) can be used to solve for the operating point of the complete circuit in (a). Because the biasing arrangements considered so far are closer to the latter variety, a practical discrete-oriented scheme will be evaluated first. Discrete-Circuit Biasing Figure 3-5 shows a classical discrete common-emitter stage incorporating a practical biasing arrangement. The components that establish the stable operating point are the base resistors R B1 and R B2 , and the resistor R E in series with the emitter. The capacitors in the circuit are obviously open circuits for DC (i.e. at zero frequency), and will be assumed to be large enough to be considered short circuits at any signal frequency of interest. The capacitor C B isolates the BJT at DC from the source resistance, thus preventing this resistance from affecting the device’s operating point. The capacitor across R E is intended to short this resistor out at signal frequencies. With the capacitors as open circuits at DC, the operating point of the circuit in Figure 3-5 can be found from the circuit’s DC equivalent shown in Figure 3-6(a). This circuit is most easily analyzed by taking a Thevenin equivalent circuit of the portion to the left of the base, as indicated by the arrow in Figure 3-6(a). This portion of the circuit is isolated in Figure 3-6(b). The complete DC circuit incorporating the resulting Thevenin equivalent is shown in Figure 3-6(c), with  R B2  V BB = V CC  ------------------------   R B1 + R B2 R B1 R B2 R BB = -----------------------R B1 + R B2 (3.1) 3.2.1 Referring to Figure 3-6(c), the loop equation for the base loop is VCC RC RS vs RB1 CB RB2 RE vCE vO CE Figure 3-5. A discrete common-emitter stage with practical biasing. DRAFT 09:28 on 17 October 2006 3-6 3 Introduction to Amplifier Circuits (a) VCC RC IC VCC (b) (c) VCC RC IC VCE RB1 IB VCE RB1 IB VBB RBB IB RB2 RE RB2 RE Figure 3-6. DC equivalent circuit for the practical common-emitter stage in Figure 3-5. The circuit in (b) is that part of the circuit in (a) that is to the left of the base (as indicated by the arrow in (a)). In (c), this part of the circuit is replaced by its Thevenin equivalent. V BB = I B R BB + V BE + ( I B + I C )R E while the loop equation for the collector loop is V CC = I C R C + V CE + ( I B + I C )R E Assuming that the BJT is in the active region, we use V BE = ( V BE ) active IC = βF IB (3.2) (3.3) in the above equations. Eqn. (3.2) is solved for I B and I C , and then Eqn. (3.3) can be solved for V CE . The stability of the operating point in this circuit is established by negative feedback that results from the voltage drop I C R E appearing in the base loop. Assume for example that I C has increased, perhaps because of the increase of β F with temperature. The associated increase in I C R E will tend, following Eqn. (3.2), to reduce V BE , with the result that the original increase in I C is reduced in magnitude. This same negative feedback would tend to reduce the amplification provided by the circuit (as we will see later on). The purpose of C E is to short out R E at signal frequencies, thereby eliminating the feedback and any associated reduction of gain. Despite the presence of R E , it is still possible to apply the graphical techniques of Section 2.3 to the circuit in Figure 3-5. For purposes of determining the operating point, we consider the circuit at DC. We can construct a DC load line for the circuit, valid for the BJT operating in the active region, from Eqn. (3.3). Its equation is 1 V CC = I C R C +  1 + -----  R E + V CE  β  F (3.4) The DC load line, superimposed in Figure 3-7 on a set of output characteristics for the BJT in Figure 3-5, is associated with determination of the operating point of the circuit. Assuming that C E is arbitrarily large, the voltage from emitter to ground must remain constant at its operating-point DC value even with the signal source v s applied (so long as v s has no component at zero frequency). Any change in the voltage at the collector (i.e. to ground) from its operating-point value, due to v s , is thus equal to the change in the collec- DRAFT 09:28 on 17 October 2006 3.2 Biasing 3-7 iC AC load line IC DC load line VCE Figure 3-7. VCC vCE DC and AC load lines for the practical discrete common-emitter stage. tor-to-emitter voltage from its operating-point value. As a consequence, the variations of collector current and collector-to-emitter voltage due to v s must follow a load line with slope – 1 ⁄ R C rather than the DC load line, whose slope is approximately – 1 ⁄ ( R C + R E ) from Eqn. (3.4). This load line for signals, usually called an AC load line, passes through the DC load line at the operating point, as shown in Figure 3-7. Note that the extremes of v CE , and thus of the output voltage from collector to ground, for which the BJT remains in the active region would be determined from the AC load line in the figure. The assumed short-circuit behavior of C E and also C B at signal frequencies is highlighted further by considering the incremental model for the circuit in Figure 3-5; it is shown in Figure 3-8. It is important to keep in mind, however, that no matter how large these capacitors are, there will be sufficiently low frequencies at which their impedances will not be negligible. In other words, the capacitors associated with the biasing arrangement in Figure 3-5 will limit the performance of the common-emitter stage in the figure as an amplifier at sufficiently low frequencies. Design of such a circuit includes selection of values for these capacitors such that their impact is acceptably small at the lowest signal frequency of interest. We will take note of this when we begin to discuss amplifier bandwidth considerations in Section 3.4. Using terminology to be introduced there, we say that Figure 3-8 shows the incremental model “at midband” of the circuit in Figure 3-5. Integrated-Circuit Biasing We have already seen several circuits in Chapter 2 in which the matching of devices is used to establish stable operating conditions. Classic examples are the current mirror circuits discussed in Section 2.2 and the differential pair circuits discussed in Section 2.5. Recall the BJT differential pair circuit that was shown in Figure 2-34. This circuit is redrawn here in Figure 3-9. with the addition of real voltage sources v S1 and v S2 connected to the inputs through source resistances R S . We again take Q1 and Q2 to be matched and Q3 and Q4 to be matched, and we recall that the latter two devices form a current mirror whose DC output current, I C4 , is the current I EE that drives the connection RS vs RB1 B 3.2.2 rb RB2 rπ vπ gmvπ E C ro RC Figure 3-8. Incremental model for the discrete common-emitter stage in Figure 3-5. The capacitors associated with biasing are assumed to be short circuits at signal frequencies. DRAFT 09:28 on 17 October 2006 increasing iB > 0 vo 3-8 3 Introduction to Amplifier Circuits VCC RC RC vC1 iC1 vC2 iC2 RS iB1 vS1 vI1 vBE1 Q1 Q2 vBE2 IC4=IEE iB2 R S vI2 vS2 R IR Q3 Q4 –VEE Figure 3-9. A practical BJT differential pair circuit. of the emitters of Q1 and Q2. The analysis in Section 2.5.1 showed that with the operating-point values of both v I1 and v I2 equal to 0, this circuit behaves linearly for “small” variations about an operating point at · I C1 = I C2 = 0.5α F I EE . For the more realistic source configuration shown in Figure 3-9, the operating point will be evaluated assuming that the sources v S1 and v S2 are purely incremental, i.e. with V S1 and V S2 both equal to zero. Note that this will be a “best-case” scenario if it yields a useful operating point because there is no need in this case to add explicit DC sources at the inputs for biasing purposes. With the sources being purely incremental, we have the following loop equation at DC: I B1 R S + V BE1 – V BE2 – I B2 R S = 0 or ( I B1 – I B2 )R S + ( V BE1 – V BE2 ) = 0 (3.5) Assuming that the devices are both operating in the active region, we have that I B1 = I C1 ⁄ β F and I B2 = I C2 ⁄ β F . Substitute these relations into Eqn. (3.5), and then consider that if V BE1 > V BE2 we must have I C1 > I C2 (and vice versa) based on what we already know about the operation of the differential pair. The only possible solution for Eqn. (3.5) must be V BE1 = V BE2 I B1 = I B2 I C1 = I C2 (3.6) The node equation at the junction of the Q1 and Q2 emitters is: I EE + I E1 + I E2 = 0 or, using the fact that the devices are active: DRAFT 09:28 on 17 October 2006 3.2 Biasing 3-9 I C1 I C2 I EE = ------- + ------αF αF Thus the operating point is characterized by α F I EE I C1 = I C2 = --------------2 (3.7) (3.8) exactly as for the circuit with R S = 0 . Note again that I EE = I C4 , which can be found by DC analysis of the current mirror made up of Q3 and Q4. The value of V BE1 (and thus of V BE2 ) can be found, either from the exponential I C vs. V BE relation or using the piecewise linear model with V BE ≈ 0.6V in the active region. The voltage to ground at the junction of the Q1 and Q2 emitters, V E , is – V BE1 – I B1 R S . The DC collector-to-emitter voltage for Q1 and Q2 can be found from the loop equation α F I EE R C V CE1 = V CE2 = V CC – ---------------------- – V E 2 (3.9) where the known result for the DC collector currents has been used. Eqn. (3.9) would be used to verify that the operating points for Q1 and Q2 are properly in the active region. Assuming the BJTs are adjacent to one another on the chip, their junctions will be at approximately the same temperature. Since they are matched, their characteristics will track with temperature. Because the voltage drop across the current-setting resistor R is generally much larger than V BE3 , the current I R will be approximately independent of the variation with temperature of V BE3 . It is easily seen from Eqn. (2.8), which describes the operation of the BJT current mirror, that the relationship between I R and I C4 is minimally dependent on temperature; α F is also minimally dependent on temperature. As a result, the temperature variation of I C1 and I C2 is extremely small. A detailed incremental analysis of BJT and MOS differential pairs will be presented later on, in Chapter 4. Additional Comments on Biasing We have seen that for the discrete common-emitter stage the source v s must be capacitively coupled to the stage so that it does not interfere with the biasing of the BJT. By contrast, the sources connected to the inputs of the differential pair in Figure 3-9 can be directly coupled, as shown, without interfering with the circuit’s biasing; this is generally the case so long as these sources can conduct the DC base current of the BJTs and the DC voltage drops across the source resistors are not excessive. We might also consider the connection of an external load resistance to these circuits. In either case, we are confronted with two alternatives: 1. Capacitively couple the load to the output, so that the load does not interfere with the circuit’s biasing. This is depicted for the discrete common-emitter stage in Figure 3-10. Note that the AC load line for the circuit in this figure (recalling the discussion in Section 3.2.1 regarding Figure 3-7) must now take the load resistance R L into account, so that its slope will be – 1 ⁄ ( R C || R L ) . Note also that the voltage v o 3.2.3 DRAFT 09:28 on 17 October 2006 3-10 3 Introduction to Amplifier Circuits VCC RC RS vs RB1 CB RB2 RE CE CL RL vo Figure 3-10. The discrete common-emitter stage with a capacitively coupled load. shown across R L has no DC component, being essentially equal to the signal voltage (i.e. due to v s ) at the collector of the BJT (assuming again that v s has no component at zero frequency). 2. Directly couple the load to the output, and design the biasing for the circuit to take into account the fact that some DC current will flow through the load. In the case of the circuit in Figure 3-10 with C L replaced by a short circuit, for example, it appears that this DC current will increase the DC voltage drop across R C , thereby reducing the DC voltage at the collector and altering the circuit’s operating point. The orientation of this course is towards the design of circuits appropriate for integrated implementation and circuits using integrated subcircuits. For this reason, we will not consider further the details of biasing discrete stages such as the common-emitter circuit in Figure 3-10. Moreover, we will see later on that the biasing of an integrated multistage amplifier (e.g. an op amp) is generally designed with the stages directly coupled and taking into account the interaction of their DC conditions. As a consequence, as we seek to understand how different single-stage configurations behave as linear circuits we will often ignore issues and even components associated with biasing, assuming that specified, appropriate operating points have been established for any BJTs and MOS transistors. 3.3 Classification and Modeling of Amplifiers In the discussion above, we were somewhat arbitrary in identifying the input and output signals of the amplifier as being voltages. In fact, we could just as easily consider either or both to be currents. Since there are four pairs of possibilities (input and output as either voltage or current), we have four basic classes of amplifiers. 3.3.1 Voltage Amplifiers Figure 3-2 showed a “stylized” voltage amplifier between a source and a load. In Figure 3-11, the voltage amplifier is redrawn to show it explicitly as a voltage-controlled voltage source with equivalent input and output resistances. The right-hand side of the circuit in the figure is a Thevenin equivalent circuit for the amplifier together with the voltage source v s and its resistance R S . Thus, the voltage-controlled voltage source labelled A VSO v s represents the open-circuit output voltage of the amplifier and R o its equivalent output resistance, with the amplifier driven by the source v s as shown. We can see the effect of the amplifier output resistance R o on the overall voltage gain A VSL ≡ v o ⁄ v s by noting from the figure that  RL  A VSL = A VSO  ------------------   R o + R L (3.10) DRAFT 09:28 on 17 October 2006 3.3 Classification and Modeling of Amplifiers 3-11 RS vs Ri Figure 3-11. ii vi Ro AVSOvs vo RL Model of a voltage amplifier. The amplifier is within the dashed box. Clearly, the larger R o is compared to R L , the more the overall voltage gain is reduced from its open-circuit value. Ideally, for a voltage amplifier (like a voltage source) R o would be zero, in which case A VSL is independent of the load R L . Figure 3-11 also indicates that the amplifier has an equivalent input resistance R i , which is equal to the ratio of the input voltage v i to the input current i i . To see the effect of the amplifier input resistance R i on the overall gain, we need to look at the gain from a slightly different perspective. Instead of A VSO , let’s consider the voltage gain from v i at the amplifier input to v o across the load; i.e. define A VIL ≡ v o ⁄ v i . It can be seen from the circuit in Figure 3-11 that the overall gain A VSL satisfies:  Ri  A VSL = A VIL  -----------------  R i + R S (3.11) It is evident from Eqn. (3.11) that the smaller R i is compared to R S , the more the overall voltage gain is reduced from A VIL . For an ideal voltage amplifier, R i would be infinite, in which case A VSL is independent of the source resistance R S . Current Amplifier We can also consider a current amplifier, i.e. a circuit that amplifies an input current and acts like a current source in delivering the resulting output to a load. In this case, we represent both the input source and the amplifier output using Norton equivalent circuits, as shown in Figure 3-12. Here, the right-hand side of the circuit is a Norton equivalent circuit for the amplifier together with the current source and its resistance R S . Thus, the current-controlled current source labelled A ISS represents the short-circuit output current. Note that, by standard convention, the reference direction for both the input current i i and the output current i o is taken to be flowing into the amplifier. We can see the effect of the amplifier output resistance R o on the overall current gain A ISL ≡ i o ⁄ i s by noting from the figure that 3.3.2 ii is RS Ri Figure 3-12. Model of a current amplifier. io vi AISS is Ro RL DRAFT 09:28 on 17 October 2006 3-12 3 Introduction to Amplifier Circuits  Ro  A ISL = A ISS  ------------------   R o + R L (3.12) Clearly, the smaller R o is compared to R L , the more the overall current gain is reduced from its short-circuit value. If the amplifier output were an ideal current source, R o would be infinite, and A ISL would be independent of the load R L . To see the effect of the amplifier input resistance R i on the overall gain, we again need to look at the gain from a slightly different perspective. Instead of A ISS , we consider the current gain from i i at the amplifier input to i o through the load; i.e. define A IIL ≡ i o ⁄ i i . It can be seen from the circuit in Figure 3-12 that the overall gain A IS satisfies:  RS  A ISL = A IIL  -----------------  R i + R S (3.13) It is evident from Eqn. (3.13) that the larger R i is compared to R S , the more the overall current gain is reduced from A IIL . Ideally, R i would be zero, in which case A ISL is independent of the source resistance R S . 3.3.3 Transconductance Amplifier It is possible to define a circuit that amplifies an input voltage but acts like a current source in delivering the resulting output to a load. Such a circuit, shown in Figure 3-13, is called a transconductance amplifier, and its gain, being a current-to-voltage ratio, has units of conductance. Here, the right-hand side of the circuit is a Norton equivalent circuit for the amplifier together with the voltage source v s and its resistance R S . Thus, the voltage-controlled current source labelled G MSS v s represents the short-circuit output current. The effect of the amplifier output resistance on the overall transconductance (gain) G MSL ≡ i o ⁄ v s is identical to its effect on the overall gain of the current amplifier, namely  Ro  G MSL = G MSS  ------------------   R o + R L (3.14) Ideally, the amplifier output would be an ideal current source with infinite output resistance, and we would have G MSL = G MSS The effects of R i on the overall gain are the same for the transconductance amplifier as for the voltage amplifier. Define G MIL to be the transconductance from v i at the amplifier input to i o through the load; then from Figure 3-13 we see that RS vs Ri Figure 3-13. ii vi GMSSvs Ro io RL Model of a transconductance amplifier. DRAFT 09:28 on 17 October 2006 3.3 Classification and Modeling of Amplifiers 3-13 ii is RS Ri Figure 3-14. Model of a transresistance amplifier. Ro vi RMSOis vo RL  Ri  G MSL = G MIL  -----------------  R i + R S (3.15) The ideal transconductance amplifier, like the ideal voltage amplifier, would have infinite input resistance, with the overall gain then being independent of R S . Transresistance Amplifier Clearly, there is one remaining possibility, namely a circuit that amplifies an input current but acts like a voltage source in delivering the resulting output to a load. A circuit with this property, shown in Figure 3-14, is called a transresistance amplifier; its gain is a ratio of voltage to current and thus has units of resistance. The current-controlled voltage source R MSO i s represents the open-circuit output voltage of the amplifier, with R MSO being the open-circuit transresistance taking the source resistance into account. The effect of the amplifier output resistance on the overall transresistance (gain) R MSL ≡ v o ⁄ i s is identical to its effect on the overall gain of the voltage amplifier, namely:  RL  R MSL = R MSO  ------------------   R o + R L (3.16) 3.3.4 An ideal transresistance amplifier would have zero output resistance, in which case the overall gain would be independent of R L . If we define R MIL to be the transresistance from i i at the amplifier input to v o across the load, then it is clear from Figure 3-14 that  RS  R MSL = R MIL  -----------------  R i + R S (3.17) An ideal transresistance amplifier would have zero input resistance, in which case the overall gain would be independent of R S . 3.3.5 Amplifier Models Independent of Source and Load The models for the four types of amplifiers discussed above include the possibility that the quantities that characterize the amplifier, namely the gain and the input and output resistances, may depend on the source and load resistances. Certainly, the controlled sources and output resistances in the Thevenin and Norton equivalent circuits may depend on the value of R S in each case. Similarly, the load-referred gains, namely A VIL , A IIL , G MIL , and R MIL , and the input resistances may clearly be dependent on the value of load resistance R L in each case. DRAFT 09:28 on 17 October 2006 3-14 3 Introduction to Amplifier Circuits RS vs ii vi Ri Ro AVIOvi vo RL Figure 3-15. Possible model of a voltage amplifier. It is interesting to consider if it possible to model an amplifier in isolation, that is to attempt to view the elements inside the dashed boxes in Figures 3-11 through 3-14 independently of the source and load. What is of course ultimately of interest for any amplifier is the overall gain from source to load, e.g. A VSL for a voltage amplifier. On the other hand, it would appear useful to have an intrinsic characterization of an amplifier that is independent of the source and load. Consider for example an attempt to construct a model of the voltage amplifier in Figure 3-11 in which the open-circuit voltage gain characterizes the amplifier with respect to the amplifier input voltage v i rather than with respect to the source voltage v s ; such a model is shown in Figure 3-15. The model in this figure would seem useful because the gain A VIO appears to be an intrinsic property of the amplifier, independent of both source and load resistances, while the interactions between these resistances and the amplifier’s input and output resistances appear explicitly in the expression for the overall gain. That is,  RL   Ri  A VSL = A VIO  ------------------   -----------------  R o + R L  R i + R S (3.18) In fact, it can be shown that a voltage amplifier can be represented using the model in Figure 3-15 only if it contains no feedback paths from the output back to the input or if the input resistance is infinite. One can determine if this is the case for a voltage amplifier by setting v s to zero in the generally applicable model in Figure 3-11 and replacing the load resistance with a voltage source. If in this configuration v i = 0 , then there cannot be feedback through the amplifier or else the input resistance is infinite. It should be noted that in those cases for which the presence of feedback causes the voltage-amplifier model in Figure 3-15 to be invalid, there is an added complication even with respect to the model in Figure 3-11. The latter is a “general” model of the amplifier only to the extent that it is a Thevenin equivalent circuit looking into the amplifier ouput terminals and thus includes the voltage source v s and its resistance R S . The fact that A VSO and R o depend on R S is a natural part of the Thevenin equivalent representation. What confuses the issue with respect to the model in Figure 3-11 in these cases is that the input resistance is a function of the load resistance. When Eqn. (3.10) is used to find the overall gain A VSL , then any dependence of R i on R L is immaterial. When we find the value of R i , however, we must keep in mind that we have tied the amplifier model to its load resistance. Of course, when there is no feedback or R i is infinite, the elements inside the dashed box in Figure 3-15 that represent the amplifier are independent of the source and load connected to the amplifier. This distinction is reflected in the figures, in that R i is shown as an explicit resistance in Figure 3-15 but is only “pointed to” inside the dashed box in Figure 3-11. The discussion so far in this section has focused on the voltage amplifier as an example. Clearly, similar considerations apply to the three other classes of amplifiers. Thus, the current amplifier in Figure 3-12 can be modeled by the circuit in Figure 3-16 with the controlled source independent of both source and load conditions, but only if the circuit has no feedback or if the input resistance is zero. To check this, we would set the current source i s to zero in Figure 3-12 and replace the load R L with an independent current source, say i x . If DRAFT 09:28 on 17 October 2006 3.3 Classification and Modeling of Amplifiers 3-15 ii is RS vi Ri AIIS ii Ro io RL Figure 3-16. Possible model of a current amplifier. the input current i i is zero under these conditions, then the “intrinsic” model of Figure 3-16 can be used for the current amplifier, and the overall current gain can be expressed as  Ro   RS  A ISL = A IIS  ------------------   -----------------  R o + R L  R i + R S (3.19) Again, if the model of Figure 3-16 cannot be used, we have the Norton equivalent circuit in Figure 3-12, and the dependence of A ISS and R o on R S is a natural part of the Norton representation; but when we compute R i we must keep in mind that its value may depend on the particular value of R L . As was the case for the voltage amplifier, we have reflected this distinction in the figures, in that R i is shown as an explicit resistance in Figure 3-16 but is only “pointed to” inside the dashed box in Figure 3-12. The discussion in this section may seem rather nit-picky. However, when we use a simple model or equivalent circuit to represent a possibly complex circuit configuration (an amplifier, for example), it is important to understand the limits of the simplified representation. We will find that some amplifier stages satisfy the conditions for being representable by intrinsic models, while others do not. In our analysis of single-stage amplifiers in Chapter 4, we will develop intrinsic models where possible, and where this is not possible we will keep in mind the dependence of R i on load resistance in the models in Figures 3-11 through 3-14. The significance of the constraints outlined here on how the various amplifier models are used should become clear later on, especially when we study multistage amplifiers. Additional Comments Return now to the four general models shown in Figures 3-11 through 3-14. As we have already noted, each of these is simply either a Thevenin equivalent circuit (voltage and transresistance amplifiers) or a Norton equivalent circuit (current and transconductance amplifiers) looking into the output terminals of an amplifier. Explicit inclusion of the input signal source and its source resistance in these equivalent circuits is superfluous. These are included in the models in Figures 3-11 through 3-14 as a means of indicating whether the input signal source is a voltage or current in each case, and also to emphasize the fact the overall gain will depend on the source resistance. Of course, any real signal source can be modeled as either a voltage source, using a Thevenin equivalent circuit, or as a current source, using a Norton equivalent circuit. Similarly, we can employ either a Thevenin equivalent circuit or a Norton equivalent circuit to model what we see looking into the output terminals of any amplifier, so long as the amplifiers output resistance is finite and non-zero. For example, an amplifier driven by a voltage source and modeled as a voltage amplifier with open-circuit voltage gain A VSO and output resistance R o can also be modeled as a transconductance amplifier with output resistance R o and short-circuit transconductance G MSS equal to – A VSO ⁄ R o . It may appear, then, that the distinctions being made here are rather artificial. At the same time, it is easy to think of amplifiers most often in terms of their input and output voltages, thus considering them at least implicitly to be voltage amplifiers. In fact, the distinctions are worth making. Consider that a signal source with a high source impedance (examples include certain types of transducers) is “closer” to being an ideal current source that an ideal voltage source, and its output may be dealt DRAFT 09:28 on 17 October 2006 3.3.6 3-16 3 Introduction to Amplifier Circuits ZS Vs Zi Figure 3-17. Ii Vi Zo AVSOVs Vo ZL Model of a voltage amplifier. This model includes the dependence on frequency of gain and impedances. with more efficiently by an amplifier with a low input impedance that “processes” the input current, i.e. a current amplifier or a transresistance amplifier. In the same way, there are applications in which a load is more efficiently driven by an amplifier whose output is a good current source than by an amplifier whose output is a good voltage source. Finally, we should note that even when an “intrinsic” model is valid for a particular amplifier, the overall gain is likely to depend on the source and load resistances; this is clear in Eqns. (3.18) and (3.19) for the voltage amplifier and current amplifier, respectively. Ideally, we would like the overall gain to be essentially independent of the source and load resistance values, at least for some range of each. While the presence of feedback from output to input seems to tie the behavior of an amplifier to the characteristics of the source and load, as discussed in Section 3.3.5, we will see later on that the judicious use of feedback will permit us to approach the ideal behavior we look for. 3.4 Amplifier Bandwidth Considerations In the models outlined in Section 3.3, there is an apparent assumption that the amplifier gains are independent of frequency and that the inputs and outputs are purely resistive. For most amplifiers, this is in fact the case for some range of frequencies. For any given amplifier, we would expect this range, usually referred to as the midband range for the amplifier, to include the range of signal frequencies appropriate for the intended application. For example, referring to Table 3-1, the midband range of an amplifier for high-quality audio signals should extend at least from 20Hz to 20kHz. The bandwidth of an amplifier is usually identified with its midband range. We will define the concept of midband more precisely by considering that it extends from a lower bound f L Hz (or ω L = 2πf L radians/sec) to an upper bound f H Hz (or ω H = 2πf H radians/sec). In order to determine these boundary frequencies for any given amplifier and characterize the operation of the amplifier over a range of frequencies that extends below f L and above f H , we need to explicitly take into account the effects of all reactive components in the circuit. This will lead to evaluation of amplifier gains as transfer functions and to analysis of input and output behavior in terms of impedance (or admittance) rather than resistance. Thus, for example, the voltage-amplifier model in Figure 3-11 is generalized as shown in Figure 3-17. Referring to the figure, the open-circuit voltage gain A VSO , input impedance Z i , and output impedance Z o are all functions of the complex frequency variable s. The figure also shows the possibilty of a complex source impedance Z S and load impedance Z L . Following Eqn. (3.10), the end-to-end voltage gain A VSL is also a function of s and is given by: ZL ( s )   A VSL ( s ) = A VSO ( s )  --------------------------------   Z o ( s ) + Z L ( s ) Finally, the quantities V s , V i , V o , I i , and I o noted in the figure represent complex amplitudes of the associated voltages and currents as complex sinusoids with complex frequency s. In discussing frequency response, DRAFT 09:28 on 17 October 2006 3.4 Amplifier Bandwidth Considerations 3-17 Lm(gain) (dB) Lm(Ao) Lm(Ao) – 3 midband range ωL Figure 3-18. ωH ω (log10) Log-magnitude plot for a typical amplifier-gain characteristic. The horizontal axis is scaled logarithmically in radian frequency ω. A o is the value of the midband gain. jωt we generally think in terms of real frequencies, i.e. s = jω = j2πf . If v s ( t ) = V s e jωt some frequency ω , then v o ( t ) = V o e with V o = A VSL ( jω )V s Dealing with the complex quantities in terms of their magnitude and phase leads to V o = A VSL ( jω ) V s ; arg ( V o ) = arg ( A VSL ( jω ) ) + arg ( V s ) in Figure 3-17 for (3.20) (3.21) where arg ( z ) is the phase (i.e. “argument”) of the complex quantity z. In terms of real signals, if v s ( t ) is a real sinusoid with real amplitude a s and phase θ s , i.e. v s ( t ) = a s cos ( ωt + θ s ) , the output is a real sinusoid with the same frequency. That is, v o ( t ) = a o cos ( ωt + θ o ) , with a o = A VSL ( jω ) a s ; θ o = arg ( A VSL ( jω ) ) + θ s (3.22) It is convenient to use a logarithmic measure to characterize the magnitude of gain quantities. We define the log magnitude of a complex quantity z, referred to as Lm ( z ) , to be Lm ( z ) = 20log10 z The units used for log magnitude are decibels (dB). Return now to consideration of the frequencies ω L and ω H that bound the midband region. By convention, these frequencies are defined to be the frequencies at which the magnitude of the gain is reduced to 1 ⁄ 2 times its midband value. It can easily be seen from Eqn (3.23) that at these frequencies the log magnitude of the gain is 3dB below its midband value. For this reason, ω L and ω H are referred to as the lower 3dB frequency and upper 3dB frequency, respectively. A plot of the log magnitude for a typical amplifier gain is shown in Figure 3-18. In some cases, the midband range of an amplifier will be explicitly limited to cover only the range of frequencies appropriate to the intended application, through the addition of components specifically for this purpose. In all cases, however, the midband range of an amplifier will be limited by unavoidable effects associated with the active devices in the circuit. In particular, (3.23) DRAFT 09:28 on 17 October 2006 3-18 3 Introduction to Amplifier Circuits • The high-frequency performance of an amplifier is limited by the effects of capacitances internal to any BJTs and MOS transistors employed. • The low-frequency performance of an amplifier is limited by the effects of any capacitances used in establishing the DC operating conditions of the circuit. For example, the capacitors C B , C E , and C L in Figure 3-10 limit the low-frequency gain of the discrete common-emitter amplifier in that figure, with the gain being zero at ω = 0 . Our interest here is focused on these unavoidable limitations on amplifier bandwidth. Moreover, based on the comments in Section 3.2.3, we will generally assume that there are no capacitors limiting the low-frequency performance; i.e., we will assume that midband extends down to ω = 0 and there is no ω L . In terms of bandwidth limitations, our focus will thus be on the effects of device capacitances on high-frequency performance. Before we investigate these effects, we pause to review some important characteristics of transfer functions and their applicability to the representation of amplifier gain quantities. 3.5 Amplifier Gains as Transfer Functions It should be clear from the discussion above that the gain of an amplifier, e.g. A VSO ( s ) or A VSL ( s ) for the circuit in Figure 3-17, is a transfer function of a linear system. As such, it must be a rational function of s, i.e. expressable as the ratio of polynomial functions of s. Using A ( s ) to represent an arbitrary amplifier gain function, we thus can always write N(s) A ( s ) = ----------D(s) (3.24) where N ( s ) and D ( s ) are polynomials in s with real coefficients. The roots of N ( s ) are the zeros of A ( s ) ; the roots of D ( s ) are the poles of A ( s ) . These roots may be real or complex; complex roots always occur in conjugate pairs. The zeros of A ( s ) may lie anywhere in the complex plane. However, the poles of A ( s ) must lie in the “left half-plane”, i.e. they must have negative real parts. If one or more poles has a real part that is greater than zero, the amplifier response is unstable, and the amplifier’s output signal will tend to become unbounded even with no apparent input signal. Of course, it is impossible for a voltage or current in a real circuit to become unbounded. A real unstable amplifier will either display some form of oscillation, i.e. it will produce an approximately periodic output signal that may appear nicely regular (e.g. sinusoidal) or highly irregular, or else it’s output will “latch up” close to the power supply voltage; in either case the behavior is essentially independent of any input signal connected. One of the most important tasks in the design of any amplifier system is to insure that it will remain stable, with all its poles in the left half-plane, under all possible operating conditions.1 Let’s look a little more closely at A ( s ) in Eqn. (3.24). Assume that A ( s ) has M zeros and N poles, all real, with neither poles nor zeros at s = 0 . Then it is possible to write A ( s ) as 1. Some circuits are designed with instability controlled in such a way as to produce periodic output signals with precisely determined frequencies and waveshapes; these circuits are called oscillators. As a historical side note, the birth of electronics has been identified by some with the realization by Edwin Armstrong that the vacuum triode circuit that was claimed by Lee Deforest to be an amplifier but that regularly emitted an unwanted howl was in fact oscillating, and Armstrong’s subsequent analysis and redesign that made the circuit useful. DRAFT 09:28 on 17 October 2006 3.5 Amplifier Gains as Transfer Functions 3-19 A ( s ) = A 0 ------------------------------------N s  1 + ---------   ω  n=1 m=1 ∏  1 + ----------  ω zm (3.25) pm M s ∏ where the zeros are at s = – ω z1, – ω z2, …, – ω zM , often called the “zero frequencies”, and the poles are at s = – ω p1, – ω p2, …, – ω pN , often called the “pole frequencies”. The usefulness of the particular factored form in Eqn. (3.25) can be seen from the following: 1. All the terms under the product operators are equal to one at s = 0 . Clearly, then A ( 0 ) = A0 (3.26) 2. If z 1 and z 2 are complex quantities, then z 1 z 2 = z 1 z 2 , and Lm ( z 1 z 2 ) = Lm ( z 1 ) + Lm ( z 2 ) . Thus using Eqn. (3.25) the magnitude of A ( jω ) is easily writen as 2  jω ω 2 1 + --------1 + ---------  2 ω zm  ω zm m=1 m=1 A ( jω ) = A 0 ---------------------------------- = A 0 --------------------------------------- ∏ N M ∏ N M 1 -- n=1 --------∏ 1 + ωpm- jω n=1 ∏  1 + ---------- 2  ω  pm N  ω 1 -2 2 (3.27) The log magnitude of A ( jω ) is also easily written as Lm ( A ( jω ) ) = Lm ( A 0 ) + or m=1 ∑ M jω Lm  1 + --------- –  ω  zm n=1 -------∑ Lm  1 + ωpn-   jω (3.28a) Lm ( A ( jω ) ) = 20log 10 A 0 + m=1 ∑ M 2  ω  10log 10  1 + --------- – 2  ω  zm n=1 ∑ N 2  ω  10log 10  1 + --------- 2  ω  zm (3.28b) 3. If z 1 and z 2 are complex quantities, then arg ( z 1 z 2 ) = arg ( z 1 ) + arg ( z 2 ) . So we have arg ( A ( jω ) ) = arg ( A 0 ) + or m=1 ∑ M jω arg  1 + --------- –  ω  zm n=1 -------∑ arg  1 + ωpn-   N jω (3.29a) DRAFT 09:28 on 17 October 2006 3-20 3 Introduction to Amplifier Circuits arg ( A ( jω ) ) = arg ( A 0 ) + m=1 ∑ M ω arctan  --------- –  ω zm n=1 -------∑ arctan  ωpn-   N ω (3.29b) and because A 0 is real, arg ( A 0 ) = 0 for A 0 > 0 and arg ( A 0 ) = ± 180° for A 0 < 0 . 4. Each term in the above relations that depends on ω actually depends on the ratio ( ω ⁄ ω o ) , where ω o is a zero or pole frequency (e.g. ω zm or ω pn ). The nature of these terms is such that jω 1 + ------ = ωo jω 2 and Lm  1 + -----  = 3.01dB;  ω o ω = ωo (3.30) jω jω 1 + ------ ≈ 1 and Lm  1 + ------ ≈ 0dB;  ωo ω o ω < 0.2ω o ω > 5ω o ω jω jω 1 + ------ ≈ ------ and Lm  1 + ------ ≈ ( 20log 10 ω – 20log 10 ω o )dB;  ωo ωo ω o and also jω arg  1 + ------ = 45°;  ω o jω arg  1 + -----  ≈ 0°;  ω  o ω = ωo ω < 0.1ω o ω > 10ω o (3.31) jω arg  1 + ------ ≈ 90°;  ω o The contributions of the individual terms can thus be assessed and combined with a minimal amount of effort. In particular, if we happen to be interested in the behavior of A ( jω ) only up to some frequency ω 1 , we can discard all the terms in Eqn. (3.25) for A ( jω ) associated with pole and zero frequencies greater than about 10ω 1 , at least to first order. Eqn. (3.25) is easily modified to includes poles and zeros occuring in complex conjugate pairs. The resulting terms that will appear in the expansions for the magnitude, log magnitude, and phase of A ( jω ) are somewhat more complicated. Relations similar to those in Eqns. (3.30) and (3.31) exist and lead to possible simplifications of A ( jω ) similar to those noted above for the all-real case; however, these must be used with greater care, especially if there are any pole-pairs or zero-pairs lying particularly close to the imaginary axis. Now, as discussed in the previous section, the responses that are of interest to us here are those for which midband extends down to ω = 0 . Such responses are often called low-pass responses. The have neither zeros nor poles at ω = 0 , and may in fact have no zeros at all (with N ( s ) = 1 in Eqn. (3.24)). Because midband extends down to ω = 0 , the gain constant A 0 in the factored form of (3.24) will also be the midband gain. A practical amplifier may have ten or more poles and several zeros. Given the values of the gain constant A 0 and the pole and zero frequencies, the magnitude, log magnitude, and phase of the gain are easily calculated at any frequency using expansions such as (3.27), (3.28b), and (3.29b). It is also possible to find the upper 3dB frequency, ω H , in this way, for example by plotting Lm ( A ( jω ) ) . In many cases, however, an amplifier will have one pole whose frequency is much smaller in magnitude than those of all the other poles and zeros. Such a pole is called a dominant pole, and its presence greatly simplifies characterization of the DRAFT 09:28 on 17 October 2006 3.6 Device Capacitances and Bandwidth Limitations 3-21 amplifier frequency response. Consider as an example the case of A ( s ) in Eqn. (3.25) with all the poles and zeros real, and assume that ω p1 < 0.2ω pn for n = 2, …, N and that ω p1 < 0.2 ω zm for m = 1, …, M . Here A ( s ) has a dominant pole at s = – ω p1 . One conclusion that is readily drawn for this case from Eqns. (3.30) is that the upper 3dB frequency is the frequency of the dominant pole, i.e. ω H = ω p1 . 3.6 Device Capacitances and Bandwidth Limitations Device capacitances are incremental capacitances. They relate a change in stored charge to a change in voltage, at a particular operating point. We are concerned here with BJT capacitances with the BJT operating in the forward-active region, and with MOSFET capacitances with the MOSFET operating in saturation. 3.6.1 BJT Capacitances Recall that in a BJT we find the following capacitances: • Collector-base depletion capacitance ( C JC ): This is the capacitance of the base-collector junction depletion region. It decreases as the reverse bias on the base-collector junction increases. • Emitter-base depletion capacitance ( C JE ): This is the capacitance of the base-emitter junction depletion region. Since the bias on the base-emitter junction remains approximately constant in the active region, this capacitance is approximately independent of the BJT operating point. • Emitter-base diffusion capacitance ( C DE ): This is the capacitance associated with the injection of minority carriers into the base from the emitter. It is directly proportional to the forward current through the junction at the operating point (i.e. to the DC collector current I C ). • Collector-substrate depletion capacitance ( C cs ): This is the capacitance associated with the depletion region of the reverse-biased junction between the collector and substrate in integrated BJTs2. Because the substrate is always connected to a fixed DC potential, this capacitance appears between collector and ground in the incremental BJT model. Because g m is also proportional to I C , we can relate C DE to g m as: C DE = g m τ b (3.32) The quantity τ b is called the base transit time in the forward direction. It can be identified as the average time per carrier spent traversing the base region, and it is essentially independent of device operating point3. Typical values for τ b are on the order of 100psec for good integrated devices. In the SPICE BJT model, τ b is called TF. The capacitances C DE and C JE both appear between base and emitter. In the hybrid-π incremental model, the net capacitance between base and emitter is called C π . Thus C π = C DE + C JE = g m τ b + C JE (3.33) In the hybrid-π incremental model, the net capacitance between base and collector is called C µ . From the discussion above, clearly 2. This capacitance is present in all npn devices, and in pnp devices in complementary bipolar technologies. In standard bipolar technologies, most pnp transistors have a “lateral” structure, with a capacitance between base and substrate instead of between collector and substrate. 3. The value of the base transit time is reduced at very high values of collector current, due to second-order effects that are often neglected in the device model. DRAFT 09:28 on 17 October 2006 3-22 3 Introduction to Amplifier Circuits Ib B Vbe rb rπ Vπ Cπ Cµ gmVπ E C ro Vce Ic Ccs Figure 3-19. The dynamic incremental hybrid-pi model for a BJT. The collector-to-substrate capacitance is shown connected to ground, because the substrate is always connected to a DC voltage source or directly to ground. C µ = C JC The dynamic incremental BJT model incorporating all these capacitances is shown in Figure 3-19. 3.6.2 (3.34) MOSFET Capacitances A MOSFET has an intrinsic capacitance associated with the gate-oxide-channel “sandwich”, as well as two kinds of parasitic capacitances. The oxide capacitance per unit area is ε ox C ox = -----t ox (3.35) – 13 where ε ox is the permittivity of the oxide dielectric ( 3.45 ×10 –2 3.45 ×10 fF/µm , for silicon dioxide) and t ox is the oxide thickness. MOSFET capacitances can be characterized as follows: F/cm , or perhaps more usefully • Intrinsic capacitance: This is the capacitance of the gate-oxide-channel “sandwich”. Analysis shows that in saturation, it contributes capacitance only between the gate and the source-end of the channel, equal to two-thirds of the total apparent capacitance of the gate area (i.e., ( 2 ⁄ 3 )WLC ox ). This capacitance is independent of operating point, so long as the device is in saturation. • Overlap capacitances: Because of imperfections in device fabrication, the gate oxide will slightly overlap the source and drain contact regions. This results in a capacitance between gate and source and a capacitance between gate and drain. These are usually specified as capacitances per unit channel width, and are independent ofoperating point. • Junction capacitances: There is a reverse-biased junction between the source contact region and the substrate, and also between the drain contact region and the substrate. The depletion regions of these junctions have associated capacitances, C sb and C db respectively. Each of these decreases as the associated junction reverse-bias increases. The net capacitance between gate and source is seen to be: 2 C gs = -- WLC ox + ( C gs ) overlap 3 while the net capacitance between gate and drain is: C gd = ( C gd ) overlap (3.37) (3.36) DRAFT 09:28 on 17 October 2006 3.6 Device Capacitances and Bandwidth Limitations 3-23 Ig G Vgs Cgs Cgd gmVgs S,B ro D Cdb Id Vds Figure 3-20. The dynamic incremental MOSFET model. The source is connected to the substrate in this model. The incremental model incorporating MOSFET capacitances, but with the source connected to the substrate, is shown in Figure 3-20. BJT Gain-Bandwidth Product Device capacitances impose an inherent upper limit on the useful range of operating frequencies for a BJT. This limit is usually quantified in terms of a parameter called the gain-bandwidth product, evaluated by considering the short-circuit common-emitter current gain, denoted by β ( jω ) as a function of frequency ω . Refer to the circuit in Figure 3-21. Since V ce = 0 in this circuit, β ( jω ) = I c ⁄ I b . Noting that the voltage across C µ is V π , again because V ce = 0 , and using the complex frequency variable s, we write two node equations: Vπ I b = ----- + sC π V π + sC µ V π ; rπ from which we obtain: C µ  g m r π  1 – s ------ g m  β ( s ) = -----------------------------------------1 + s ( C π + C µ )r π We find β ( jω ) by substituting s = jω in Eqn. (3.38). Referring to Eqn. (3.38), we note first that at zero frequency ( ω = 0 , equivalent to s = 0 ), β ( 0 ) = g m r π = β o ; this is as expected based on the definition of β o . Now, defining 1 ω β ≡ -----------------------------( C π + C µ )r π I c = g m V π – sC µ V π 3.6.3 (3.38) Ib B Vbe rb rπ Vπ Cπ Cµ gmVπ E C ro Ic Ccs Vce= 0 Figure 3-21. Calculation of short-circuit common-emitter current gain for a BJT. The emitter is connected to ground, so the collector-substrate capacitance appears between collector and emitter. DRAFT 09:28 on 17 October 2006 3-24 3 Introduction to Amplifier Circuits Lm(β) (dB) Lm(βo) ωT 0 ωβ ω (log10) Figure 3-22. Log magnitude of β versus frequency. The frequency axis is scaled logarithmically. The dashed line is a piecewise linear approximation to the single-pole low-pass characteristic. we note that β ( s ) has a single pole at s = – ω β , as well as a zero at s = + ( g m ⁄ C µ ) . Let’s assume that at frequencies ω of interest, ( ωC µ ⁄ g m ) « 1 , so that the effects of the zero can be neglected; then: gm rπ β ( jω ) ≈ ----------------ω 1 + j -----ωβ (3.39) The log magnitude of β ( jω ) , which is 20log 10 β ( jω ) (in dB), is plotted in Figure 3-22. It is clear from Eqn. (3.39) and the figure that ω β is the frequency at which the magnitude of β is 0.707β o , i.e. at which the log magnitude of β is 3dB below that of β o . It is thus the upper 3dB frequency of β, and so is effectively the bandwidth of β. Consider now the frequency at which β = 1 . This frequency, denoted by ω T , is easily found from Eqn. (3.39). Noting that we expect ω T » ω β since β o » 1 , and using the definition of ω β , we have gm ω T = ------------------Cπ + Cµ By recalling the behavior of C π and C µ from Eqns. (3.33) and (3.34) above, we find C JE + C JC 1 ------ = τ b + ------------------------ωT gm (3.41) (3.40) We can see from this that at low values of collector current ω T will increase with increasing I C . At higher values of collector current, C π (i.e., the effect of transit-time τ b ) will be much larger than the sum of the junction capacitances, and ω T will be independent of I C . At very high values of collector current, ω T will decrease with increasing I C because τ b is now decreasing with increasing I C . From its definition, ω T is the unity-gain frequency of β. It is also the product of the midband value of β (i.e. β o ) and its bandwidth ω β . For this reason, ω T is referred to as the gain-bandwidth product of the BJT. DRAFT 09:28 on 17 October 2006 3.6 Device Capacitances and Bandwidth Limitations 3-25 Values of f T = ( ω T ⁄ 2π ) are generally given on BJT data sheets, as are values of C JC . Given these quantities and the operating point, C π is easily determined using Eqn. (3.40). Finally, note that for frequencies greater than ω T , a BJT has no useful gain. Therefore, the “frequencies of interest” for operation of a BJT are those below ω T . Since in general C µ « C π , it is easily shown that ( ω T C µ ⁄ g m ) « 1 . Thus the approximation we made in going from Eqn. (3.38) to Eqn. (3.39) is clearly justified. The term that we neglect in the numerator of the right-hand side of Eqn. (3.38) will appear again when we look at the voltage gain of a common emitter stage, and we will neglect it there as well for the same reason. MOSFET Gain-Bandwidth Product The short-circuit common-source current gain of a MOSFET, i.e. I d ⁄ I g with V ds = 0 , can be found by starting with the dynamic incremental MOSFET model in Figure 3-20, and proceeding as for the BJT. Defining ω T for the MOSFET to be the frequency at which the magnitude of this gain is unity, we find gm ω T = ----------------------C gs + C gd This quantity can be viewed as a gain-bandwidth product for the MOSFET. Finally, it is interesting to note that we have considered non-zero gate current I g here in the dynamic MOSFET model, while we have had zero gate current in the static MOSFET model. This is completely consistent with the purely capacitive nature of MOSFET gate. (3.42) 3.6.4 DRAFT 09:28 on 17 October 2006 3-26 3 Introduction to Amplifier Circuits A VSO is Thevenin open-circuit voltage gain A VIL is input-to-load voltage gain A VIO is “intrinsic” open-circuit voltage gain A VSL is overall voltage gain source to load A ISS is Norton short-circuit current gain A IIL is input-to-load current gain A IIS is “intrinsic” short-circuit current gain A ISL is overall current gain G MSS is Norton short-circuit transconductance G MIL is input-to-load transconductance G MIS is “intrinsic” short-circuit transconductance G MSL is overall transconductance source to load R MSO is Thevenin open-circuit transresistance R MIL is input-to-load transresistance R MIO is “intrinsic” open-circuit transresistance R MSL is overall transresistance source to load DRAFT 09:28 on 17 October 2006 4.1 The Common-Emitter Stage at Midband 4-1 4 Single-Stage Amplifier Circuits Virtually all practical amplifier circuits are multistage amplifiers, because only rarely can a single-stage circuit meet all of the requirements placed on a design. In order to understand the analysis and design of multistage amplifiers, however, it is necessary to begin by looking at single-stage circuits. This chapter focuses on single-stage amplifier circuits in what we call canonical form. In canonical form, a stage of a particular type (for example, a common-emitter stage) can be readily identified within a complete amplifier, and its contribution to the overall amplifier performance can be evaluated by considering the stage essentially in isolation. As noted earlier, an amplifier should ideally be such that its output is a linear function of its input. For this reason, we will assume that in the amplifier circuits to be considered all BJTs are operating in the active region and all MOS transistors are operating in saturation. Incremental models will be constructed accordingly. We first present an analysis of the amplifier stages of interest at midband. In line with the discussion in Section 3.4, “midband” is equivalent to ω = 0 . We will then revisit each of these amplifier stages and evaluate their behavior at high frequencies. 4.1 The Common-Emitter Stage at Midband Figure 4-1 shows a canonical common-emitter (CE) amplifier stage and its incremental model at midband. The resistance R C in the figure is an integral part of the CE stage, providing the path for the DC collector current; except for this resistance, the biasing arrangement is ignored. Any external load resistance R L would be connected from collector to ground, essentially in parallel with R C . VCC RC RS Vs Ri Figure 4-1. Ro RS Ii Vi Ri rb rπ Vπ gmVπ ro RC Ro Vo Ii Vi Vo Vs A common-emitter stage and its incremental model at midband. Considering this stage as a voltage amplifier with no external load (i.e. with its output open-circuited), and recalling the discussion in Section 3.3.1, we will represent the stage using the equivalent circuit of Figure 3-11, shown open-circuited with the load resistance removed in Figure 4-2. The circuit equations needed to find A VSO ≡ V o ⁄ V s are: Vs = Ii ( RS + rb + rπ ) ; Vπ I i = ----- ; rπ V o = – g m R'C V π where R'C ≡ R C || r o . Note that from these equations A VSO can be expressed as DRAFT 09:28 on 17 October 2006 4-2 4 Single-Stage Amplifier Circuits RS Vs Ri Figure 4-2. Ii Vi Ro AVSOVs Vo Equivalent circuit at midband for the CE stage as a voltage amplifier. The amplifier output is open circuited, with no external load connected.  V π  V o A VSO =  -----   -----   V s   V π Clearly, then – g m R'C r π A VSO = ---------------------------RS + rb + rπ The input resistance R i as shown in Figure 4-1 satisfies R i ≡ V i ⁄ I i . To find R i , note that Vi = Ii ( rb + rπ ) so that Ri = rb + rπ (4.2) (4.1) To find R o , the independent source V s is set to zero and the output is driven by a test source. If the test source is a voltage V x and the current drawn from it is I x , as shown in Figure 4-3, then R o ≡ V x ⁄ I x . It can be seen that if V s = 0 , then V π = 0 , so R o = R'C (4.3) In many cases, R C « r o so that R'C ≈ R C , and R S » r b so that R S + r b ≈ R S . The corresponding approximate relations are –gm RC rπ A VSO = ---------------------- ; RS + rπ Ri = rπ ; Ro = RC (4.4) RS Vi rb r π Ix Vπ gmVπ ro R'o RC Ro Vx Figure 4-3. Finding the output resistance of the CE stage. DRAFT 09:28 on 17 October 2006 4.1 The Common-Emitter Stage at Midband 4-3 Note that a resistance R o is shown in Figure 4-3 looking directly into the collector of the BJT, behind ' R C and thus not including R C . This resistance represents the effective output resistance of the circuit without taking into account the collector resistor that is external to the BJT. Recall that we have taken R C to be an integral part of the circuit because it provides the path for the DC collector current to flow from the supply voltage V CC through the BJT to ground (see Figure 4-1). However, there are applications where the path for the DC collector current is actually through the load that is external to the CE stage. Perhaps the most important example of such an application is the current mirror that was discussed in Section 2.2, shown in Figure 2-10 on page 2-12. Device Q2 in that figure is in a CE connection, with a special configuration in its input circuit consisting of the diode-connected transistor Q1. In circuits of this type it is important to know the output resistance looking directly into the collector, which for the CE stage in Figure 4-1 is the resistance R o ' shown in Figure 4-3. It should be immediately evident from the figure that R o = r o ; indeed, this is precisely ' equivalent to the result for the output resistance of the simple BJT current mirror that is given in Eqn. 2.9. It should also be clear from the figure that R o = R o || R C , which is equivalent to Eqn. (4.3). ' Finally, referring again to Figure 4-3, we can conclude that the CE stage satisfies the condition stated in Section 3.3.5 for the existence of its “intrinsic” representation as a voltage amplifier, namely that V i = 0 when V s = 0 and the output is driven by a voltage source. We can draw the same conclusion by examining Eqns. (4.1) and (4.2) and observing that the effect of R S on the midband voltage gain of the CE stage can be isolated into a term of the form R i ⁄ ( R S + R i ) . It is thus possible to identify an intrinsic midband voltage gain for the CE stage that is independent of both source and load resistors, and to model the stage using the equivalent circuit shown in Figure 3-12 (redrawn with the output open-circuited in Figure 4-4). RS Vs Ri Vi Ro AVIOVi Vo Figure 4-4. Alternate midband equivalent circuit for the CE stage as a voltage amplifier. It is easily shown that A VIO ≡ V o ⁄ V i is given by – g m R'C r π A VIO = ----------------------- ≈ – g m R'C rb + rπ with the approximation on the right valid since in general r b « r π . Example 4.1 The BJT in the CE stage shown in Figure 4-1 has β F = β o = 150 , r b = 100Ω , and V A = 100 , with an operating point at I C = 1mA . Also, V CC = 12V , R S = 5kΩ , and R C = 6kΩ . Note first that the DC voltage from collector to ground is 6V, which permits approximately equal positive and negative swings of collector voltage about the operating point. This would represent a “good” operating point, according to the discussion in Section 3.2 on biasing. Now, the parameters of the incremental model at the operating point are (4.5) DRAFT 09:28 on 17 October 2006 4-4 4 Single-Stage Amplifier Circuits qI C βo VA g m = -------- = 40mA/V; r π = ----- = 3.75kΩ; r o = ------ = 100kΩ kT gm IC Using these results and the specified value of r b in Eqns. (4.1), (4.2), and (4.3), we compute A VSO = – 95.9; R i = 3.85kΩ; R o = 5.66kΩ ' and we also have R o = 100kΩ . Note that the approximate relations in Eqn. (4.4) yield A VSO ≈ – 103; R i ≈ 3.75kΩ; R o ≈ 6kΩ We can use these results to characterize the incremental behavior of the circuit in the time domain, e.g. for a real sinusoid with v s ( t ) = V s cos ω o t and the frequency ω o within the midband range of the voltage gain. The incremental output voltage will be v o ( t ) = A VSO V s cos ω o t . Let V s = 1mV . Referring to Figure 4-1, we see that v o as shown is the incremental component of v CE . Having found above that V CE = 6V in this example, we can write the total voltage v CE as v CE ( t ) = 6 – 0.0959 cos ω o t V Finally, if we choose to represent the CE stage using the equivalent circuit in Figure 4-4, we find from Eqn. (4.5) A VIO = – 221 In some sense, A VIO represents the intrinsic gain of the stage, independent of source and load resistances. The voltage gain A VSO is less than half of the intrinsic gain in this example, because of the voltage division between R S and R i . If an external load resistance were to be added to the circuit, the actual voltage gain would be reduced further because of voltage division between this load resistance and R o . 4.2 The Common-Emitter Stage with Active Load at Midband A glance at the voltage-gain relations for the CE stage, for example Eqns. (4.1) and (4.5), will show that the magnitude of the gain increases with R C . Apparently, the voltage gain can be made larger simply by increasing R C . On the other hand, consider that in the circuit of Figure 4-1 the DC collector current flows through R C . Large values of R C (say greater than 50kΩ) are usually impractical in this circuit, resulting in very small values of DC collector current (and thus of g m ), or requiring very large values of V CC . What would seem ideal here is a load in the collector circuit of the CE stage that would permit the BJT to operate at an appropriate operating point, i.e. an appropriate level of DC collector current, while maintaining a high incremental value of effective collector resistance. Recalling the discussion of BJT current sources in Section 2.2.1, we might be led to investigate the use of such a circuit as an active load for the CE stage. We consider first the circuit in Figure 4-5, with the active load consisting of a DC current source with output current I CC and finite output resistance R I . Note that from a biasing perspective, given that R I is typically large, we would tend to assume that the DC current through R I can be neglected and that the DC collector current of the BJT should be essentially equal to I CC . Then, we have the incremental model of the circuit as shown in the figure, with the BJT model parameters evaluated at I C = I CC . It is identical to the incremental model of the CE stage in Figure 4-1, with the collector resistance R C replaced by R I ; its voltage gain, input DRAFT 09:28 on 17 October 2006 4.2 The Common-Emitter Stage with Active Load at Midband 4-5 VCC ICC RI Ro RS Vs Ri Figure 4-5. Ii Vi Vo Vs RS Ii Vi Ri rb rπ Vπ gmVπ ro R'o RI Ro Vo Common emitter stage with an active load. The load here is a DC current source with finite output resistance. resistance, and output resistance are thus given by Eqns. (4.1), (4.2), and (4.3) with R C replaced by R I . Note that, since a DC current source has an incremental value of zero and a zero-valued current source is an open circuit, the I CC current source does not appear at all in the incremental model in Figure 4-5. It is instructive at this point to consider replacing the current source in Figure 4-5 with a real BJT current source. We can use a current mirror circuit similar to that in Figure 2-9. Since the output current must flow down from a positive voltage to become the collector current of an npn transistor (see Figure 4-5), the transistors in the current mirror will be pnps. The resulting circuit is shown in Figure 4-6. We call it an “almost real” CE stage with active load because the complete biasing of the current mirror is included, while some details of the biasing of the amplifying device ( Q 1 ) are not. We’ll investigate this circuit in the following example. Example 4.2 In the circuit of Figure 4-6, the npn transistor has β FN = β oN = 150 and V AN = 100 , while the pnp transistors are matched with β FP = β oP = 75 and V AP = 75 .1 For all the devices, r b = 100Ω . In addition, R S = 5kΩ and V CC = 12V . We would like Q 1 , the “driver” device in this circuit, to operate at the same DC collector current as the BJT in Example 4.1; i.e., we want I C1 = 1mA . VCC Q2 ICC Q3 RU IR RS Vs Ri Figure 4-6. An “almost real” CE stage with active load. Ro Ii Vi Q1 Vo 1. Note that the ‘N’ subscript refers to npn devices and the ‘P’ subscript refers to pnp devices. DRAFT 09:28 on 17 October 2006 4-6 4 Single-Stage Amplifier Circuits We assume, as with the circuit of Figure 4-5, that I C1 is equal to I CC , which in the circuit of Figure 4-6 is the negative of the DC collector current of Q 2 . With all transistors assumed to be operating in the active region, we have I C2 = I C3 because of the current-mirror action. Thus, we want I C3 = – I C1 = – 1mA . We would select the value of R U to satisfy this condition. From Eqn. (2.8), the DC current through R U (indicated as I R in Figure 4-6) is  V CC – ( – V BE3 ) 2 I R = – I C3  1 + --------- = 1.027mA =  ------------------------------------   RU β FP   Using the piecewise linear model (see Section 1.2.6), we have for Q 3 that ( V BE3 ) active = – 0.6V , and so we find that R U = 11.1kΩ . We should also note, of course, that there must be some bias circutry in the base circuit of Q 1 , not shown in Figure 4-6, to establish I C1 at the desired value of 1mA. We now have what we need to find the incremental model of the circuit. Note that we do not have to construct a complete incremental model involving all three devices. We already know from previous work (in Section 2.2.1) that the incremental model of the current mirror consisting of Q 2 and Q 3 in the circuit of Figure 4-6 reduces to a resistance equal to the incremental output resistance of Q 2 . In other words, the incremental model of the circuit in Figure 4-6 is shown in Figure 4-5 with R I = r o2 . The element values in the incremental model are: qI C1 β o1 V AN V AP g m1 = ---------- = 40mA/V; r π1 = -------- = 3.75kΩ; r o1 = --------- = 100kΩ; r o2 = ---------- = 75kΩ kT g m1 I C1 I C2 Obviously, the values of the model parameters for Q 1 here are the same as those for the BJT in Example 4.1, since both devices operate at a DC collector current of 1mA. Now, from Eqn. (4.1), – g m1 ( r o1 || r o2 )r π1 A VSO = ---------------------------------------------- = – 726.4 R S + r b1 + r π1 and from (4.2) and (4.3), R i = r b1 + r π1 = 3.85kΩ; R o = r o1 || r o2 = 42.9kΩ Since the circuit in Figure 4-6 is a common-emitter stage, it can be represented using the model shown in Figure 4-4, with A VIO given by Eqn. (4.5): A VIO ≈ – g m1 ( r o1 || r o2 ) = – 1714 Finally, note one particular “less than real” aspect of the circuit in Figure 4-6, namely that the DC voltage at the the output (i.e., at the junction of the collectors of Q 1 and Q 2 ) cannot be uniquely determined. The problem is that we have neglected base-width modulation in the DC analysis. Recall, however, that our focus here is on incremental behavior, with an agreement that we will reconsider biasing in detail later on. Observe now that the voltage gain of the circuit with active load in Figure 4-6 is almost an order of magnitude greater that that of the circuit with resistive load in Figure 4-1, and that this difference is a direct result of the effective R C in the former case (i.e., r o2 ) being so much larger than the R C in the latter case. DRAFT 09:28 on 17 October 2006 4.2 The Common-Emitter Stage with Active Load at Midband 4-7 Another consequence of this difference, however, is that the output resistance is also much larger in the circuit with active load. What we have computed for both circuits is the open-circuit voltage gain. With an external load R L , the gain is reduced by voltage division between R o and R L , as in Eqn. (3.10); this reduction will thus be greater for the circuit with active load. In fact, it is easy to show that for a load R L = 1kΩ , the overall voltage gain of the CE circuit in Example 4.1 is -14.4, while that of the CE circuit with active load in Example 4.2 is -16.5. In fact, the relatively high output resistance of the CE circuit with active load suggests that it might be more usefully modeled by a configuration that ideally has a high output resistance. The transconductance amplifier model discussed in Section 3.3.3, redrawn in Figure 4-7, is one such configuration. We will develop this model for the circuit in Figure 4-6 by continuing the example begun above. RS Vs Ri Figure 4-7. Model of a transconductance amplifier. The output is short-circuited to find G MSS Ii Vi GMSSVs Ro Io Example 4.2 (continued) In the configuration shown in Figure 4-7, the transconductance G MSS is the ratio of the short-circuit output current to the source voltage V s . To find G MSS , we need to consider the incremental model in Figure 4-1 with the output short-circuited; this is shown in Figure 4-8. If we compare the circuit in this figure with that in Figure 4-1, we see that the equations relating V s , V i , I i , and V π (here V π1 )are unchanged from those stated in Example 4.1. Similarly, to find R o we would remove the short circuit at the output and replace it by a test source as in Figure 4-3, so the result would be as before. So we still have (obviously), R i = r b1 + r π1 ; R o = r o1 || r o2 With the short circuit at the output, clearly I o = g m1 V π1 . Thus we have Io g m1 r π1 G MSS ≡ ----- = ---------------------------------V s R S + r b1 + r π1 Using the element values we found earlier in this example, we have G MSS = 16.95mA/V . (4.6) RS Vs Ri Figure 4-8. Ii Vι rb1 rπ1 Vπ1 gm1Vπ1 ro1 ro2 Ro Io Incremental model of the CE stage with active load. The output is short-circuited to find G MSS DRAFT 09:28 on 17 October 2006 4-8 4 Single-Stage Amplifier Circuits RS Vs Ii Vi Ri GMISVi Ro Io Figure 4-9. “Intrinsic” model for a transconductance amplifier. The output is shown short-circuited. It can be shown that, just as we found an “intrinsic” open-circuit voltage gain A VIO that is independent of the source resistance for the CE stage, we can find an “intrinsic” short-circuit transconductance G MIS for this stage that is also independent of the source resistance. Referring to Figure 4-8, g m1 r π1 Io G MIS ≡ ---- = --------------------- ≈ g m1 V i r b1 + r π1 (4.7) Apparently, the intrinsic transconductance of the CE stage is simply the transconductance of the amplifying device. In this example, G MIS = 39mA/V ≈ 40mA/V . The associated “intrinsic” transconductance-amplifier model is shown in Figure 4-9. It is important to point out that while we have changed our representation of the CE stage with active load in Figure 4-6, its performance remains the same. If we calculate the voltage gain of the circuit starting from the transconductance model, with an external 1kΩ load instead of a short circuit at the output, the result is the same as that we found earlier on page 4-7. However, using the transconductance model for this circuit does highlight two important (and related) properties of the circuit’s behavior, when it drives a load resistance R L that is much smaller than its output resistance. First, the transconductance with the load in place, denoted by G MSL in Eqn. (3.14), is approximately independent of R L ; this follows directly from Eqn. (3.14). Second, the voltage gain is approximately equal to – G MSS R L and thus proportional to R L ; this can be seen from Eqn. (3.14) together with the relationship between I o and V o that is evident in Figure 3-13. Clearly, we can use the transconductance model with the resistively loaded CE stage considered in Section 4.1. It is easy to show that the short-circuit transconductance of the resistively loaded CE stage is also given by Eqn. (4.6). In fact, there is really no qualitative difference between that circuit and the actively loaded CE stage discussed in this section, at least with respect to their incremental behavior. In the limit as the resistance in the collector circuit becomes large (which, practically speaking, is only possible with the actively loaded stage), the output resistance of the CE stage approaches R o (see Figure 4-3 and Figure 4-5), which is ' equal to the r o of the amplifying device, and the behavior of the circuit becomes closer to that of an ideal controlled current source. One can argue on this basis that the transconductance model is the most natural model for the CE stage. 4.3 The Common-Source Stage at Midband Figure 4-10 shows a canonical common-source (CS) amplifier stage and its incremental model at midband. The resistance R D in the figure is an integral part of the CS stage, providing the path for the DC drain current; except for this resistance, the biasing arrangement is ignored. Any external load resistance R L would be connected from drain to ground, essentially in parallel with R D . DRAFT 09:28 on 17 October 2006 4.3 The Common-Source Stage at Midband 4-9 VDD RD RS Vs Ri Figure 4-10. Ro RS Ii Vi Ri Vgs gmVgs ro R'o RD Ro Vo Ii Vi Vo Vs A common-source stage and its incremental model at midband. The analysis of this circuit as a voltage amplifier follows that of the common-emitter stage in Section 4.1. One significant difference is that for the common-source stage in Figure 4-10 the input current I i must be zero, so that V s = V i = V gs . Defining R' D ≡ R D || r o , it is easy to find that A VSO = – g m R' D ; Ri → ∞ ; R o = R' D (4.8) for the voltage amplifier equivalent circuit in Figure 3-11. Because R i is infinite for the CS stage, we can use the equivalent circuit in Figure 3-11 with A VIO = A VSO .. Referring back to Eqn. ,(4.5), note that the intrinsic voltage gain of the CS stage has the same form as that of the CE stage. Example 4.3 The NMOS transistor in the CS circuit in Figure 4-10 is biased at a DC drain current I D = 1mA and 2 –1 has V T = 1V , k' = 50µA/V , W = 64µ , L = 8µ , and λ = 0.02V . In the circuit shown, V DD = 12V , R S = 5kΩ , and R D = 6kΩ . First, we can find the DC gate-to-source voltage; given the device parameters and the specified I D , V GS = 1 + 5 = 3.236V The parameters of the incremental model of the MOS transistor at the operating point are k'W g m = -------- ( V GS – V T ) = 894µA/V ; L 1 r o = -------- = 50kΩ λI D It should be recalled here in passing that the value of V T need not have been specified in this example, since g m can be found from the difference ( V GS – V T ) , which is found from I D . From Eqn. (4.8), the voltage gain and output resistance are A VSO = A VO = – 4.792 ; R o = 5.357kΩ DRAFT 09:28 on 17 October 2006 4-10 4 Single-Stage Amplifier Circuits In Example 4.3, the DC drain current and drain resistor were intentionally chosen to be the same as the DC collector current and collector resistor, respectively, for the CE stage in Example 4.1. It is clear from the results in these two examples that the MOS transistor has a much lower g m than the BJT at the operating current of 1mA, so that the voltage gain of the CS stage in Example 4.3 is correspondingly much lower than that of the CE stage in Example 4.1. In fact, it is generally the case that a MOS transistor will have a much lower g m than a BJT at the same DC operating current. The difference is perhaps exaggerated in these examples, because a DC drain current of 1mA is quite high for a MOS transistor with the specified parameters; but in the process we have highlighted another aspect of the difference between the MOS transistor and the BJT, namely that the g m of a MOS transistor depends on device parameters ( k' and geometry) while that of a BJT does not. Finally, there is indicated in Figure 4-10 the “internal” output resistance R o of the CS stage, looking ' directly into the drain of the MOS transistor. As was the case for the CE stage, we have R o = r o and ' ' ' R o = R o || R D . In addition, the significance of the resistance R o here is essentially the same as for the CE stage, as discussed above on page 4-3. 4.4 The Common-Source Stage with Active Load at Midband We can replace the drain resistor R D in the CS stage in Figure 4-10 with an active load with high equivalent resistance in an attempt to increase its voltage gain, just as we did for the CE stage. In fact, we have already seen in Section 2.4 two circuits that are essentially CS stages with active loads: the MOS inverter with enhancement load in Figure 2-19, and the MOS inverter with depletion load in Figure 2-21. Recall from the discussion there that it is only the depletion load that has a high incremental resistance and thus yields a high-gain circuit. In this section, we consider using an MOS current mirror as an active load, thus avoiding the need for depletion-mode devices. The circuit is exactly analogous to the CE stage with active load that we analyzed in Section 4.2. Recalling the CE circuit in Figure 4-5, we again view the active load as a DC current source, labeled I DD for the CS case, with output resistance R I . An “almost real” CS circuit is shown in Figure 4-11, with an NMOS driver device and PMOS current mirror. For purposes of hand analysis of the circuit in Figure 4-11, we would assume that I DD is the negative of the DC drain current of M 2 , which is found with channel-length modulation neglected, and also that the DC drain current of M 1 is equal to I DD . Of course, we find R I using the incremental model of the current mirror, which takes channel-length modulation into account. Consider the following example. M3 RU IR RS Vs Ri Figure 4-11. IDD VDD M2 RI RS M1 Vi Vo Vs Ri Ii Vi Vgs gmVgs ro R'o RI Ro Vo Ii Ro An “almost real” CS stage with active load. The resistance R I indicated looking into the drain of M 2 represents the output resistance of the current mirror comprised of M 2 and M 3 . DRAFT 09:28 on 17 October 2006 4.4 The Common-Source Stage with Active Load at Midband 4-11 Example 4.4 The NMOS transistor in Figure 4-11 has the same device parameters as the device in Example 4.3. The 2 P M O S t r a n s i s t o r s a r e m a t c h e d w i t h 2 V TP = – 1V , k'P = 50µA/V , W = 64µ , L = 8µ , a n d –1 λ P = 0.02V . In addition, V DD = 12V and R S = 5kΩ . We would like the DC drain current of M 1 to be the same as in Example 4.3; i.e. I D1 = 1mA . Under the assumption stated above, we should thus have I D2 = – 1mA and so, because of the current-mirror action, I D3 = – 1mA . We would select the value of R U to satisfy this objective. From the saturation-region equation for M 3 (remembering that it is a PMOS transistor), we find that V GS3 = – ( 1 + 5 ) = – 3.236V . Since the DC current I R in R U is equal to – I D3 , we can solve for R U as V DD – ( – V GS3 ) R U = ------------------------------------- = 8.764kΩ IR The biasing circuitry needed to establish the DC gate-to-source voltage of M 1 such that I D1 = 1mA is not shown, as usual. We know from the incremental analysis of the MOS current mirror in Chapter 2 that its output resistance is equal to the incremental drain resistance of M 2 . Thus 1 R I = r o2 = ----------------- = 50kΩ λ P I D2 Since M 1 has the same device parameters and operating point as the NMOS device in Example 4.3, the values of its incremental-model parameters are equal to those in that example. The voltage gain and output resistance are found using Eqn. (4.8) with R D replaced by R I = r o2 ; thus A VSO = A VIO = – 22.36 ; Finally, we still have R i → ∞ . Now, as we did for the CE stage with active load, we can represent the CS stage in Figure 4-11 as a transconductance amplifier. The modification to its incremental model to find the short-circuit transconductance is straightforward (see Figure 4-8). We immediately find that G MSS = G MIS = g m1 (4.9) R o = 25kΩ while clearly R i and R o are the same as in the voltage-amplifier representation. Moreover, the comments regarding the CE stage as a “natural” transconductance amplifier on page 4-8 apply equally to the the CS stage. In the limit as the resistance in the drain circuit becomes large (which, practically speaking, is only possible with the actively loaded stage), the output resistance of the CS stage approaches R o (see Figure 4-10 and ' Figure 4-11), which is equal to the r o of the amplifying device, and the behavior of the circuit becomes closer to that of an ideal controlled current source. As for the CE stage, one can argue on this basis that the transconductance model is the most natural model for the CS stage. 2. We use the subscript ‘P’ to identify parameters of the PMOS transistors and the subscript ‘N’ to identify those of the NMOS device. DRAFT 09:28 on 17 October 2006 4-12 4 Single-Stage Amplifier Circuits 4.5 The Common-Collector Stage at Midband We have seen that the common-emitter stage can provide large voltage gain but has relatively large output resistance and relatively small input resistance. The common-collector stage (sometimes called an emitter follower), with the output taken from the emitter and the collector common to both input and ouptut circuits, displays behavior that is dramatically different. Figure 4-12 shows a common-collector (CC) stage and its incremental model at midband. Note that in drawing the incremental model we have placed the collector node at the bottom and the emitter node at the top, since in the CC stage the collector node is at ground potential (“common”) for incremental signals. Note also that the resistance R E in the figure is an integral part of the stage, providing the path for the DC emitter current; except for this resistance, the biasing arrangement is ignored. Any external load resistance R L would be connected from collector to ground, essentially in parallel with R E . We can think about the qualitative behavior of the CC stage by recalling that the base-emitter voltage of a BJT remains approximately constant in the active region. With the input voltage from base to ground and the output voltage from emitter to ground, we would expect these voltages to be almost equal. The output voltage, at the emitter, is said to follow the input voltage at the base (hence the term emitter follower). Now, referring to the figure, we can proceed to a quantitative analysis of the stage. We find the open-circuit voltage gain A VSO = V o ⁄ V s by writing a loop equation: Vπ V s = ----- ( R S + r b + r π ) + V o rπ and a node equation: Vo 1 ---- V π + g m V π = ------rπ R'E where R'E ≡ R E || r o , and we have used the fact that I i = V π ⁄ r π . Solving for V o in terms of V s , ( 1 + g m r π )R'E A VSO = ---------------------------------------------------------------------R S + r b + r π + ( 1 + g m r π )R'E (4.11) (4.10b) (4.10a) VCC RS Ii Ro Vi RS Vs Ri Ii B rb Vi rπ Vπ gmVπ C E Vs RE Vo ro RE Ro Vo Ri Figure 4-12. A common-collector stage and its incremental model at midband. To clarify how the incremental model has been drawn the emitter, base, and collector nodes are labeled in the figure. DRAFT 09:28 on 17 October 2006 4.5 The Common-Collector Stage at Midband 4-13 Eqn. (4.11) clearly shows that the voltage gain of the CC stage, unlike that of the CE stage, is positive and less than unity. In addition, since g m r π = β o and generally β o » 1 , we would expect that A VSO is likely to be very close to 1. The input resistance R i = V i ⁄ I i is easily found by modifying the loop equation (4.10a) so that V i rather than V s is on the left-hand side and using again the node equation (4.10b) and the relationship between I i and V π noted above. The result is R i = r b + r π + ( 1 + g m r π )R'E (4.12) To find the output resistance R o , we need to set the input signal source V s to zero and connect a test source to the output. The appropriate circuit configuration is shown in Figure 4-13, with R o = V x ⁄ I x . Again, one loop equation and one node equation, as follows: Vπ V x = – ----- ( R S + r b + r π ) ; rπ Vx Vπ I x = ------- – ----- – g m V π R'E r π will lead to the desired result (where we have again used I i = V π ⁄ r π ). It is easier to solve first for I x ⁄ V x , with 1 + gm rπ Ix 1 ----- = ------- + ---------------------------R'E R S + r b + r π Vx We can see then that R o is in fact the parallel combination of two resistances, that is:  R S + r b + r π R o = R'E ||  ----------------------------   1 + gm rπ  (4.13b) (4.13a) Before proceeding to an example, we can observe additional qualitative differences between the CC and CE stages. From Eqn. (4.12) it is clear that the input resistance of the CC stage is greater than that of the CE stage, by ( 1 + β o ) times the net resistance in the emitter circuit; thus the input resistance of the CC stage can be quite high. From Eqn. (4.13b) we see that the output resistance of the CC stage includes a component in parallel that is equal to the net resistance in the base circuit divided by ( 1 + β o ) ; thus unless R S is very large, the output resistance of the CC stage will be quite small. RS Ii B rb Vi rπ Vπ gmVπ C E Ix ro RE Vo Ro Vx Figure 4-13. Finding the output resistance of the CC stage. DRAFT 09:28 on 17 October 2006 4-14 4 Single-Stage Amplifier Circuits Example 4.5 The BJT in the CC stage in Figure 4-12 operates with I C = 1mA and has the same device parameters as the BJT considered in Example 4.1. The parameters of its incremental model are thus also the same as in Example 4.1. In addition, R S = 10kΩ and R E = 6kΩ . The following values are computed using Eqns. (4.11), (4.12), and (4.13b): A VSO = 0.984 ; R i = 858.6kΩ; R o = 91.6Ω If we consider this CC stage loaded by an external load resistance R L = 1kΩ , we can find the overall voltage gain A VSL (e.g. using Eqn. (3.11)):  RL  A VSL = A VSO  ------------------  = 0.901  R o + R L (4.14) The reduction in voltage gain resulting from the connection of this load is small (less than 10%) because the output resistance is small compared to the load resistance. Having connected a load to the circuit, we need to consider the possibility that the input resistance depends on the load (see the discussion in Section 3.3.5). Referring to Figure 4-12, the load resistance R L would be connected directly in parallel with R E and r o . Using this observation, it is easily shown that the input resistance with R L connected is given by R i = r b + r π + ( 1 + g m r π ) ( R'E || R L ) With R L = 1kΩ , the input resistance is R i = 132.2kΩ This input resistance is considerably smaller than for the open-circuited CC stage found above but is still significantly larger than for the CE stage operating with the same DC collector current that we considered in Example 4.1. Note in addition that the effect on the overall voltage gain A VSL of the reduction in input resistance when the load is connected is already accounted for in Eqn. (4.14). This example confirms that the CC stage has at least two characteristics of a good voltage amplifier, namely high input impedance and low output impedance. The fact that its voltage gain is less than one, and thus actually represents attenuation rather than amplification, may seem problematic. On the other hand, we might anticipate the benefits of using a CC stage connected somehow with a stage having large voltage gain. It should be evident from Figure 4-13 that the CC stage does not satisfy the conditions stated in Section 3.3.5 for the existence of an “intrinsic” model that is completely independent of source and load conditions. This can also be seen from the dependence of the input resistsance on the load indicated in Eqn. (4.15). This behavior is the result of feedback within the CC stage. As we shall see later on, it is this feedback that causes the input resistance to be high and the output resistance to be low, i.e. to have the characteristics of a good voltage amplifier. (4.15) DRAFT 09:28 on 17 October 2006 4.6 The Common-Drain Stage at Midband 4-15 Finally, we should note that the emitter resistor R E in the CC stage in Figure 4-12 can be (and in fact often is) replaced by a DC current source. If we call this current source I EE , then we would typically assume that the DC emitter current of the BJT in the figure is – I EE , while the emitter resistor R E is replaced in the circuit’s incremental model by the output resistance of the current source. 4.6 The Common-Drain Stage at Midband Figure 4-14 shows a common-drain (CD) stage and its incremental model at midband. This stage is analogous in many respects to the CC stage considered above. The output is taken from the source of the MOSFET, while the drain is at ground potential for incremental signals. Because the output voltage, at the source, tends to follow the input voltage, at the gate, the circuit is sometimes referred to as a source follower. The resistance in series with the source of the MOSFET is considered part of the stage, providing a path for the DC drain current to flow to ground. We call this resistance R Z to prevent confusion with R S , which is the output resistance of the voltage source V s . We write a loop equation and a node equation, similar to Eqns. (4.10a) and (4.10b) used for the CC stage, to find the open-circuit voltage gain of the circuit in Figure 4-14. The key difference is that here I i = 0 . Defining R' Z ≡ R Z || r o , we have V s = V gs + V o ; so that g m R' Z A VSO = ----------------------1 + g m R' Z (4.16) Vo ------ = g m V gs R' Z Since I i = 0 , the input resistance must be infinite. To find the output resistance, we employ a circuit configuration analogous to that shown in Figure 4-13 for the CC stage, with the following result: 1 R o =  -----  || R' Z  g m (4.17) VDD RS Ii Ro Vi RS Vs Ri Ii G Vgs Vi gmVgs D S Vs RZ Vo ro RZ Ro Vo Ri Figure 4-14. A common-drain stage and its incremental model at midband. DRAFT 09:28 on 17 October 2006 4-16 4 Single-Stage Amplifier Circuits Example 4.6 The NMOS transistor in the CD stage of Figure 4-14 operates at I D = 100µA and has V T = 1V , 2 –1 k' = 50µA/V , W = 64µ , L = 8µ , and λ = 0.02V . In addition, R S = 20kΩ and R Z = 20kΩ . The parameters of the device’s incremental model are g m = 282.3µA ⁄ V ; We have R' Z = 19.23kΩ , and A VSO = 0.845 ; Ri → ∞ ; R o = 2.99kΩ r o = 500kΩ If we consider this CD stage driving a load resistance of 1kΩ, as for the CC stage in Example 4.5, we find that:  RL  A VSL = A VSO  ------------------  = 0.212  R o + R L The loaded voltage gain of this CD stage is much smaller than that of the CC stage in Example 4.5, primarily because the output resistance of this CD stage is much larger than that of the CC stage in Example 4.5. This is another reflection of the much smaller transconductance of MOS transistors. 4.7 The Degenerated Common-Emitter Stage at Midband In Section 3.2.1, we noted that a resistor in series with the emitter of a common-emitter circuit stabilizes the circuit’s operating point, and we also pointed out that when used for this purpose the resistor is bypassed with a large capacitor so as not to reduce the circuit’s midband gain. A CE stage with emitter resistance bypassed in this way behaves at midband like the ordinary CE stage considered above in Section 4.1. We consider here how the CE stage behaves if it includes an emitter resistance that is unbypassed, as in Figure 4-15. Indeed, the single difference between the circuit in this figure and the CE stage in Figure 4-1 is that here we have a resistor R E connected between the emitter and ground. At the same time, the presence of this resistor introduces a similarity with the CC stage in Figure 4-12, namely that the input voltage V i from base to ground appears across the base-emitter junction of the BJT in series with a resistor in which the BJT’s emitter current VCC RC RS Ii Vo Vi RE Vs Ri RS Ii B Ro ro rb Vi Vπ rπ E C Vs Ve RE gmVπ R'o RC Ro Vo Ri Figure 4-15. A degenerated CE stage, and its incremental model at midband. The circuit is shown with its output open-circuited. DRAFT 09:28 on 17 October 2006 4.7 The Degenerated Common-Emitter Stage at Midband 4-17 flows. Following the qualitative discussion of the CC stage on page 4-12, we observe that the voltage across this resistor will remain approximately equal to V i . As a result the collector current will be approximately equal to V i ⁄ R E , and the output voltage V o will be approximately equal to – V i R C ⁄ R E . In other words, the short-circuit transconductance relative to the voltage at the base will be approximately equal to 1 ⁄ R E , while the open-circuit voltage gain, also relative to the voltage at the base, will be approcimately equal to – R C ⁄ R E . Both these quantities are thus approximately independent of the BJT device parameters, depending only on the values of the collector and emitter resistors. This useful property is a consequence of negative feedback in the circuit, as outlined on page 3-7 in Section 3.2.1. Because negative feedback is sometimes referred to as degeneration, we call the circuit in Figure 4-15 a degenerated CE stage. In Figure 4-15, the incremental model is shown with the output of the stage open-circuited. Earlier, on page 4-8, we noted that a CE stage is most naturally modeled as a transconductance amplifier. We will proceed here directly to an analysis of of the CE stage with unbypassed R E as a transconductance amplifier. To this end, Figure 4-16 shows the incremental model of the stage with the output short-circuited, so that the short-circuit transconductance G MSS = I o ⁄ V s can be found. The analysis is straightforward once we realize that, with the output short-circuited, the voltage across r o is V e and there is no current through R C . We write a loop equation and two node equations, as follows: Vπ V s = ----- ( R S + r b + r π ) + V e ; rπ Ve Ve Vπ ------ = ----- + g m V π – ----- ; RE rπ ro Ve I o = g m V π – ----r o With some algebra we solve these equations to find the short-circuit transconductance g m r π – R E( 1 + g m r π )g o ' gm rπ G MSS = ---------------------------------------------------------------------- ≈ -------------------------------------------------------------------R S + r b + r π + R E( 1 + g m r π ) R S + r b + r π + R E ( 1 + g m r π ) ' (4.18a) where R' = R E || r o and g o = 1 ⁄ r o . The approximation on the right in Eqn. (4.18a) is valid when R E « r o , E which is the usual case. Moreover, if g m r π » 1 and g m r π R E » R S + r b + r π , then we have the further approximation: 1 G MSS ≈ -----RE which is consistent with the qualitative result discussed above. By setting V s to zero in Figure 4-16 and driving the output, we can find the output resistance. Actually, it is easier to find R o and then use the fact that R o = R o || R C to find R o . Setting V s to zero in the incremen' ' tal model in Figure 4-15 and connecting a test current source I x between collector and ground, as in Figure 4-17, we have R o as V x ⁄ I x . Writing the appropriate circuit equations here becomes easier when we ' ro (4.18b) RS Vs Ri Figure 4-16. Ii B rb Vi Vπ rπ E C Io Ve RE gmVπ R'o RC Ro Incremental model for the degenerated CE stage to find the short-circuit transconductance. DRAFT 09:28 on 17 October 2006 4-18 4 Single-Stage Amplifier Circuits notice that the current entering the emitter node (‘E’ in the figure) from the right is equal to I x , and that the net voltage across the resistors r π , r b , and R S in series is equal to V e . We then have the following: Ix = gm Vπ + go ( Vx – Ve ) With a little algebra we obtain g m r π R E + g o R E ( R S + r b + r π ) gm rπ RE    ' R o = r o  1 + ------------------------------------------------------------------------  ≈ r o  1 + -----------------------------------------  R E + R S + r b + r π RE + RS + rb + rπ    (4.19) 1 1 I x = V e  ------ + ----------------------------  R  E RS + rb + rπ rπ   V π = – V e  ----------------------------   R S + r b + r π The approximation on the right of Eqn. (4.19) is valid if g m r π r o » R S + r b + r π ; this condition is almost invariably satisfied. Note that R o > r o here, while for the ordinary CE stage (with R E = 0 ) we had R o = r o . Thus, in the ' ' limit as the external resistance in the collector circuit becomes large, the CE stage with non-zero R E will have a higher output resistance (perhaps significantly so), and so will act more like an ideal current source, than the CE stage with R E = 0 . This is another consequence of the negative feedback associated with the presence of non-zero R E in the circuit. Also, since R o is so large, we can usually write that ' Ro ≈ RC (4.20) We can find the open-circuit voltage gain of the circuit in Figure 4-15, thereby representing it as a voltage amplifier, by converting from a Norton equivalent circuit to a Thevenin equivalent circuit at the stage’s output. Thus A VSO = – G MSS R o , or –gm RC rπ A VSO = -------------------------------------------------------------------RS + rb + rπ + RE ( 1 + gm rπ ) (4.21a) assuming that R E « r o . If in addition g m r π » 1 and g m r π R E » R S + r b + r π , then we have the approximation RC A VSO ≈ – -----RE (4.21b) ro RS Ii B rb Vi Vπ rπ E Ve RE gmVπ C Vx R'o Ix Figure 4-17. Finding the output resistance of the CE stage with emitter resistance. DRAFT 09:28 on 17 October 2006 4.8 The Degenerated Common-Source Stage at Midband 4-19 Note that the voltage gain is independent of device parameters, but that this useful property is achieved at the expense of a reduction in gain magnitude compared to the CE stage with R E = 0 . To find the input resistance R i = V i ⁄ I i , we return to Figure 4-15. However, we cannot assume that the output is short-circuited. The complexity of the circuit is such that the appropriate circuit equations are not easily written and solved. Rather, some methodology for writing and solving circuit equations, for example an approach based on the use of node equations, is really necessary. In any event, it can be shown that ( 1 + g m r π )R E + g o R E R C R i = r b + r π + ----------------------------------------------------------1 + g (R + R ) o E C (4.22a) Here the input resistance depends on R C . Since any external load resistance would appear in parallel with R C , the input resistance will change with the load resistance. However, since the conductance g o is small, Eqn. (4.22a) can generally be approximated as Ri = rb + rπ + RE ( 1 + gm rπ ) (4.22b) The dependence on R C and thus on the load does not appear in this approximation. Note also that this result is identical to the expression for the input resistance of the CC stage in Eqn. (4.12). As for the CC stage, the input resistance of the CE stage with nonzero R E may be significantly greater than that of an ordinary CE stage. Example 4.7 The CE stage in Example 4.1 is modified by the addition of R E = 500Ω . From Eqn. (4.18a), we have for the short-circuit transconductance G MSS = 1.78mA/V , while the approximation in Eqn. (4.18b) yields G MSS ≈ 2.0mA/V . By contrast, the value for the circuit in Example 4.1 is 16.9mA/V. Similarly, the open-circuit voltage gain here, from Eqn. (4.21a), is A VSO = – 10.67 , while the approximation in Eqn. (4.21b) yields A VSO ≈ – 12 , and the value in Example 4.1 was – 95.9 . ' From Eqn. (4.19), we find that R o = 902kΩ , a value significantly higher than r o , while R o = 5.96kΩ . With no external load resitance, we have R i = 74.8kΩ from Eqn. (4.22a); the approximation in Eqn. (4.22b) yields R i = 79.4kΩ . By contrast, the input resistance for the circuit in Example 4.1 was 3.85kΩ . The extent to which the gain has been made independent of device parameters by the presence of R E in this example can be seen by considering a reduction in β o from 150 to 75. In the circuit without R E in Example 4.1, this reduces the magnitude of the open-circuit voltage gain from 95.9 to 64.5. Here, the magnitude of the open-circuit voltage gain is reduced from 10.7 to 10.0. Similarly, we can see the effect of the increased input resistance by considering an increase in the source resistance from 5kΩ to 10kΩ. In Example 4.1, this reduces the magnitude of the open-circuit voltage gain from 95.9 to 65.0, while here the magnitude of A VSO is reduced from 10.7 to 10.1 4.8 The Degenerated Common-Source Stage at Midband The MOS equivalent of the circuit in Figure 4-15 is the degenerated CS stage, shown in Figure 4-18, with a resistance R Z in series with the source of the MOS transistor. We should expect the behavior of this DRAFT 09:28 on 17 October 2006 4-20 4 Single-Stage Amplifier Circuits circuit to be analogous to that of the degenerated stage, i.e. that its short-circuit transconductance and open-circuit voltage gain can be approximately independent of the device parameters. Because I i = 0 for the MOS transistor, the equations for the circuit in Figure 4-18 are simpler than for the BJT circuit in Figure 4-15. By connecting a short circuit across the output as in Figure 4-16, it is easily shown that the short-circuit transconductance for the degenerated CS stage is gm gm G MSS = --------------------------------------- ≈ ---------------------1 + ( g m + g o )R Z 1 + g m R Z where the approximation on the right holds if g m » g o . If, in addition, g m R Z » 1 , then 1 G MSS ≈ ----RZ This is essentially the same as the result obtained above for the degenerated CE stage. that ' The resistance R o can be found by setting V s = 0 and driving the output as in Figure 4-17. We find ' R o = r o [ 1 + ( g m + g o )R Z ] ≈ r o ( 1 + g m R Z ) (4.24) (4.23b) (4.23a) where the approximation on the right again holds if g m » g o . As for the degenerated CE stage, we have ' R o > r o ; in other words, the negative feedback provided by R Z increases the intrinsic output resistance of the stage. We also have that R o = R o || R D ≈ R D ' (4.25) With A VSO = – G MSS R o and using the approximations in Eqns. (4.23a) and (4.25), we find that the open-circuit voltage gain is –gm RD RD A VSO = ---------------------- ≈ – -----1 + gm RZ RZ VDD RD RS Vs Ii Vo Vi RZ Vs Ri RS Ii G (4.26) Ro ro Vgs Vi S D RZ Vz gmVπ R'o RD Ro Vo Ri Figure 4-18. A degenerated CS stage, and its incremental model at midband. The circuit is shown with its output open-circuited. DRAFT 09:28 on 17 October 2006 4.9 The Common-Base and Common-Gate Stages at Midband 4-21 ro VCC RC Ii E C Io Ii Is RS Ri Figure 4-19. Io Is RS Vi Vπ r π rb B gmVπ RC Vi Ro Ri R'o Ro The common-base stage and its incremental model at midband. The output is shown short-circuited. where the approximation on the right holds for g m R Z » 1 . Finally, because I i = 0 , the input resistance R i is infinite. We could at this point reconsider the CS stage in Example 4.3 by adding a non-zero resistance R Z . The exercise would be of limited interest, however. The usefulness of the degenerated CS stage as considered here is limited by the impracticality of building resistors of appropriate values for R Z in integrated MOS technologies. 4.9 The Common-Base and Common-Gate Stages at Midband Figure 4-19 shows a common-base stage and its incremental model at midband. As its name implies, the base terminal is “common”, with the input at the emitter and the output at the collector. We show a current source in the figure as the signal source driving the amplifier, and we will model the circuit as a current amplifier using the equivalent circuit in Figure 4-20. The reason for starting the analysis of the CB stage with this approach can be drawn, with a little thought, from the qualitative behavior of circuits we have already studied. We have remarked several times that when we take the output from the collector of a BJT, the equivalent output resistance R o (behind R C ) is high. Referring to Figure 4-19, we notice that the ' input resistance of the CB stage is looking into the emitter of the BJT. We had occasion to find the equivalent resistance looking into the emitter of a BJT when we found the output resistance of the CC stage in Section 4.5, using the circuit in Figure 4-13. The circuit seen looking into the emitter in Figure 4-19 is not identical to that seen looking into the emitter in Figure 4-13, but we might hypothesize that the equivalent resistances in these two cases would be qualitatively similar. We found that the output resistance of the CC stage is small and would therefore suggest that the input resistance of the CB stage should be small. An amplifier with a small input resistance and high output resistance is best represented as a current amplifier, as discussed in Section 3.3.2. Ii Is RS Ri Figure 4-20. Equivalent circuit of a current amplifier. The output is short-circuited to find AISS. Io AISSIs Ro Vi DRAFT 09:28 on 17 October 2006 4-22 4 Single-Stage Amplifier Circuits Practical applications of the CB stage are limited. The most common is as a current buffer connected to the output of a CE stage; this particular two-stage combination is so useful, however, that is has a special name (“cascode”). Analysis of the circuit in Figure 4-19 yields for the short-circuit current gain: gm rπ + go ( rπ + rb ) gm rπ A ISS = – ------------------------------------------------------------------------- ≈ – -------------------1 + gm rπ + ( go + GS ) ( rπ + rb ) 1 + gm rπ (4.27) where g o = 1 ⁄ r o and G S = 1 ⁄ R S as usual, and the approximation is valid so long as R S » ( 1 ⁄ g m ) . Note that A ISS is slightly less than one in magnitude; in fact, it is essentially equal to – α F . The output resistance ' R o can be shown to be g m r π R S + g o R S ( r b + r π ) gm rπ RS    ' R o = r o  1 + ----------------------------------------------------------  ≈ r o  1 + ----------------------------  RS + rb + rπ R S + r b + r π    (4.28a) where the approximation is always valid because g m » g o . Note that if in addition R S » r b + r π we have the further approximation ' Ro ≈ ro ( 1 + gm rπ ) (4.28b) In other words, the intrinsic output resistance R o of the CB stage can be as high as ( 1 + β o )r o . The output ' resistance taking R C into account is R o = R o || R C ≈ R C ' (4.29) In finding the input resistance R i , we need to consider the possibility that there will be dependence on the load conditions, i.e. on R C and on any external load resistance R L connected in parallel with R C . Defining R C ≡ R C || R L , it can be shown that R i can be written as the parallel combination of three components: ' ( r π + r b ) ( 1 + g o R C) ' R i = ( r o + R C) || ( r π + r b ) || ------------------------------------------------' gm rπ In many cases, R C « r o , which allows Eqn. (4.30a) to be approximated as ' rπ + rb R i ≈ -------------------1 + gm rπ (4.30b) (4.30a) The input resistance is indeed small, as we anticipated at the outset. The result in Eqn. (4.30b) is similar to that for the output resistance of the CC stage in Eqn. (4.13b), and is also essentially identical to that for the equivalent incremental resistance of the diode-connected BJT (see Eqn. (2.4b) in Sec. 2.1.1). The common-gate MOS stage is qualitatively similar to the CB stage in its performance and also in its application. The common-gate MOS stage and its incremental model are shown in Figure 4-21. Its short-circuit current gain can be found to be: DRAFT 09:28 on 17 October 2006 4.10 The Differential Pair at Midband 4-23 VDD IDD Ii Is RS Ri Figure 4-21. ro Io S D Io Vo Ro RL Vi Ro Vo RL Is RS Ri Vgs G gmVgs A common-gate stage and its incremental model. Io A ISS ≡ --Is RL = 0  RS ( gm + go )  = –  ---------------------------------------  1 + R S ( g m + g o ) (4.31a) where g o = 1 ⁄ r o . Since it is often the case that g m » g o , we have as a useful approximation:  gm RS  A ISS = –  ----------------------  1 + g m R S We can find the output resistance to be: Ro = RS + ro ( 1 + gm RS ) while the input resistance may be found to be: ro + RL R i = -------------------1 + gm ro (4.33) (4.32) (4.31b) Note that the input resistance depends on the external load resistance R L , while the output resistance depends on the resistance R S of the source driving the input of the stage. Note further that the output resistance R o is larger than r o , and in fact may be many times larger if the source driving the input of the stage is a reasonably good current source (i.e. if R S is relatively large). 4.10 The Differential Pair at Midband The last of the canonical single-stage amplifiers that we will look at here is the differential pair. It may seem odd to consider a circuit with as many as six transistors to be a single stage. However, as we will see, this identification is appropriate and worthwhile. We have already investigated the differential pair twice. In Section 2.5 we developed nonlinear models for the BJT and MOS circuits, and in Section 3.2.2 we used the BJT differential pair as an example of how an operating point is established in an integrated-circuit amplifier stage. Here, we will consider the incremental analysis of the differential pair. We will be able to take the biasing into account in this analysis, and thus investigate complete circuits, because as we saw in Section 3.2.2 the biasing of the differential pair can be so simple. DRAFT 09:28 on 17 October 2006 4-24 4 Single-Stage Amplifier Circuits A key component in the biasing of the differential pair is the DC current source that provides the total emitter current (for the BJT circuit) or the total drain current (for the MOS circuit) of the two devices in the pair. We will now show these DC current sources as having an incremental output resistance. Recall that we already know how to design simple versions of such current sources, and we also know how to find their incremental output resistances. 4.10.1 The BJT Differential Pair with Resistive Load Figure 4-22 shows a BJT differential pair. As usual, the devices Q1 and Q2 are matched. Included in the figure are the series resistances associated with the input voltage sources v S1 and v S2 , assumed to be equal and labeled as R S . Also included is the incremental output resistance R I of the I EE current source. One benefit of the incremental analysis is that it allows us to evaluate the effects of these resistances with relative ease. Before proceeding, we define differential-mode and common-mode voltages and currents, as we did in Section 2.5.3 We have total-differential mode quantities: v SDM ≡ v S1 – v S2 ; v CDM ≡ v C1 – v C2 ; v IDM ≡ v I1 – v I2 ; i CDM ≡ i C1 – i C2 (4.34) and total common-mode quantities: 1 v SCM ≡ -- ( v S1 + v S2 ); 2 1 v CCM ≡ -- ( v C1 + v C2 ); 2 1 v IDM ≡ -- ( v I1 + v I2 ); 2 1 i CDM ≡ -- ( i C1 + i C2 ) 2 (4.35) Note that these equations represent linear transformations between pairs of voltages and currents in the circuit of Figure 4-22 and the corresponding differential-mode and common-mode voltages and currents. The transformations are easily invertible; for example, given values for v SDM and v SCM it is easy to find the correVCC RC RC vC1 iC1 vC2 iC2 RS vS1 vI1 Q1 Q2 vI2 RS vS2 IEE RI -VEE Figure 4-22. A BJT differential pair with resistive load. 3. Note that the definition of common-mode quantities is slightly different than in the earlier discussion in Section 2.5. The definition used here is consistent with common practice. DRAFT 09:28 on 17 October 2006 4.10 The Differential Pair at Midband 4-25 sponding values for v S1 and v S2 . Note also that the same transformations can be applied to incremental quantities and similarly to the complex amplitudes of incremental quantities; for example: v sdm ≡ v s1 – v s2 ; V sdm ≡ V s1 – V s2 ; 1 v scm ≡ -- ( v s1 + v s2 ) 2 1 V scm ≡ -- ( V s1 + V s2 ) 2 We need to define the operating point at which the incremental model will be constructed. In Section 3.2.2, we took the DC values of the input voltage sources to be zero; i.e. we had V S1 = V S2 = 0 , so that v S1 = v s1 and v S2 = v s2 . The operating was then found under the assumption that the I EE current source had infinite output resistance. In Figure 4-22, we show a finite incremental output resistance for this current source. However, we will assume that this resistance is so large that the DC current through it is negligible compared to I EE ; in other words, we will take the resistance R I into account only for the incremental analysis.4 We then have the result given in Eqn. (3.8), namely: α F I EE I C1 = I C2 = --------------2 (4.36) Since the devices are matched and are operating with equal DC collector currents, it is easy to find the parameter values for their incremental models: qα F I EE g m = g m1 = g m2 = ------------------ ; 2kT βo r π = r π1 = r π2 = ----- ; gm 2V A r o = r o1 = r o2 = --------------α F I EE (4.37) and r b = r b1 = r b2 . The incremental model for the differential pair is shown in Figure 4-23, under the assumption that V A → ∞ so that r o → ∞ . This assumption greatly simplifies the circuit analysis, and gives reasonably accurate results for most quantities of interest. Note that we make this assumption only for the devices in the differential pair. We would not make this assumption for devices used in a real implementation of the I EE current source, for example, since this would yield an infinite value for R I and would thus hide the effect a finite R I has on the performance of the differential pair. B1 Ii1 rb rπ RI Ve E1,E2 Vs1 RS Vi1 Vπ 1 gmVπ1 C1 Vc1 RC Vc2 RC C2 Vs2 Vi2 RS B2 gmVπ2 rπ Vπ 2 rb Ii2 Figure 4-23. Incremental model for the BJT differential pair with resistive loads. The model shown here assumes that the Early voltage for the devices is infinite. 4. Note that this is the same approximation that we have made in the analysis of current sources in Section 2.2 and in that of CE and CS stages with active loads in Sections 4.2 and 4.4. DRAFT 09:28 on 17 October 2006 4-26 4 Single-Stage Amplifier Circuits The differential pair in Figures 4-22 and 4-23 is a circuit with two inputs ( V s1 and V s2 ) and two outputs ( V c1 and V c2 ). We could characterize incremental performance of the differential pair by defining voltage gains from each of the two inputs to each of the two outputs. However, we expect based on what we already know that the behavior of the circuit is most interesting for the equivalent differential input V sdm and the equivalent common-mode input V scm . We therefore characterize the circuit by gains relative to differential and common-mode input voltages, as follows: V cdm A dds ≡ ----------V sdm V ccm A ccs ≡ ----------V scm V ccm A cds ≡ ----------V sdm V cdm A dcs ≡ ----------V scm (4.38) V sdm = 0 V scm = 0 V sdm = 0 V scm = 0 A dds is the ratio of the differential output voltage to the differential source voltage, when the common-mode source voltage is zero; it is referred to as the differential-mode voltage gain. Similarly, A ccs is the ratio of the common-mode output voltage to the common-mode source voltage when the differential source voltage is zero; it is referred to as the common-mode voltage gain. The two cross gain terms A cds and A dcs are also defined. Using superposition, we can write V cdm = A dds V sdm + A dcs V scm V ccm = A ccs V scm + A cds V sdm (4.39) and recall that we can find V c1 and V c2 from V cdm and V ccm by inverting the linear transformation similar to that in Eqn. (4.35). Referring to Figure 4-23, we write the loop equations for the Q1 input loop and for the Q2 input loop: V π1 V s1 = -------- ( R S + r b + r π ) + V e ; rπ V π2 V s2 = -------- ( R S + r b + r π ) + V e rπ (4.40) where we have used V π1 = I i1 r π and V π2 = I i2 r π . We also have a node equation at the junction of the two emitters: Ve 1 ----- = ( V π1 + V π2 )  g m + ----   r π RI Finally, we have the following for the output voltages: V c1 = – g m R C V π1 V c2 = – g m R C V π2 (4.42) (4.41) To find A dds and A cds , we arrange V s1 and V s2 so that V scm = 0 ; i.e., take V s1 = – V s2 so that V sdm = 2V s1 . Substituting this condition into Eqns. (4.40) and adding the resulting equations, we can find V e in terms of V π1 and V π2 . Substitution for V e in the node equation (4.41) yields: 1 RS + rb + rπ ( V π1 + V π2 ) g m + ---- + ---------------------------- = 0 2r R r π π I Since the quantity in brackets is strictly positive, the solution of this equation must be: V π1 + V π2 = 0 or equivalently V π1 = – V π2 DRAFT 09:28 on 17 October 2006 4.10 The Differential Pair at Midband 4-27 so that V e = 0 and V c1 = – V c2 . Using the input loop equations again together with Eqn. (4.42) for the output voltages, we obtain for the differential-mode gain: –gm rπ RC A dds = ---------------------------RS + rb + rπ and in addition A cds = 0 . To find A ccs and A dcs , we arrange V s1 and V s2 and so that V sdm = 0 ; i.e., take V s1 = V s2 so that V scm = V s1 . Substituting this condition into Eqns. (4.40) and subtracting the resulting equations, we find that we must have: V π1 – V π2 = 0 or equivalently V π1 = V π2 (4.43) so that in addition V c1 = V c2 . Substitution of this result into Eqn. (4.41) gives an equation for V e in terms of V π1 , which, together with the input loop equations, then yields for the common-mode gain: –gm rπ RC A ccs = ---------------------------------------------------------------------R S + r b + r π + 2R I ( 1 + g m r π ) and in addition A dcs = 0 . We note from Eqn. (4.44) that as R I becomes infinitely large, the common-mode gain goes to zero. This is consistent with the nonlinear analysis, in which R I was assumed to be infinite and for which we found that the circuit responds only to differential-mode inputs (i.e. that the common-mode response is effectively zero). Clearly, the smaller the common-mode gain compared to the differential gain, the more “perfect” the operation of the differential pair. The common-mode rejection ratio, or CMRR, defined to be A dds CMRR ≡ ---------A ccs RS → 0 (4.45) (4.44) is a commonly used figure of merit for differential amplifiers. Using Eqns. (4.43) and (4.44), and noting that g m r π » 1 , it is easily shown that CMRR ≈ 1 + 2g m R I (4.46) Generally, the output of the circuit in Figure 4-22 is taken from one collector or the other, i.e. as V c1 or V c2 , rather than as V cdm , which is the differential voltage between the two collectors. Gain quantities such as A 1ds ≡ ( V c1 ⁄ V sdm ) and A 1cs ≡ ( V c1 ⁄ V scm ) are therefore of interest. By inverting the linear transformation (see Eqn. (4.35), for example), we have 1 V c1 = -- V cdm + V ccm 2 so that 1 V c2 = – -- V cdm + V ccm 2 DRAFT 09:28 on 17 October 2006 4-28 4 Single-Stage Amplifier Circuits V c1 A 1ds ≡ ----------V sdm V scm = 0 1 = -- A dds 2 V c1 A 1cs ≡ ----------V scm = A ccs V sdm = 0 Use of superposition then leads to the following result for V c1 : 1 V c1 = -- A dds V sdm + A ccs V scm 2 with a corresponding result for V c2 . We consider the input resistance of the differential pair also in terms of differential and common-mode quantities. In particular, we define the differential input resistance R id and the common-mode input resistance R ic as: V idm R id ≡ ----------- ; I idm V icm R ic ≡ ---------I icm (4.48) (4.47) Referring to Figure 4-23 and the loop and node equations above, we find R id = r b + r π ; R ic = r b + r π + 2R I ( 1 + g m r π ) (4.49) It is also possible to consider the output resistance of the differential pair, actually in terms of a differential-mode output resistance and a common-mode output resistance. With these, the results in Eqn. (4.48) for input resistance, and the results in Eqns. (4.39), (4.43), and (4.44), we can construct differental-mode and common-mode voltage-amplifier models for the differential pair. Because in many practical circuits the output is taken from either one collector or the other, as was already noted above in connection with Eqn. (4.47), we wind up with load conditions that are not balanced, i.e. not symmetric at the two collectors. It is possible to use the separate differential-mode and common-mode voltage-amplifier models to analyze circuits with arbitrary load conditions. At this point, for the circuit in Figure 4-22, it is worth making a few key observations. If we compare Eqns. (4.43), (4.44), and (4.49) to the equations for the gain and input resistance of BJT amplifier stages, we are led to suggest the following: • The differential-mode gain of the circuit in Figure 4-22 is equal to the voltage gain of the ordinary common-emitter stage with the same source resistance and collector resistance and a dc collector current equal to that in either BJT in the differential pair (see Figure 4-24(a)). The differential input resistance of the circuit in Figure 4-22 is equal to the input resistance of this ordinary common-emitter stage. In other words, for differential signals, the differential pair acts exactly like an ordinary common-emitter stage. • The common-mode gain of the circuit in Figure 4-22 is equal to the voltage gain of the ordinary common-emitter stage with the same source resistance and collector resistance, an emitter resistance equal to 2R I , and a dc collector current equal to that in either BJT in the differential pair (see Figure 4-24(b)). The common-mode input resistance of the differential pair is equal to the input resistance of this common-emitter stage with emitter resistance of 2R I . In other words, for common-mode signals, the differential pair acts exactly like an ordinary common-emitter stage with emitter resistance 2RI. DRAFT 09:28 on 17 October 2006 4.10 The Differential Pair at Midband 4-29 VCC VCC RC RS Vsdm Rid Figure 4-24. RC RS Iicm Vocm Vicm 2RI Iidm Vidm Vodm Vscm (a) Ric (b) “Half-circuit” equivalents for the BJT differential pair with resistive load. (a) differential-mode; mon-mode. (b) com- These observations lead to the equivalent circuits shown in Figure 4-24, called differential-mode and common-mode half-circuits. The differential-mode half-circuit is an ordinary CE stage that is equivalent to the differential-pair for differential signals; the common-mode half-circuit is a degenerated CE stage that is equivalent to the differential pair for common-mode signals. It is possible to derive the equivalences between the differential pair and the two half-circuits solely from the symmetric structure of the differential pair circuit. Given these equivalences, we can develop all the results we need for the differential pair from results we already have for different forms of the CE circuit. For example, it should now be possible to go back and obtain results with finite values of V A and r o . The use of so-called half-circuit equivalents for the analysis of differential-pair circuits is a very powerful and general technique. It can provide a unified approach to dealing with a wide variety of circuits in which the “differential pair” becomes a fairly complicated configuration consisting of several symmetric stages, and in which the source and load conditions can be arbitrary and in particular without symmetry. Unfortunately, like most powerful and general techniques, a fair amount of groundwork is necessary to make it understandable and useful. As a result, it is beyond the scope of the present discussion. 4.10.2 The MOS Differential Pair with Resistive Load Figure 4-25 shows an NMOS differential pair with resistive loads. The analysis of the MOS differential pair follows that of the BJT circuit. The operating point is found with v S1 = v S2 = 0 and assuming that the DC current through R I is negligible. The result is that 1 I D1 = I D2 = -- I SS 2 (4.50) With the devices matched and the DC drain currents equal, the parameters of the incremental model at the operating point are k'W g m = g m1 = g m2 = -------- V GS – V T ; L where V GS – V T = ( I SS L ) ⁄ ( k'W ) . 2 r o = r o1 = r o2 = ---------λI SS (4.51) DRAFT 09:28 on 17 October 2006 4-30 4 Single-Stage Amplifier Circuits VDD RD RD vD1 iD1 vD2 iD2 RS vS1 vI1 M1 M2 vI2 RS vS2 ISS RI –VSS Figure 4-25. An MOS differential pair with resistive load. The incremental analysis of this circuit follows exactly that of the BJT circuit in Section 4.10.1. For purposes of this analysis, we will assume that λ = 0 for M1 and M2, so that r o → ∞ . The incremental model of the circuit is shown in Figure 4-26. The loop equations at the input, corresponding to Eqns. (4.40), are: V s1 = V gs1 + V z V s2 = V gs2 + V z (4.52) and the node equation at the junction of the sources of the two devices, corresponding to Eqn. (4.41), is: V ----z = g m ( V gs1 + V gs2 ) RI (4.53) G1 Ii1 D1 Vs1 RS Vi1 RI Vz Vgs1 S1,S2 gmVgs1 Vd1 RD Vd2 RD D2 Vs2 Vi2 RS G2 Vgs2 gmVgs2 Ii2 Figure 4-26. Incremental model of the MOS differential pair with resistive load. DRAFT 09:28 on 17 October 2006 4.10 The Differential Pair at Midband 4-31 and for the output voltages we have V d1 = – g m R D V gs1 and V d2 = – g m R D V gs2 . These lead to the following results: V ddm A dds ≡ ------------ = – g m R D ; V sdm V dcm –gm RD A ccs ≡ ----------- ≈ -----------------------V scm 1 + 2g m R I (4.54) where the differential-mode and common-mode output voltages are V ddm and V dcm , respectively, and are defined in the usual way. In addition, the differential-mode and common-mode input resistances, defined as in Eqns. (4.48), are both infinite for this circuit. The common-mode rejection ratio (CMRR) is exactly as in Eqn. (4.46). Finally, voltage gains to one or the other of the two drains, i.e. to V d1 or V d2 can also be found by following the discussion immediately preceding Eqns. (4.47). 4.10.3 The BJT Differential Pair with Active Load In the differential-pair circuits discussed above, the output is taken as the voltage across one of the collector (or drain) resistors or as the differential voltage between the two collectors (or drains). We saw earlier that for ordinary common-emitter and common-source amplifier stages, the load resistor is often replaced by a high resistance active load, usually a current source. A similar technique is commonly used for differential pairs, for reasons that include the following: • The high equivalent resistance of the active load maximizes the voltage gain of the stage. • The differential pair is often followed by another amplifier stage as part of an integrated circuit amplifier, or op amp. The active load on the differential pair provides a “natural” biasing for the next stage. • In integrated circuit technology, it is easier to fabricate transistors than resistors. In Figure 4-27, we show an npn BJT differential pair with a pnp active load. We assume that the npn transistors are matched, and that the pnp transistors are matched. The DC voltage source V X in the figure is assumed to be set so that the voltage at the collector of Q4 is equal to the voltage at the collector of Q3. VCC Q3 iC3 iC1 iB3 iB4 Q4 Ro iC4 iC2 iX VX RS vI2 vS2 RS vS1 vI1 Q1 Q2 IEE RI -VEE Figure 4-27. A BJT differential pair with active load. The DC voltage source VX is used to balance the DC voltages at the collectors of the active-load transistors. DRAFT 09:28 on 17 October 2006 4-32 4 Single-Stage Amplifier Circuits We consider first the operating point of the circuit and then the incremental analysis at the operating point. As before, we find the operating point with v S1 = v S2 = 0 and neglecting the DC current through R I . Following the analysis for the circuit in Figure 4-22, we can conclude that α FN I EE I C1 = I C2 = -----------------2 as in Eqn. (4.36), where α FN is the α F of the npn transistors. Because Q3 and Q4 are matched and operate with equal base-to-emitter voltages, we must also have I C3 = I C4 . Furthermore, from our analysis of BJT current mirrors, we know that I C1 I C3 = – -----------------------2  1 + ---------  β FP (4.55) where β FP is the β F of the pnp devices. We also find that, with the voltage V X set so that the circuit is perfectly balanced, the DC current I X shown in Figure 4-27 flowing out of this source satisfies I C3 – α FN I EE – I X = I B3 + I B4 = 2I B3 = 2 --------- = --------------------β FP 2 + β FP Several observations are worth making before proceeding: 1. We have obviously assumed that all devices remain in the forward-active region. 2. For the circuit’s operating point to be balanced, as we have obtained it, there must be a DC current path away from the junction of the collectors of Q2 and Q4. 3. As we have been doing right along, we have ignored base-width modulation in finding the operating point (i.e., we have neglected the dependence of I C on V BC ). With V X set in Figure 4-27 as described, we have V BC1 = V BC2 and V BC3 = V BC4 . In other words, the circuit has a balanced operating point even if base-width modulation is taken into account. 4. The “load” we have employed in establishing the balanced operating point (i.e. the DC voltage source V X ) represents a short circuit to signals (incremental quantities). In fact, any load connected to the junction of the Q2 and Q4 collectors that results in the following conditions being satisfied: • the voltage at the junction of the Q1 and Q3 collectors is equal to that at the junction of the Q2 and Q4 collectors • the current flowing into the load is related to I EE as in Eqn. (4.56). will cause the circuit’s operating point to be balanced. 5. Because β F for all devices is usually high, it is generally sufficient to take the quiescent current in all four devices to have magnitude equal to 0.5I EE . Now, before analyzing the incremental model of the circuit in Figure 4-27 in detail, let’s consider an approximate qualitative description of its operation based on what we already know about its component blocks, namely the differential pair and the current mirror. (4.56) DRAFT 09:28 on 17 October 2006 4.10 The Differential Pair at Midband 4-33 For a positive differential source voltage v SDM , we would expect i C1 to be greater than its quiescent value I C1 , and i C2 to be less than its quiescent value I C2 by the same amount; in other words, the incremental collector current of Q1 would be positive, while that of Q2 would be equal in magnitude but negative. We would further expect the increase in i C1 to be reflected in an increase in the current coming out of the collector of Q3; if we neglect the base currents of Q3 and Q4, these increases are equal. Because the collector currents of Q3 and Q4 must always be equal, we have an equal increase in the current coming out of the collector of Q4. Now, let’s take i X , the current flowing into the connection of the Q2 and Q4 collectors in Figure 4-27, to be the output current of the circuit. Clearly, this current is the difference between the current flowing into the Q2 collector (i.e. i C2 ) and that flowing out of the Q4 collector (i.e. – i C4 ). The discussion above indicates that the increase in the latter component from its quiescent value is approximately equal in magnitude to the decrease in the former component from its quiescent value. Thus, the change in i X due to v SDM is approximately twice the change in i C2 . In essence, the action of the active load in Figure 4-27 is to process the collector currents of Q1 and Q3 such that the overall incremental output current i x is approximately equal to the negative of the differential-mode collector current i cdm = i c1 – i c2 . This is one form of what is referred to as differential to single-ended conversion. With this qualitative description of the operation of the bipolar differential pair with active load, we are prepared to confront its incremental model, shown in Figure 4-28, in detail. Referring to the figure, note that the output of the circuit is shorted to ground, with the output current I x flowing in this short circuit; this correspond to the connection of the DC voltage source V X as the load in Figure 4-27. Of course, in general there would be some load other than a short circuit connected at the output. By constructing a Norton equivalent circuit looking into the output, including the output resistance R o as shown in Figure 4-28, we can determine the behavior of the circuit into an arbitrary load. The resulting transconductance amplifier model must include responses to both differential-mode and common-mode input signals, so we define transconductances Ix G mdx ≡ ----------V sdm and using superposition we can write I x = G mdx V sdm + G mcx V scm (4.58) V scm = 0 Ix G mcx ≡ ----------V scm (4.57) V sdm = 0 Now, the incremental model for the circuit can be drawn as shown in Figure 4-28, under the assumption that V A → ∞ for all devices. Before proceeding to analyze this circuit, we obtain the values of the model parameters at the operating point found above. For the npn devices in the differential pair, we have (see Eqn. (4.37)): qα FN I EE g mN = g m1 = g m2 = ---------------------- ; 2kT β oN r πN = r π1 = r π2 = --------- ; g mN 2V AN r oN = r o1 = r o2 = ------------------ (4.59) α FN I EE and r bN = r b1 = r b2 . For the pnp devices in the active load, we have: qI C3 g mP = g m3 = g m4 = ---------- ; kT β oP r πP = r π3 = r π4 = --------- ; g mP V AP r oP = r o3 = r o4 = --------I C3 (4.60) DRAFT 09:28 on 17 October 2006 4-34 4 Single-Stage Amplifier Circuits and r bP = r b3 = r b4 . Note that we have used the subscript ‘N’ to refer to parameters of the npn devices, while the subscript ‘P’ refers to those of the pnp devices. Note also that under the assumption that V A → ∞ for all devices, we have that r oN and r oP are both infinite. We begin the analysis of the circuit in Figure 4-28 the same way we began that of the resistively loaded BJT differential pair in Figure 4-23. First, write loop equations for the two input loops: V π1 V s1 = -------- ( R S + r bN + r πN ) + V e ; r πN V π2 V s2 = -------- ( R S + r bN + r πN ) + V e r πN (4.61) These are identical to Eqns. (4.40). Then, write a node equation at the emitters of Q1 and Q2: Ve 1 ----- = ( V π1 + V π2 )  g mN + --------  r πN RI This is identical to Eqn. (4.41). Moreover, we have I c1 = g mN V π1 I c2 = g mN V π2 (4.63) (4.62) excatly as we did for the resistively loaded circuit. Thus the relationship between the collector currents of Q1 and Q2 and the differential-mode and common-mode source voltages will be the same as for the resistively loaded circuit in Figure 4-23. Before we review this relationship and use it to find the transconductances defined in Eqn. (4.57), it is worth simplifying the circuit in Figure 4-28 by taking into account what we already know about a diode-connected BJT like Q3, namely that its incremental model can be represented by a single equivalent resistance. For Q3, we will call this resistance R eq3 and remember (see Eqn. (2.4b) on page 2-4) that it is given by B1 Ii1 rbN rπ N V π1 RI Ve E1,E2 Vs1 RS Vi1 Vs2 Vi2 RS B2 gmNVπ1 B3,C3 C1 B4 gmNVπ2 C2,C4 rπ N Vπ2 rbN Ii2 rbP gmPVπ3 rbP gmPVπ4 Ix rπP Vπ 3 rπP Vπ 4 E3,E4 Ro Figure 4-28. Incremental model for the BJT differential pair with active load. DRAFT 09:28 on 17 October 2006 4.10 The Differential Pair at Midband 4-35 r bP + r πP  r bP + r πP  R eq3 =  ---------------------------  || r oP = --------------------------1 + g mP r πP  1 + g mP r πP (4.64) The resulting equivalent circuit for the output with active load is shown in Figure 4-29. From the figure and B1 Ii1 rbN rπ N V π1 RI Ve E1,E2 Vs1 RS Vi1 Vs2 Vi2 RS B2 gmNVπ1 B3,C3 C1 B4 gmNVπ2 C2,C4 rπ N Vπ2 rbN Ii2 Req3 rbP gmPVπ4 Ix rπP Vπ 4 E3,E4 Figure 4-29. Incremental model for the BJT differential pair with active load. The incremental model for Q3 has been replaced by its equivalent resistance. using Eqn. (4.63), clearly I x = I c2 + g mP V π4 From the left side of the the output circuit, it is possible to obtain the following:  r πP  V π4 = – I c1 [ R eq3 || ( r bP + r πP ) ]  ----------------------   r bP + r πP which can be rewritten as: r πP   V π4 = – I c1  ---------------------------   2 + g mP r πP From the above relations it is possible to write the following:  g mP r πP  I x = I c2 – I c1  ---------------------------   2 + g mP r πP (4.67) (4.66b) (4.66a) (4.65) and we are ready to use the results we have relating the collector currents of Q 1 and Q 2 to the differential-mode and common-mode source voltages. DRAFT 09:28 on 17 October 2006 4-36 4 Single-Stage Amplifier Circuits Consider first the differential-mode transconductance G mdx defined in Eqn. (4.57). To find this quantity, we arrange V s1 and V s2 so that V scm = 0 ; i.e., take V s1 = – V s2 so that V sdm = 2V s1 . Exactly as in the resistively loaded circuit, we find in this case that V π1 = – V π2 and thus g mN r πN  V sdm  I c1 = – I c2 =  -----------------------------------  ---------- R S + r bN + r πN 2 Using this relation with Eqn. (4.67) leads to – g mN r πN  – g mN r πN   1 + g mP r πP G mdx =  -----------------------------------   ---------------------------  ≈ ---------------------------------- r bN + r πN + R S  2 + g mP r πP r bN + r πN + R S where the approximation on the right is generally valid because g mP r πP = β oP » 1 . Consider now the common-mode transconductance G mcx defined in Eqn. (4.57). To find this quantity, we arrange V s1 and V s2 so that V sdm = 0 ; i.e., take V s1 = V s2 so that V scm = V s1 . Exactly as in the resistively loaded circuit, we find in this case that V π1 = V π2 and thus g mN r πN V scm   I c1 = I c2 =  ------------------------------------------------------------------------------------- V scm ≈ ----------2R I  R S + r bN + r πN + 2R I ( 1 + g mN r πN ) (4.70) (4.69) (4.68) where the approximation on the right is generally valid because R I is large. Using this relation with Eqn. (4.67) leads to 1 2 G mcx ≈  --------  ---------------------------   2R I  2 + g mP r πP (4.71) To complete the Norton equivalent circuit looking into the output of the differential pair with active load, we need the equivalent output resistance R o . This is the equivalent resistance looking to the left into the connection of the collectors of Q2 and Q4 in Figure 4-28. Because we have assumed that V A → ∞ for these devices, we would find here that R o is essentially infinite. However, we know that R o will in fact be finite; moreover there are circuits for which we will need to know its value. Unfortunately, analysis of the circuit in Figure 4-28 with finite V A (i.e. finite r oN and r oP ) is very difficult and really requires the half-circuit methodology. All we can do here is to state the result, namely R o = r oN || r oP (4.72) We now have a very simple equivalent circuit for the differential pair with active load as a transconductance amplifier. It is shown inside the shaded box in Figure 4-30, with the source and load connections as in Figures 4-27 and 4-28. For the BJT circuit in these figures, G mdx is given in Eqn. (4.69), G mcx is given in Eqn. (4.71), and R o is given in Eqn. (4.72). For purely differential-mode inputs, the circuit in Figure 4-27 is essentially equivalent to the CE stage with active load discussed in Section 4.2. Compare, for example, the result for G mdx in Eqn. (4.69) and that for G MSS for the CE stage with active load in Eqn. (4.6). DRAFT 09:28 on 17 October 2006 4.10 The Differential Pair at Midband 4-37 Ii1 Vs1 RS Vi1 GmdxVsdm Vi2 RS Ii2 Figure 4-30. Transconductance model of the differential pair with active load. The output is shown short-circuited. The source connection is that of the circuit in Figure 4-27. GmcxVscm Ro Ix Vs2 Generally, G mcx ≈ 0 for the BJT differential pair with active load. We know from the analysis in Section 4.10.1 and earlier in this section that the collector currents of Q1 and Q2 remain equal for a purely common-mode input. In the limit as β F becomes infinitely large for Q3 and Q4, the current-mirror action of the active load causes the collector currents of Q1 and Q2 to cancel each other perfectly at the output, so that I x = 0 for a purely common-mode input; the actual factor in Eqn. (4.71) is approximately 2 ⁄ ( 2 + β FP ) . As we look at applications of the differential pair with active load, we will overlook on this basis its common-mode behavior, and we will neglect G mcx so that Eqn. (4.58) for the short-circuit output current I x reduces to I x = G mdx V sdm Example 4.8 A BJT differential pair with active load, with a realization of the I EE current source using a BJT current mirror, is shown in Figure 4-31. The npn transistors are matched with β FN = β oN = 150 and V AN = 100 , while the pnp transistors are matched with β FP = β oP = 75 and V AP = 75 . For all the devices, – 16 I S = 2 ×10 A and r b = 100Ω . In addition, V CC = 12V and V EE = 12V . A design objective for the circuit is that G mdx = 10mA/V with R S = 0 . We will carry out the design, which amounts essentially to finding the value of the current-mirror resistor R, using convenient approximations, and then we will characterize the circuit in detail. If r bN were zero, Eqn. (4.69) indicates that g mN = 10mA/V to meet the design objective, which in turn requires that I C1 = I C2 = 250µA and so I C6 = I EE ≈ 500µA . Note that g mN = 10mA/V yields r πN = 15kΩ , so neglecting r bN compared to r πN is justified. Using the simplified nonlinear model for Q5 and Q6 in the active region, we find that V BE5 = V BE6 = 714mV . The loop equation to be solved for R is V EE – V BE5 R = ---------------------------IR With I R = I C6 ( 1 + 2 ⁄ β FN ) , this equation yields R = 22.28kΩ . Using this value of R, we would then actually have I C1 = I C2 = 0.5α F I EE = 248.3µA , and also I C3 = I C4 = – 241.9 µA , with I X = 6.45µA and V EB4 = 696mV . The necessary value for V X is found as V X = V CC – V EB4 = 11.304V . (4.73) DRAFT 09:28 on 17 October 2006 4-38 4 Single-Stage Amplifier Circuits Using the computed values of the DC collector currents to find the values of the incremental model parameters yields g mN = 9.93mA/V; r πN = 15.1kΩ; r oN = 402.7kΩ g mP = 9.68mA/V; r πP = 7.75kΩ; r oP = 310.1kΩ In addition, the resistance R I is the incremental output resistance of the current source; i.e. V AN R I = r o6 = --------- = 200kΩ I EE We obtain the following results with R S = 0 : G mdx = – 9.74mA/V; R id = 15.2kΩ; R o = 175.2kΩ; G mcx = 65.56nA/V (4.74a) We might also consider the circuit with a non-zero value of R S . For example, with R S = 5kΩ , we find using Eqn. (4.69) that G mdx = – 7.34mA/V while the other quantities in Eqn. (4.74a) do not depend on R S . Note that the magnitude of G mcx is more than five orders of magnitude smaller than that of G mdx ; thus, it is quite reasonable to take G mcx ≈ 0 . Note also that the computed magnitude of G mdx is about 2.5% below the design objective with R S = 0 , because of the approximations made at the outset. This is well within the error tolerance one would expect for hand analysis using nominal values of device parameters. We could have obtained equally useful results by taking α F ≈ 1 , 1 + β F ≈ 2 + β F ≈ β F , etc. Indeed, effects such as VCC Q3 iC3 iC1 (4.74b) iB3 iB4 Q4 iC4 iC2 Ro iX VX RS Vs2 RS Vs1 Q1 Q2 IC6 R IR Q5 Q6 -VEE Figure 4-31. Circuit for Example 4.8. DRAFT 09:28 on 17 October 2006 4.10 The Differential Pair at Midband 4-39 base-width modulation not taken into account in the by-hand DC analysis introduce additional errors in the computed results above. These can be seen by running a simulation of the circuit. Results of a Spice simulation for each of the BJTs in the circuit, using R = 22.28kΩ as above and V X adjusted to 11.277V, are summarized in Table 4-1. Note that I C6 is larger than I C5 due to base-width modulaTable 4-1 Spice simulation results for Example 4.8. Q1 IC (µA) VBE (mV) gm (mA/V) rπ (kΩ) ro (kΩ) 274 720 10.6 15.8 406 Q2 274 720 10.6 15.8 406 Q3 −267 −722 10.3 7.27 281 Q4 −267 −722 10.3 7.27 281 Q5 499 739 19.3 7.78 200 Q6 551 739 21.3 7.78 200 tion; while V BC5 = 0V , the simulation shows that V BC6 = – 10.5V . As a result, the DC collector currents of Q1 and Q2 and thus also their transconductances are about 10% higher than the values obtained by hand calculation. For the circuit, the simulation results corresponding to the computed values in Eqn. (4.74a) are: G mdx = – 10.39mA/V; R id = 15.85kΩ; R o = 167kΩ; G mcx = 65.66nA/V (4.75) The differences between these results and the computed values in Eqn. (4.74a) are completely accounted for by the differences between the computed device parameters and the values in Table 4-1. Finally, it is interesting to note that the simulation shows R ic = 33.9MΩ . Clearly, taking R ic → ∞ is quite reasonable here. 4.10.4 The MOS Differential Pair with Active Load Figure 4-32 shows an MOS differential pair with active load. The load devices, M3 and M4, are matched PMOS transistors, while the differential pair uses matched NMOS transistors as before. The DC voltage source V X in the figure is assumed to be set so that the voltage at the drain of M4 is equal to the voltage at the drain of M3. We consider first the operating point of the circuit, and then the incremental analysis at the operating point. As before, we find the operating point with v S1 = v S2 = 0 and neglecting the DC current through R I . Following the analysis for the circuit in Figure 4-25, we can conclude that the DC drain currents of M1 and M2 are equal, while the DC drain currents of M3 and M4 must be equal because of the “current mirror” connection. The adjustment of the DC voltage source V X described above insures that these conditions hold, with the circuit perfectly balanced at its operating point, even with channel-length modulation taken into account. At the operating point, we thus have 1 I D1 = I D2 = -- I ss 2 1 I D3 = I D4 = – -- I ss 2 (4.76) DRAFT 09:28 on 17 October 2006 4-40 4 Single-Stage Amplifier Circuits VDD M3 iD3 iD1 M4 iD4 iD2 iX VX RS vI2 vS2 RS vS1 vI1 M1 M2 ISS RI –VSS Figure 4-32. An MOS differential pair with active load. The incremental model at the operating point is shown in Figure 4-33, where we have made the assumption that λ = 0 for all devices. We have taken advantage of the equivalent circuit we already have for the “diode-connected” transistor M3, showing its equivalent incremental resistance in the figure as R eq3 with 1 R eq3 = --------g mP (4.77) The short-circuit transconductances are defined for the circuit in the same way they are for the BJT circuit (see Eqn. (4.57)). The circuit analysis also follows that for the BJT circuit. First, the parameters of the incremental model at the operating point found above are G1 Ii1 Vgs1 RI Vz S1,S2 Vs1 RS Vi1 Vs2 Vi2 RS G2 gmNVgs1 Vgs2 D1,D3 G4 gmNVgs2 D2,D4 Ii2 Req3 Vgs4 S3,S4 gmPVgs4 Ix Figure 4-33. Incremental model of the MOS differential pair with active load. DRAFT 09:28 on 17 October 2006 4.10 The Differential Pair at Midband 4-41 k'W g mN = g m1 = g m2 =  -------- V GSN – V TN ;  L N k'W g mP = g m3 = g m4 =  -------- V GSP – V TP ;  L P where V GSN – V TN = I SS ( L ⁄ k'W ) N and V GSP – V TP = 2 r oN = r o1 = r o2 = ------------λ N I SS 2 r oP = r o3 = r o4 = ------------λ P I SS (4.78) I SS ( L ⁄ k'W ) P . Note that the subscript ‘N’ refers to the NMOS devices in the differential pair, while the subscript ‘P’ refers to the PMOS devices in the active load. Except for the load configuration, the circuit under consideration here in Figure 4-33 is identical to the resistively loaded circuit in Figure 4-26. We rewrite Eqns. (4.52) and (4.53): V s1 = V gs1 + V z V s2 = V gs2 + V z V ----z = g mN ( V gs1 + V gs2 ) RI and in addition we again have that I d1 = g mN V gs1 and I d2 = g mN V gs2 . Now, for the output circuit we can write: I x = I d2 + g mP V gs4 so that, using Eqn. (4.77): I x = I d2 – I d1 Following the analysis for the BJT circuit in Figure 4-29, we find that G mdx = – g mN ; and in addition R id and R ic are both infinite. Consider now the equivalent output resistance R o , i.e. the equivalent resistance looking to the left into the connection of the collectors of M2 and M4 in Figure 4-33. Because we have assumed that λ = 0 for these devices, we would find here that R o is essentially infinite. However, we know that R o will in fact be finite; moreover there are circuits for which we will need to know its value. Unfortunately, analysis of the circuit in Figure 4-33 with non-zero λ (i.e. finite r oN and r oP ) is very difficult and really requires the half-circuit methodology. All we can do here is to state the result as we did for the actively loaded BJT differential pair; it is in fact the identical result, namely R o = r oN || r oP (4.82) (4.80) and V gs4 = – I d1 R eq3 (4.79) G mcx = 0 (4.81) One additional artifact of using λ = 0 in the incremental analysis is that the common-mode transconductance G mcx is found to be exactly zero. In fact, with non-zero λ G mcx is also not zero; however, it is extremely small and can reasonably be taken to be zero. The entire circuit in Figure 4-32 can now be represented using the same transconductance model in Figure 4-30 that was used for the BJT differential pair with active load. DRAFT 09:28 on 17 October 2006 4-42 4 Single-Stage Amplifier Circuits 4.10.5 Additional Remarks The differential-pair circuits we have considered are essentially complete. That is, they have included explicitly whatever is needed to bias the BJT or MOS transistors so that their operating points are appropriate. The only apparently unusual aspect of the biasing is the the DC voltage source, V X , used in the circuits with active load to insure that the circuits’ DC conditions are balanced. As we will see, the application of these circuits tends to be such that an equivalent DC voltage is provided at the output that maintains a balanced operating point. Perhaps the most common applications for these circuits are as input stages of op amps or other amplifier subsystems. In some cases, the circuits are exactly those of Figures 4-27 and 4-32. In other cases, that portion of the amplifier that displays differential symmetry may consist of several equivalent stages; for example, a topology that is common in MOS technology is the so-called differential cascode (sometimes in the form of a so-called folded cascode), in which each of the two differential-pair devices in Figure 4-32 is replaced by two devices, the first connected essentially as common-source and the second connected as common-gate. Analysis of these more complicated circuits can be carried out following steps similar to those used here for the basic actively loaded circuits. Alternatively, given the appropriate groundwork the half-circuit analysis techniques referred to at the end of Section 4.10.1 can be employed. 4.11 Analysis of Amplifier Stages at High Frequencies We are now ready to investigate the high-frequency behavior of the amplifier stages considered above. Whereas we characterized these circuits at midband using either Thevenin or Norton equivalent circuit, i.e. with the output either open-circuited or short-circuited, we will carry out the high-frequency analysis with some finite, non-zero load in place. The major reason is that, for several of the amplifier stages, the behavior at high frequencies depends in fundamental ways on the value of the load resistance. 4.12 The CE and CS Stages at High Frequencies Figure 4-34 shows the dynamic incremental model of a common-emitter stage driven by a voltage source V s . A resistance R L is shown connected at the output from the collector to ground. This resistance is assumed to be the parallel combination of a resistance internal to the stage, i.e. the resistance R C for the CE stage in Figure 4-1 or the resistance R I for the CE stage with active load in Figure 4-5, and an externally connected load resistance. Figure 4-36 below shows the dynamic incremental model of a common-source stage. It can be seen from the figures that the circuits are very similar, and they will be treated together in this section. We will carry out an exact analysis of these circuits and then develop an approximation that will permit us to focus on the dominant factors in controlling their high-frequency behavior. 4.12.1 Exact Analysis for the CE Stage Referring to Figure 4-34, our objective is to find A VSL ≡ ( V o ⁄ V s ) with the load resistance in place. We begin by defining for convenience R' S ≡ R S + r b and R' L ≡ R L || r o . Writing node equations at V π and V o yields RS B Vs Vbe rπ Vπ Cπ gmVπ E Figure 4-34. Dynamic incremental model of a CE stage. Ib rb Cµ C ro Ccs Ic RL Vo DRAFT 09:28 on 17 October 2006 4.12 The CE and CS Stages at High Frequencies 4-43 Vs 1 1 ------ =  ------ + ---- + sC π + sC µ V π – sC µ V o ;  R'  R' S S rπ Solving these equations for V o in terms of V s yields 1 0 = ( g m – sC µ )V π +  ------ + sC µ + sC cs V o  R'  L sC µ  A o  1 – --------  gm   A VSL ( s ) = ---------------------------------1 + a1 s + a2 s2 where – g m r π R' L A o = ---------------------R' S + r π a1 = 0 Cπ Rπ (4.83a) (4.83b) + 0 Cµ Rπ ( 1 + g m R' L ) + R' L ( C cs + C µ ) ; a2 = 0 R' L R π ( C π C cs + C π C µ + C µ C cs ) 0 0 and R π ≡ r π || R' S (in fact, R π is the equivalent resistance in parallel with C π with all other capacitors in the circuit replaced by open circuits). Note that the quantity A o in Eqn. (4.83b) is in fact the midband value of the voltage gain A VSL . This is to be expected, since in Eqn. (4.83a) A o = A VSL ( 0 ) , which is the gain at zero frequency ( ω = 0 ). The roots of the denominator polynomial in Eqn. (4.83a) are the poles of A VSL ( s ) . Assuming that these roots are real, s = – ω p1 and s = – ω p2 , we can write A VSL ( jω ) for ω < ω T as: Ao A VSL ( jω ) = ---------------------------------------------------ω ω  1 + j --------   1 + j --------   ω p1  ω p2 (4.84) where we have used ( ω T C µ ⁄ g m ) « 1 as we did in connection with Eqn. (3.38). The behavior of the log magnitude of A VSL ( jω ) as a function of ω is shown in Figure 4-35. Note in particular that if the lower frequency pole, shown as ω p1 in the figure, is much smaller than the higher frequency pole, then the value of ω H , the upper 3dB frequency of A VSL (and thus the bandwidth of A VSL ) is essentially equal to ω p1 . Example 4.9 The BJT in the circuit of Figure 4-34 is biased at I C = 1mA and V CE = 10V . At this operating point, the device parameters are β F = β o = 100 , f T = 1GHz , C µ = 0.1pF , and C cs = 0 . Also, R' S = 10kΩ and R' L = 10kΩ . Clearly, g m = 0.04A/V and r π = 2.5kΩ . Also, from Eqn. (3.40) we find that C π = 6.3pF . Substituting values into Eqns. (4.83b), we have: A o = – 80 ; a 1 = 9.37 ×10 –8 ; a 2 = 1.25 ×10 – 17 Factoring the denominator polynomial of A VSL yields DRAFT 09:28 on 17 October 2006 4-44 4 Single-Stage Amplifier Circuits Lm(AVSL) (dB) fP1 = 1.7MHz fP2 = 1.19GHz f (Hz) Figure 4-35. Log magnitude of the voltage gain for a CE stage. The values shown are for the circuit in Example 4.9. ω p1 = 10.68 ×10 rad/sec (1.7MHz) ; 6 ω p2 = 7.47 ×10 rad/sec (1.19GHz) 9 Clearly, for this circuit ω H = ω p1 . Note also that ( ω T C µ ⁄ g m ) = 0.016 , so that taking the numerator in Eqn. (4.83a) to be essentially equal to A o for frequencies up to ω T (and thus well above ω H ), as we did in Eqn. (4.84), is a valid approximation. In the example above, the bandwidth of the voltage gain is almost three orders of magnitude smaller than the maximum useful frequency of the BJT ( ω T ) and almost one order of magnitude smaller than ω β , the bandwidth of β. Unfortunately, from the exact analysis presented here we gain no insight at all into how the bandwidth of the voltage gain is limited by the circuit parameters, and we have no clear way of identifying those parameters that are most important in this respect. Before considering an approximation that will provide the insight we’re looking for, we comment on the exact analysis for a common-source stage. 4.12.2 Exact Analysis for a Common Source Stage Figure 4-36 shows the dynamic incremental model of a CS stage driven by a voltage source V s . A resistance R L is shown connected at the output from the drain to ground. This resistance is assumed to be the parallel combination of a resistance internal to the stage, i.e. the resistance R D for the CS stage in Figure 4-10 or the resistance R I for the CE stage with active load in Figure 4-11, and an externally connected load resistance. The circuit analysis for A VSL ≡ ( V o ⁄ V s ) follows that for the CE stage above. We find RS Vs Ig Vgs G Cgs Cgd gmVgs S,B Figure 4-36. Dynamic incremental model of a CS stage. D ro Cdb Id RL Vo DRAFT 09:28 on 17 October 2006 4.12 The CE and CS Stages at High Frequencies 4-45 sC gd  A o  1 – ----------- gm   A VSL ( s ) = ---------------------------------1 + a1 s + a2 s2 where (4.85a) A o = – g m R' L (4.85b) a 1 = C gs R S + C gd R S ( 1 + g m R' L ) + R' L ( C db + C gd ) ; a 2 = R' L R S ( C gs C db + C gs C gd + C gd C db ) The considerations discussed above for the CE stage apply to the CS stage here, as well. 4.12.3 Miller’s Theorem The complicating factor in the analysis of the CE and CS stages above is the presence of a capacitor between input and output ( C µ for the CE stage, C gd for the CS stage). Miller’s theorem appears to provide a useful simplification for these cases. Consider two networks connected by an impedance Z, as shown in Figure 4-37(a). It is possible to replace Z by two impedances Z M1 and Z M2 , connected as shown in Figure 4-37(b). The two circuits in the figure are specified as being identical, in that V x = V' x , V y = V' y , I x = I' x , and I y = I' y . In other words, the networks N 1 and N 2 cannot tell the difference between being interconnected with the impedance Z or having the impedances Z M1 and Z M2 connected in shunt as shown in Figure 4-37(b). The values of Z M1 and Z M2 that provide the equivalence can be found by equating the appropriate voltages and currents in the two circuits as noted above. Defining K M ≡ V y ⁄ V x , we find: Z Z M1 = ---------------1 – KM ZK M Z M2 = ---------------KM – 1 (4.86) 4.12.4 The Miller Approximation for CE and CS Stages We can apply Miller’s theorem to a CE stage, transforming C µ to a capacitance C M1 in parallel with C π and r π , and a capacitance C M2 in parallel with r o , as shown in Figure 4-38. From Eqn. (4.86): C M1 = C µ ( 1 – K M ) ; Cµ ( KM – 1 ) C M2 = ---------------------------- ; KM Vo K M = ----Vπ Referring back to Figure 4-34, we can solve for K M as Ix N1 Z Vx (a) Iy Vy N2 N1 I'x ZM1 V'x (b) I'y V'y ZM2 N2 Figure 4-37. The equivalence provided by Miller’s theorem. DRAFT 09:28 on 17 October 2006 4-46 4 Single-Stage Amplifier Circuits sC µ  K o  1 – --------  gm   Vo K M ( s ) = ----- = ---------------------------------------------1 + s ( C cs + C µ )R' L Vπ (4.87) where K o = – g m R' L . Using this relation to find C M1 and C M2 , we again have a level of complexity in the algebra that hides what is really going on in the circuit. However, examination of Eqn. (4.87) shows that we can make the following approximation: K M ( jω ) ≈ K o = – g m R' L for ω ( C cs + C µ )R' L « 1 (4.88) Our basic interest here is to find the upper 3dB frequency ω H of the common emitter voltage gain. Without yet knowing what ω H is, let’s assume that this approximation is valid for frequencies at least up to ω H . So: C M1 = C µ ( 1 + g m R' L ) ; 1 C M2 = C µ  1 + -------------- ≈ C µ  g R'  m L (4.89) The quantity g m R' L is generally quite large. We see then that the large inverting voltage gain from V π to V o (essentially from base to collector) causes a much magnified version of C µ to appear at the input (essentially from base to ground). This Miller input capacitance is often much larger than the capacitance already there 0 ( C π ). It is this large C M1 together with the equivalent resistance in parallel with it ( R π Eqn. (4.83b)) that generally determines ω H . From Figure 4-38, the voltage gain A VSL ( s ) can be written almost by inspection: Ao A VSL ( s ) = --------------------------------------------------------s s  1 + -------------  1 + -------------    ω ω pM1 pM2 (4.90a) where A o is given in Eqn. (4.83b) and 1 ω pM1 = ----------------------------------- ; 0 R π ( C π + C M1 ) 1 ω pM2 = -------------------------------------R' L ( C cs + C M2 ) (4.90b) In general, ω pM1 « ω pM2 , so that ω H ≈ ω pM1 . Moreover, when this is true we also find that the approximation in Eqn. (4.88) is valid at ω = ω pM1 , so the approximation is indeed useful in evaluating ω H and in providing the insight we have found into the effect of the Miller input capacitance on the CE stage bandwidth. Ib B Vs Vbe rπ Vπ Cπ CM1 E Figure 4-38. Application of Miller’s theorem to the base-collector capacitance. RS rb gmVπ ro Ccs C CM2 Ic RL Vo DRAFT 09:28 on 17 October 2006 4.13 The CC and CD Stages at High Frequencies 4-47 On the other hand, it is important to note that ω pM2 is essentially equal to the pole frequency of K M ( s ) (see Eqn. (4.87)). At this frequency, the approximation in Eqn. (4.88) is not valid. In other words, the value we obtain for C M2 in Eqn. (4.89) using this approximation cannot be correct, and the value we obtain for the higher frequency pole of the CE voltage gain using this approximation also cannot be correct. Fortunately, our primary interest here is to find ω H . The Miller approximation is almost always valid at this frequency, which we obtain by considering only C M1 . In other words, the Miller approximation essentially amounts to taking A VSL ( s ) to be a single-pole response, with Ao A VSL ( s ) = ---------------------------s  1 + -------------  ω pM1 and ω pM1 given in Eqn. (4.90b). Example 4.9 (continued) In Example 4.9 above, g m R' L = 400 , so that C M1 = 40.1pF and C M2 = 0.1pF . Using Eqn. (4.90b), we find ω pM1 = 10.78 ×10 rad/sec (1.72MHz), in excellent agreement with the exact result given above. The Miller approximation is valid only for ω « 10 rad/sec in this example by Eqn. (4.88), but we also would have ω pM2 = 10 rad/sec if we attempt to use the approximation to find it. Recall from above that the value of the second pole from the exact analysis (i.e. ω p2 ) is 7.47 ×10 rad/sec . The development of the Miller approximation for the CS stage follows alomst exactly that for the CE stage. 9 9 9 6 (4.90c) 4.13 The CC and CD Stages at High Frequencies Recall the common-collector stage in Figure 4-12 and the common-drain stage in Figure 4-14. The dynamic incremental model of the common-collector stage is shown in Figure 4-39. An external load, consisting of a resistance R L and capacitance C L in parallel, has been added. The load capacitance is important here. Common-collector stages are often used to drive off-chip loads, and these generally have some capacitive component, even if only parasitic. The collector-substrate capacitance is not shown in Figure 4-39; because the substrate is always at incremental ground, it is effectively shorted out in the CC stage. The dynamic incremental model of the common-drain stage is shown in Figure 4-40. Here again the external load consisting of R L and C L in parallel has been added. The capacitance C db is not explictly shown; with the assumption that Cπ RS Vs Ii Vi B rb Cµ rπ Vπ gmVπ E ro C RE RL CL Vo Figure 4-39. Incremental model at high frequencies of the CC stage in Figure 4-12. An external load consisting of a resistance and capacitance has been added. DRAFT 09:28 on 17 October 2006 4-48 4 Single-Stage Amplifier Circuits Yb Is Ya Va Vb gmVb Yc Vc Figure 4-41. A generalized “follower” circuit model. the substrate is connected to the source, C db is in parallel with the load capacitance and so is taken to be included in C L . We can write circuit equations and solve for the loaded voltage gain A VSL ( s ) of the CC and CD stages exactly. We would also like to have useful approximations that will highlight those elements in these circuits that control theri bandwidth. Unfortunately, there is no approximation that is generally applicable to these circuits in the way the Miller approximation is generally applicable for the CE and CS stages. Nonetheless, we will be able to find some useful results. In obtaining an exact solution for the CC and CD stages, we will take a somewhat more abstract approach than that taken in Section 4.12. First, we will a generic “follower” circuit model5, of which the circuits in Figures 4-39 and 4-40. We will then use the formalized method generally employed by computer tools such as SPICE to write circuit equations. This method generates node equations in which the voltages from each node to ground are the independent variables and the independent sources are current sources. The node equations are written in matrix form and are solved using matrix algebra. The generalized “follower” circuit is shown in Figure 4-41. The elements Y a , Y b , and Y c are admittances that we will identify with appropriate components in the CC and CD circuits. The voltage source V s and the resistance directly in series with it in Figures 4-39 and 4-40 have been replaced by a Norton equivalent with independent current source I s . Comparing the circut in Figure 4-41 with the CC stage in Figure 4-39, we can make the following identifications for the CC stage: Vs I s = -----R' S 1 Y a = ------ + sC µ R' S 1 Y b = ---- + sC π rπ 1 Y c = ------ + sC L R' L (4.91) where R' S ≡ R S + r b and R' L ≡ r o || R E || R L . Comparing the circut in Figure 4-41 with the CD stage in Figure 4-40, we can make the following identifications for the CD stage: RS Ii Vs Vi G Cgs Cgd Vgs gmVgs S,B ro D RZ RL CL Vo Figure 4-40. Incremental model at high frequencies of the CD stage in Figure 4-14. An external load consisting of a resistance and capacitance has been added. 5. Recall that the CC stage is sometimes called an “emitter follower” and that the CD stage is simetimes called a “source follower”. Similar circuits built using vacuum tubes were called “cathode followers”. DRAFT 09:28 on 17 October 2006 4.13 The CC and CD Stages at High Frequencies 4-49 Vs I s = ----RS where R' L ≡ r o || R Z || R L . 1 Y a = ----- + sC gd RS Y b = sC gs 1 Y c = ------ + sC L R' L (4.92) The node equations for the circuit in Figure 4-41 can be written in matrix form as follows: Ya + Yb –Yb – gm –Yb Va Is 0 Yc + Yb + gm Vc = (4.93) These equations are formulated by considering the the admittances connected to each node and between pair of nodes. In outline form, which will be sufficient for right now: • Each diagonal element contains the sum of all the admittances connected to the associated node. For example, the (1,1) element contains the sum of all the admittances connected to node associated with V a . • Each non-diagonal element contains the negative of the sum of all the admittances connected directly between the associated node pair. For example, the (1,2) element contains the negative of Y b , which is the net admittance connected directly between the nodes associated with V a and V c . • Voltage-controlled current sources are dealt with based upon the nodes between which they are connected and the nodes whose voltages control them. The g m source in Figure 4-41 flows into the node associated with V c and is controlled by ( V a – V c ) ; the way g m appears in the matrix in Eqn. (4.93) is the consequence. • Each element of the right-hand-side vector contains the net of all independent current sources flowing into the associated node. The only independent current source in the circuit under consideration is I s , and it flows into the node associated with V a . At this point, a computer tool such as SPICE would be already using the relations for the specific circuit (i.e. (4.91) or (4.92)) with specific component values and would then proceed to invert the matrix in (4.93) to obtain the solution. Here, we’ll keep things general just a while longer. Inverting the matrix in Eqn. (4.93) yields Va Is 1 Y + Yb + gm Yb = -- c ∆ Vc Yb + gm Ya + Yb 0 (4.94) where the determinant ∆ is given by ∆ = ( Yc + Yb + gm ) ( Ya + Yb ) – Yb ( Yb + gm ) = Ya ( Yc + Yb + gm ) + Yb Yc The desired result is Vc Vc Yb + gm A VSL ( s ) = ----- = ----------- = -----------------R' S ∆ Vs I s R' S (4.95) We’ll now look at the specifics of the CC stage. Using Eqn. (4.91) and a good deal of algebra, the voltage gain in Eqn. (4.95) can be written as DRAFT 09:28 on 17 October 2006 4-50 4 Single-Stage Amplifier Circuits s A 0  1 + -----   ω z A VSL ( s ) = ---------------------------------2 1 + a1 s + a2 s where A 0 is the loaded midband voltage gain of the CC stage, from Section 4.5: ( 1 + g m r π )R' L A 0 = ----------------------------------------------------------R' S + r π + ( 1 + g m r π )R' L the zero frequency ω z is 1 + gm rπ gm ω z = -------------------- ≈ ------ ≈ ω T rπ Cπ Cπ and the coefficients of the denominator polynomial are ( C µ C L + C µ C π + C π C L )R' L R' S r π a 2 = --------------------------------------------------------------------------------R' S + r π + ( 1 + g m r π )R' L and C µ R' S [ r π + ( 1 + g m r π )R' L ] + C π r π ( R' L + R' S ) + C L R' L ( r π + R' S ) a 1 = ------------------------------------------------------------------------------------------------------------------------------------------------------------R' S + r π + ( 1 + g m r π )R' L (4.96) (4.97) (4.98) (4.99) (4.100) These relations may appear to be rather formidable. However, they do contain some readily accessible information. In particular, the expression for a 1 in (4.100) is the sum of three terms, each in the form of a time constant (i.e. an RC-product), with one term for each of the capacitances in the circuit; also, the expression for a 2 in (4.99) is the sum of three terms, each in the form of the product of two time constants, with one term for each pair of capacitances in the circuit6. Assume now that the poles of A VSL ( s ) are real, at s = – ω p1 and s = – ω p2 . By writing out the denominator polynomial from its factored form as ( 1 + s ⁄ ω p1 ) ( 1 + s ⁄ ω p2 ) , we can make the following identifications: 1 1 a 1 = -------- + -------ω p1 ω p2 1 a 2 = -----------------ω p1 ω p2 (4.101) If A VSL ( s ) has a dominant pole (recall the discussion at the end of Section 3.5), say with ω p1 « ω p2 , we have the approximation 1 ω H ≈ ω p1 ≈ ---a1 (4.102) If one of the three terms in Eqn. (4.100) is much larger than the others, then that term, and the capacitance and equivalent resistance that make up that term, dominate in establishing the upper 3dB frequency ω H 6. The coefficients a 1 and a 2 for the CE stage in Eqn. (4.83b) and for the CS stage in Eqn. (4.85b) also behave this way. The properties outlined here can be generalized, as will be discussed later. DRAFT 09:28 on 17 October 2006 4.13 The CC and CD Stages at High Frequencies 4-51 Example 4.10 In the CC circuit in Figure 4-39, the BJT is biased at I C = 1mA and has f T = 1GHz , C µ = 100fF , and β F = β o = 100 ; also R' S = R' L = 1kΩ and C L = 0 . At the operating point we have g m = 0.04A/V , r π = 2.5kΩ , and C π = 6.3pF . We compute: A 0 = 0.967 9 a 1 = 4.0 ×10 – 10 a 2 = 1.5 ×10 10 – 20 ω p1 = 2.80 ×10 rad/sec (446MHz) 9 ω p2 = 2.39 ×10 rad/sec (3.79GHz) (4.103) ω z = 6.45 ×10 rad/sec (1.03GHz) A plot of the log magnitude of A VSL for this example is shown in Figure 4-42(a). The plot shows that the Lm(AVSL) (dB) (a) Lm(AVSL) (dB) (b) fH = 550MHz fH = 188MHz f (Hz) f (Hz) Figure 4-42. Log magnitude of the gain of the CC stage. (a) CL = 0; (b) CL = 10pF. upper 3dB frequency (in Hz) is f H = 550MHz . In this example, while ω p1 is an order of magnitude smaller than ω p2 , it is not strictly speaking a dominant pole, because of the proximity of the zero at ω z . Nonetheless, approximating ω H ≈ ω p1 yields an estimate within about 20% of the actual value for ω H . In addition, looking at the values of the individual terms that make up a 1 , we would notice that the component due to C π is about three times as large as that due to C µ , so that it is the term in C π that dominates in determining ω p1 and thus ωH . Consider now the same circuit but with C L = 10pF . Redoing the calculations, we have new values for the denominator coefficients and the pole frequencies: a 1 = 7.35 ×10 – 10 a 2 = 1.55 ×10 – 18 ω p1, ω p2 = ( 2.38 ± j7.68 ) ×10 rad/sec 8 8 (4.104) In this case the poles are complex, with the magnitude of the pole frequencies equal to 8.04 ×10 rad/sec or 128MHz. The log magnitude of A VSL for this case is shown in Figure 4-42(b). The figure clearly shows a 5dB peak in the response in the neighborhood of the pole-frequency magnitude. The peak is due to the complex pole pair with imaginary part significantly larger than the real part (by a factor of 3.2 in this example), and it is generally undesirable. It is not unusual, however, for the presence of a capacitive load to shift the poles of a CC stage off the real axis. Careful design can prevent undesirable peaking. In this example, a large DRAFT 09:28 on 17 October 2006 4-52 4 Single-Stage Amplifier Circuits increase in R S will shift the poles back toward the real axis and eliminate the peaking; however, the midband gain and bandwidth are both reduced. For the CD stage, using Eqn. (4.92), A VSL ( s ) is given by Eqn. (4.96) with g m R' L A 0 = ----------------------1 + g m R' L C gs ( R S + R' L ) + C L R' L a 1 = C gd R S + ------------------------------------------------------1 + g m R' L gm ω z = -------C gs ( C gd C L + C gd C gs + C gs C L )R' L R S a 2 = ----------------------------------------------------------------------------------1 + g m R' L (4.105) The observations above regarding the form of a 1 and a 2 for the CC stage clearly apply here as well. DRAFT 09:28 on 17 October 2006 4.13 The CC and CD Stages at High Frequencies 4-53 Table 4-2 Qualitative behavior of amplifier stages Stage CE CS CE (degen.) CS (degen.) CC CD CB CG Best Model Transconductance Transconductance Transconductance Transconductance Voltage amp Voltage amp Current amp Current amp Gain Behavior AVSO large, negative AVSO large, negative G MSS ∼ 1 ⁄ R E G MSS ∼ 1 ⁄ R Z AVSO positive, < 1 AVSO positive, < 1 AISS close to – 1 AISS close to – 1 Ri rb + rπ ∞ high ∞ high ∞ ~ 1 ⁄ gm ~ 1 ⁄ gm Ro ' ro ro > ro > ro low low >> r o >> r o Upper 3dB Freq. limited by C µ and Miller effect limited by C gd and Miller effect higher than CE higher than CE very high very high very high very high DRAFT 09:28 on 17 October 2006 4-54 4 Single-Stage Amplifier Circuits DRAFT 09:28 on 17 October 2006 5.1 Incremental Analysis of Multistage Amplifiers 5-1 5 Multistage Amplifiers Most practical amplifiers are multistage amplifiers, i.e. they consist of several stages with the output of one connected to the input of the next. This is generally referred to as a cascade connection; one generally speaks of a multistage amplifier as consisting of several amplifier stages connected in cascade. The motivation for building multistage amplifiers can be seen from the following example. Recall that a common-emitter stage can provide significant voltage gain but has a relatively high output resistance, and that a common-collector stage has a low output resistance but its voltage gain is less than one. An amplifier consisting of a CE stage followed by a CC stage can have a net voltage gain that remains large in magnitude and also a relatively low output resistance, and it may thus be potentially useful as a voltage amplifier. 5.1 Incremental Analysis of Multistage Amplifiers In dealing with multistage amplifier circuits, we would like to be able to take as much advantage as possible of the results we have developed for single-stage circuits. This is possible, but only up to a point. The midband analysis can be made methodical and relatively straightforward. The high-frequency analysis is much more difficult; however, for our purposes here there are some useful approximations that simplify the analysis. 5.1.1 Midband Analysis Figure 5-1 shows in a somewhat abstract view a three-stage amplifier driven by a voltage source V s with source resistance R S and driving a load resistance R L . The approach we take to analyze this circuit can be outlined as follows: • Start with stage 1. Construct a Thevenin or Norton equivalent circuit looking into the output of the stage. • Consider stage 2 driven by the equivalent circuit constructed for stage 1. Now obtain a Thevenin or Norton equivalent circuit looking into the output of stage 2. Note that for this analysis stage 2 is just a single stage driven by either a voltage source or a current source. Note also that the equivalent circuit found in this step represents everything to the left of the output of stage 2 in Figure 5-1, i.e. both stage 1 and stage 2. • Consider stage 3 driven by the equivalent circuit for stages 1 and 2. Now obtain a Thevenin or Norton equivalent circuit looking into the output of stage 3. This equivalent circuit can be used in place of the entire amplifier to drive the load resistance. This process is illustrated in Figure 5-2. In (a) and (b) in the figure, a Thevenin equivalent circuit is constructed for the first stage driven by the voltage source V s ; the equivalent circuit consists of a voltage source A 1 V s and equivalent output resistance R o1 . In Figure 5-2(c), the second stage is driven by this equivalent circuit shown as a voltage source V s2 with an associated source resistance R S2 ; as indicated in the figure, RS Vs Figure 5-1. A three-stage amplifier. STAGE 1 STAGE 2 STAGE 3 Vo RL DRAFT 09:28 on 17 October 2006 5-2 5 Multistage Amplifiers RS Vs (a) Ro1 STAGE 1 A1Vs (b) RS2 Vs2 (c) Ro2 STAGE 2 A2Vs2 (d) V s2 = A 1 V s R S2 = R o1 RS3 Vs3 (e) Ro3 STAGE 3 A3Vs3 (f) V s3 = A 2 V s2 R S3 = R o2 Figure 5-2. Analysis of the three-stage amplifier. V s2 = A 1 V s and R S2 = R o1 . In Figure 5-2(d), a Thevenin equivalent circuit is constructed looking into the output of the circuit in Figure 5-2(c); this consists of a voltage source A 2 V s2 with equivalent output resistance R o2 . In Figure 5-2(e), the third stage is driven by this equivalent circuit shown as a voltage source V s3 with an associated source resistance R S3 , with V s3 = A 2 V s2 and R S3 = R o2 . Finally, in Figure 5-2(f), we construct a Thevenin equivalent circuit of the entire three-stage amplifier, shown as a voltage source A 3 V s3 in series with an equivalent output resistance R o3 . We now have a model of the entire three-stage circuit as a voltage amplifier. The basic voltage amplifier with open-circuit voltage gain A VSO and output resistance R o is shown again in Figure 5-3. Comparing this circuit with the circuit in Figure 5-2(f), it should be clear that A 3 V s3 = A VSO V s . Using the relations shown in Figure 5-2, one can write: A 3 V s3 = A 3 A 2 V s2 = A 3 A 2 A 1 V s so that A VSO = A 3 A 2 A 1 and finally (5.1b) (5.1a) RS Vs Ri Figure 5-3. A voltage-amplifier model. Ro AVSOVs Vo RL DRAFT 09:28 on 17 October 2006 5.1 Incremental Analysis of Multistage Amplifiers 5-3 R o = R o3 (5.1c) The net of this is that analysis of the three-stage amplifier in Figure 5-1 essentially reduces to the analysis of three isolated single-stage circuits. We thus ought to be able to use directly the results obtained in Chapter 4 for single-stage amplifiers. That this is indeed the case will be seen using the example of the CE-CC cascade mentioned at the outset. Before proceeding with the example, it should be pointed out that the input resistance of the three-stage amplifier, marked as R i on the voltage-amplifier model in Figure 5-3, cannot be found from the analysis outlined above. The input resistance can also be found by treating the individual stages in isolation, but starting from the last stage (stage 3 for the amplifier in Figure 5-1) and working backwards to the first stage. For many amplifier circuits of interest, the input resistance is simply equal to the input resistance of the first stage. Example 5.1 The circuit in Figure 5-4 is a CE-CC cascade. The two DC current sources shown are assumed to be ideal, with I CC1 = I EE2 = 1mA . The operating point for the devices is taken to be at I C1 = I C2 = 1mA . The devices both have β F = β o = 150 , r b = 100Ω , and V A = 100 . The circuit drives an external load R L = 1kΩ . and R S = 5kΩ . The incremental model for the circuit is shown in Figure 5-5, with g m1 = g m2 = 0.04A/V ; r π1 = r π2 = 3.75kΩ ; r o1 = r o2 = 100kΩ The first stage here is a CE stage, as in Figure 4-1 on page 4-1 but with R C → ∞ or as in Figure 4-5 on page 4-5 but with R I → ∞ . The open-circuit voltage gain and output resistance of the stage are given in Eqns. (4.1) and (4.3), respectively; these relations immediately give us the Thevenin equivalent circuit looking into the output of the first stage as in Figure 5-2(b): VCC ICC1 RS Q2 Ro Q1 IEE2 STAGE 1 STAGE 2 Vs Vo RL Ri Figure 5-4. A CE-CC cascade. STAGE 1 STAGE 2 RS Ii Vs Ri Figure 5-5. rb1 gm1Vπ1 rπ1 Vπ1 ro1 rb2 Vπ2 rπ2 gm2Vπ2 ro2 Ro Vo RL Vi Incremental model of the CE-CC cascade. DRAFT 09:28 on 17 October 2006 5-4 5 Multistage Amplifiers – g m1 r π1 r o1 A 1 = ---------------------------------R S + r b1 + r π1 R o1 = r o1 (5.2) The second stage is a CC stage that is driven by this Thevenin equivalent circuit, i.e. by a voltage source V s2 = A 1 V s in series with an equivalent resistance R S2 = R o1 . This is exactly the circuit in Figure 4-12 on page 4-12, but here with R E → ∞ . The open-circuit voltage gain and output resistance of this stage are given in Eqns. (4.11) and (4.13b), respectively. With the particulars of the Thevenin equivalent source that drives the stage here, we obtain the Thevenin equivalent circuit looking into the output of the second stage as in Figure 5-2(d): ( 1 + g m2 r π2 )r o2 A 2 = ----------------------------------------------------------------------------------R S2 + r b2 + r π2 + ( 1 + g m2 r π2 )r o2  R S2 + r b2 + r π2 R o2 =  ------------------------------------  || r o2  1 + g m2 r π2  (5.3) Using the specific values for the circuit in this example, we obtain A 1 = – 1695 R o1 = 100kΩ A 2 = 0.993 R o2 = 688Ω so that for the entire amplifier, following Eqns (5.1b) and (5.1c): A VSO = A 1 A 2 = – 1683 R o = R o2 = 688Ω The overall voltage gain with the load in place is now easily found by referring to Figure 5-3: Vo A VSL ≡ ----Vs  RL  = A VSO  ------------------  = – 997  R o + R L RL Note that A VSL for the CE stage driving the 1kΩ load directly is – 16.95 . Finally, consider the input resistance R i of the two-stage amplifier. In Figure 5-5, it will be seen that R i = V i ⁄ I i , at the input to the CE stage. Because the input resistance of the CE stage is simply r b1 + r π1 , independent of what is connected at the stage’s output, the input resistance of the two-stage amplifier is just that of the first stage, i.e. R i = r b1 + r π1 = 3.85kΩ 5.2 A Simple BJT Op Amp An op amp (or operational amplifier) is a multistage amplifier with very high gain (ideally infinite), high input impedance (ideally infinite), and low output impedance (ideally zero). The very high gain is made useful in practical applications through the use of negative feedback, which establishes the true gain of the circuit at a reasonable value such that it is essentially idependent of device parameters and their variation. Op amps generally have differential inputs and single-ended outputs, although circuits with differential ouputs are used in certain applications. In addition, op amps are direct-coupled, i.e. midband extends down to zero frequency, and with feedback applied the total output voltage is nominally zero when the total differential input voltage is zero. A stylized picture of an op amp is shown in Figure 5-6. The input and output voltages DRAFT 09:28 on 17 October 2006 5.2 A Simple BJT Op Amp 5-5 V+ vIDM vO V– Figure 5-6. A stylized picture of an op amp. The terminals labeled V+ and V– represent positive and negative power-supply voltages, each with respect to ground are indicated as total quantities in the figure to highlight the fact that their operating-point values are nominally zero. There is a “classical” op amp architecture that employs three stages: a differential input stage, a “gain stage” (CE or CS), and an output buffer (CC or CD). This section presents an analysis of a “simple” three-stage BJT op amp, shown below in Figure 5-7. The circuit is practical in that it can be built essentially as shown in the figure, assuming a complementary bipolar technology (i.e. with true vertical pnp transistors), and will function as an op amp. It is, however, suboptimum in may respects (that are unfortunately beyond the scope of the present discussion). The analysis to be presented deals first with biasing and then with incremental behavior. We will assume that all the npns are matched, with parameters identified with subscript ‘N’, and all pnps are matched, with parameters identified with subscript ‘P’. 5.2.1 Biasing analysis For the op amp in Figure 5-7, we are in a position, given the completeness of the circuit, to provide a complete biasing analysis. In fact, the biasing analysis is of great importance. Because the stages are direct-coupled, the operating points of the stages interact. In fact, the circuit architecture is such that the stages fit together in just the right way from a biasing perspective. Moreover, we need to verify that the operating-point value of the output voltage is in fact nominally zero. The operating point is defined at v S1 = v S2 = 0 . We will assume that the operating point of the input stage, i.e. the differential pair with active load, remains balanced with the rest of the circuit connected. Following the biasing analysis of the BJT differential pair with active load in Section 4.10.3, we have first for the differential pair: 1 I C1 = I C2 = –  -- α FP I EE 2  and for the active load:  β FN   α FP β FN 1 I C3 = I C4 = – I C1  ------------------  = -- I EE  -------------------  2  2 + β FN  2 + β FN  Then: (5.5) (5.4) DRAFT 09:28 on 17 October 2006 5-6 5 Multistage Amplifiers V+ iC6 iB6 IEE ICC Q6 RS vS1 vI1 iC1 iC2 Q1 Q2 RS vI2 vS2 iO vO Cx iC5 RL iC3 iC4 iB5 Q3 Q4 Q5 IEE6 V– Figure 5-7. A simple BJT op amp. 2I C3 I B5 = I B3 + I B4 = ---------β FN and I C5 = β FN I B5 = 2I C3 (5.6) It is worth recalling at this point that, in the discussion in Section 4.10.3, a DC voltage source was connected to the collectors of Q2 and Q4 so that the DC voltage from this node to ground would be set equal to the DC volatge from the collectors of Q1 and Q3 to ground. In the circuit in Figure 5-7, the DC voltage at the collectors of Q2 and Q4 is set by the connection to the base of Q5; because V BE is always about 0.6V for an npn BJT in the active region, the V BE of Q5 establishes the DC voltage at the collectors of Q2 and Q4 at essentially the desired value. Moreover, the current I X that flows away from this node in the circuit in Section 4.10.3 becomes naturally the base current of Q5 in the circuit in Figure 5-7. The one other point to be made here is that the analysis so far holds even if base-width modulation is taken into account, except for the equation on the right in (5.6). This is because the only place where collector currents are to be matched but where there is a potentially significant mismatch in V BC is between Q4 and Q5. Thus base-width modulation may cause β FN5 to differ slightly from β FN4 , which in turn may cause I C5 to differ slightly from 2I C3 . This possibility will be ignored here. Now, looking at the base current of Q6, we observe: I B6 = I CC – I C5 (5.7) Observe also that with I C5 = 2I C3 , the value of I C5 is approximately equal to but slightly less than that of I EE . If we choose I CC = I EE (which, by the way, is extremely easy to implement such that these two currents track with temperature), we find that I B6 is a small, positive current that may be just right as the base current of the device Q6 that acts as the CC output buffer. With this choice, we have: DRAFT 09:28 on 17 October 2006 5.2 A Simple BJT Op Amp 5-7 α FP β FN   2 + β FN ( 1 – α FP ) I B6 = I EE  1 – -------------------  = I EE  ------------------------------------------- 2 + β FN 2 + β FN     and  β FN  I C6 = β FN I B6 = I EE  ------------------  ( 2 + β FN ( 1 – α FP ) )  2 + β FN (5.8a) (5.8b) By this point, any attempt at matching becomes difficult, because of the term β FN ( 1 – α FP ) in Eqn. (5.8b). We can continue and write: 1 I O = I EE6 – I C6  1 + ---------  β  FN VO = –IO RL (5.9) What is desired is that I O = V O = 0 . Let’s “arbitrarily” take I EE6 = 3I EE and, by means of an example, see what the DC conditions are at the output. Example 5.2 For the devices in the circuit in Figure 5-7, β FP = 75 and β FN = 150 . Also, I EE = I CC = 200µA and I EE6 = 600µA . Using the equations above, we find: I C3 = I C4 = 97.4µA I C1 = I C2 = – 98.7µA I C5 = 194.8µA I C6 = 784.3µA I O = 189.5µA If R L = 1kΩ , then V O = – 189.5 mV . Thus there is a small but non-zero DC output current and a corresponding small but non-zero DC output voltage. The DC voltage that appears at the op amp output when its total input voltage is zero is called the output offset voltage. The offset voltage found in the example above is a structural offset, i.e. it is due to the structure of the circuit assuming that device matching is perfect. There is a second, statistical source of offset voltage that is due to imperfect matching of devices. In general, an op amp’s bias design is good if the structural offset is significantly smaller than the worst-case statistical offset. To understand the impact of the output offset voltage V O , one might ask the following question: what value of input voltage v IDM will cause the total output voltage to be zero? This value of input voltage is called the input offset voltage. One way to estimate the input offset voltage is using an incremental analysis. Because V IDM = 0 at the operating point, take v IDM to be purely incremental, i.e. v IDM = v idm . Also, write v O = V O + v o . If we have the overall voltage gain from v idm to v o , we can estimate the value of v idm that will result in v O = 0 . Note that we are treating DC voltages here as incremental quantities; however, they represent changes from the operating point, and so this is consistent with the incremental analysis. Note also that we could view these voltages as amplitudes at zero frequency (which is DC), so that we could use the notation V idm and V o just as easily as v idm and v o . DRAFT 09:28 on 17 October 2006 5-8 5 Multistage Amplifiers Ro1 GmdxVsdm Ro1 (a) A1Vsdm (b) Figure 5-8. Norton and Thevenin models of the differential-pair stage. Incremental analysis at midband We will first characterize the incremental behavior of the op amp in Figure 5-7 by constructing a Thevenin equivalent circuit looking into the amplifier output (not including the external load resistance). Thus we need the open-circuit voltage gain Vo A VSO ≡ ----------V sdm (5.10) RL → ∞ 5.2.2 and the output resistance R o . The op amp is a three-stage amplifier and can be analyzed using the method developed above in Section 5.1.1 and outlined in Figure 5-2. The first stage is an actively loaded differential pair. We have a transconductance model for this stage in Figure 4-30, and we will use this model with assumption that the common-mode transconductance is zero. The transconductance model is redrawn in Figure 5-8(a) and is converted to a Thevenin equivalent in Figure 5-8(b) to be consistent with the analysis outlined in Figure 5-2. From the results in Section 4.10.3, especially Eqns. (4.69) and (4.72), we have: – g m1 r π1 G mdx = ---------------------------------r b1 + r π1 + R S and clearly g m1 r π1 ( r o2 || r o4 ) A 1 = – G mdx R o1 = ------------------------------------------r b1 + r π1 + R S (5.12) R o1 = r o2 || r o4 (5.11) DRAFT 09:28 on 17 October 2006 5.2 A Simple BJT Op Amp 5-9 The equivalent circuit in Figure 5-8(b) is shown driving the incremental model of the rest of the amplifier in STAGE 2 Ro1 A1Vsdm rb5 gm5Vπ5 rπ5 Vπ5 ro5 rb6 STAGE 3 Vπ6 rπ6 gm6Vπ6 ro6 Ro Figure 5-9. Incremental model at midband of the three-stage BJT op amp. Vo RL Figure 5-9. Note that the subscripts on the device parameters shown in the figure, and also those in the two equations above, correspond to the device identifiers in the circuit in Figure 5-7. Following the analysis outlined in Figure 5-2, observe that the second-stage voltage gain, A 2 , is the voltage gain of a CE stage driven from a source resistance equal to R o1 . Using the standard results for a CE stage: – g m5 r π5 r o5 A 2 = -----------------------------------r b5 + r π5 + R o1 R o2 = r o5 (5.13) The third-stage voltage gain, A 3 , is the voltage gain of a CC stage driven from a source resistance equal to R o2 . Using the standard results for a CC stage: ( 1 + g m6 r π6 )r o6 A 3 = ----------------------------------------------------------------------------------R o2 + r b6 + r π6 + ( 1 + g m6 r π6 )r o6 We thus have for the overall gain and output resistance: A VSO = A 1 A 2 A 3 Example 5.2 (continued) In addition to the specification at the beginning of this example, the devices in the circuit in Figure 5-7 have V AN = 80V , V AP = 40V , and r bN = r bP = 0 ; and R S = 0 . The operating points for the devices have already been found. The element values in the incremental model are: g m1 = g m2 = 3.95mA/V g m3 = g m4 = 3.90mA/V g m5 = 7.79mA/V g m6 = 31.4mA/V The computed gains are: A 1 = 1071.4 A 2 = – 212 A 3 = 0.974 r π1 = r π2 = 19kΩ r π3 = r π4 = 38.5kΩ r π5 = 19.3kΩ r π6 = 4.78kΩ r o1 = r o2 = 405.3kΩ r o3 = r o4 = 821.5kΩ r o5 = 410.7kΩ r o6 = 102kΩ R o = R o3 (5.15)  R o2 + r b6 + r π6 R o3 = r o6 ||  ------------------------------------   1 + g m6 r π6  (5.14) DRAFT 09:28 on 17 October 2006 5-10 5 Multistage Amplifiers and R o3 = 2.68kΩ , so that: A VSO = – 2.21 ×10 5 R o = 2.68kΩ The gain found in the example is quite large in magnitude; however, the value is not unreasonable for an op amp. Note also that the gain is strongly dependent on the device parameters. Finally, with an external load resistance, the gain becomes:  RL  A VSL = A VSO  ------------------   R L + R o Example 5.2 (continued) With an external load R L = 1kΩ , the loaded gain is A VSL = – 6.01 ×10 . Note that the output resistance is such that the gain is reduced by almost a factor of four with this load. Nonetheless, the gain is still very large in magnitude. Finally, it is now possible to answer the question posed at the end of Section 5.2.1 regarding the input offset voltage. In this example, because R S = 0 , we have V idm = V sdm , and so V o = A VSL V idm with the external load connected. We had V O = – 189.5 mV . To force the total output voltage to zero, we need V idm such that V o = 189.5mV . With the computed value of A VSL , we find V idm = – 3.15 µV . In other words, an input voltage of 3.15µV will reduce the total output voltage to zero. Thus the structural input offset voltage is 3.15µV. In comparison, the worst-case statistical input offset voltage for a typical BJT op amp (and also for an op amp such as that shown in Figure 5-7) is on the order of 5mV. Clearly, the structural offset voltage in this circuit is insignificant. One might wonder, though, about the effect of an input offset voltage of 5mV. Reversing the analysis here, treating this as equivalent to V idm = 5mV , and applying the loaded voltage gaon found above yields an output offset voltage with a magnitude of 300V. In other words, a worst-case mismatch between devices in the circuit (especially between Q1 and Q2 and between Q3 and Q4) would appear to result in a DC voltage at the output with a magnitude of 300V; but this is surely larger in magnitude than any power supply voltage in the circuit and so is clearly not possible. What may actually happen, and what in fact almost always happens when an op amp is powered up without a feedback connection, is that the output latches up at either the positive supply voltage or the negative supply voltage. 5.2.3 Incremental analysis at high frequencies A complete high-frequency analysis of a three-stage circuit such as the op amp in Figure 5-7 is extremely complicated and difficult. We might claim, based on the analysis of the CC stage at high frequencies in Section 4.13, that its capacitances can be ignored because it bandwidth is likely to be so much greater than that of the rest of the circuit. We would still be left with the actively-loaded differential pair and the CE stage. 4 It turns out that for op-amp configurations such as that in Figure 5-7 the bandwidth of A VSL is essentially determined solely by the behavior of the CE stage. In fact, a capacitor is connected between the output and input of the CE stage specifically to insure that this stage contributes a dominant pole to A VSL , which in turn determined the bandwidth of A VSL ; this capacitor is shown as C x in Figure 5-7. Under the assumption that this in fact is the case, it is sufficient in finding the bandwidth to consider only the capacitances of the CE stage and C x and then to apply the Miller approximation to this stage. DRAFT 09:28 on 17 October 2006 5.2 A Simple BJT Op Amp 5-11 STAGE 2 Cx Ro1 A1Vsdm rb5 rπ5 Vπ5 Cµ5 Cπ5 g V m5 π5 ro5 Ccs5 Vo5 Ri6 Figure 5-10. Incremental model of the simple BJT op amp showing the capacitances associted with the CE stage. STAGE 3 rb5 Vπ6 rπ6 gm6Vπ6 ro6 Vo RL The incremental model of the circuit in Figure 5-7 including the capacitances of the CE stage and C x but no other capacitances is shown in Figure 5-10. One additional simplification that has been made in drawing the circuit in this figure is that C x is shown connected directly in parallel with C µ5 . In fact, the left hand end of C x should be connected to the left hand end of r b5 . However, because r b5 is small, the approximation associated with the representation of the circuit in Figure 5-10 is excellent at the frequencies of interest and greatly simplifies the circuit analysis. Applying the Miller approximation to the CE stage in Figure 5-10 results in the net capacitance C µ5 + C x being transformed to a capacitance C M1 that appears in parallel with C π5 , while C cs5 is replaced by an open circuit. The result is shown in Figure 5-11. Based on the derivation of the Miller approximation in Section 4.12.4, we should have: V o5  C M1 = ( C µ5 + C x )  1 – -------V π5     (5.16a) ω=0 It should be clear from looking at the circuit in Figure 5-10 at midband, i.e. with all the capacitances replaced by open circuits, or alternatively from Figure 5-9, that the gain ( V o5 ⁄ V π5 ) at midband depends on the net equivalent resistance through which the current g m5 V π5 flows, and that this equivalent resistance here is r o5 || R i6 . So we have: C M1 = ( C µ5 + C x ) [ 1 + g m5 ( r o5 || R i6 ) ] Observe that R i6 is the input resistance at midband of the CC stage, so that: (5.16b) STAGE 2 Ro1 A1Vsdm rb5 rπ5 Vπ5 ro5 gm5Vπ5 rb6 STAGE 3 Vπ6 rπ6 gm6Vπ6 ro6 Vo RL Cπ5 CM1 Figure 5-11. The circuit in Figure 5-10 transformed using the Miller approximation. DRAFT 09:28 on 17 October 2006 5-12 5 Multistage Amplifiers R i6 = r b6 + r π6 + ( 1 + g m6 r π6 ) ( r o6 || R L ) (5.17) We should thus expect that R i6 will be large, and we should also keep in mind that R i6 and so also C M1 will depend on the value of the external load resistance R L . Finally, the overall gain is a single-pole transfer function with pole frequency: 1 ω pM1 = ----------------------------------------------------------------------------[ ( R o1 + r b5 ) || r π5 ] ( C π5 + C M1 ) and with the upper-3dB frequency ω H equal to the pole frequency. Example 5.2 (continued) In the circuit shown in Figure 5-7, Q5 has f T = 2GHz and C µ5 = 40fF at its operating point. Given the value of g m5 already found, we obtain C π5 = 580fF . Take C x = 0 and consider first the case with the output open-circuited ( R L → ∞ ). Find: R i6 = 15.4MΩ C M1 = 124.7pF ω pM1 = 4.44 ×10 rad/s (70.7kHz) 5 (5.18) For the case with R L = 1kΩ , and still with C x = 0 , find: R i6 = 154.3kΩ C M1 = 35pF ω pM1 = 1.56 ×10 rad/s (248.8kHz) 6 It is interesting to note that the product of the midband gain magnitude and the pole frequency for the open-cir5 5 10 cuited case ( ( 2.21 ×10 ) ( 4.44 ×10 ) = 9.82 ×10 is approximately equal to the product of these quantities 4 6 10 for the case with R L = 1kΩ ( ( 6.01 ×10 ) ( 1.56 ×10 ) = 9.40 ×10 ). This is not a coincidence. Clearly, any non-zero value for C x will reduce the value of the pole frequency, and thus that of the upper-3dB frequency, for any load condition. With C x = 1pF and the output open-circuited, C M1 is increased to 3.24nF and the pole frequency is reduced to 2.73kHz. DRAFT 09:28 on 17 October 2006 6.1 A Feedback System Model 6-1 6 Introduction to Feedback Amplifiers 6.1 A Feedback System Model Before beginning to look at feedback amplifier circuits, it will be useful to consider the feedback system model shown in Figure 6-1. There is a tremendous body of knowledge that exists covering techniques for the analysis and design of feedback systems. If the structure of a feedback amplifier can be put in the form of the model in the figure, then these techniques can be applied with relative ease to the feedback amplifier as a feedback system. In the figure, the signals represented by X s , X i , X f , and X o can be either voltages or currents. Because the first three are connected to a summing element, they must all be the same, i.e. either they are all currents or they are all voltages. The element labeled ‘A’ provides the forward gain, while the element labeled ‘β’ provides the feedback from output to input.1 The overall input signal is X s . The signal X f is the feedback signal. The signal X i is the input signal to the forward gain element and is sometimes called the “error signal” in a feedback system. The gain of interest for the system in Figure 6-1 is from the overall input signal to the output and is denoted by A f . We have the following definitions and terminology: Xo A = open-loop gain = ----Xi Xf β = feedback factor = ----Xo Xo A f = closed-loop gain = ----Xs It should be evident from the figure and the definitions that: Xi = Xs – Xf Thus the closed-loop gain is found to be: A A f = --------------1 + βA (6.3) (6.1) X o = AX i X f = βX o (6.2) Xs Xi A Xo Xf β Figure 6-1. Block diagram of a feedback system. 1. It is unfortunate that we have a reuse of the symbol ‘β’ here, but this is the usual symbol for the feedback factor in a feedback system. DRAFT 09:28 on 17 October 2006 6-2 6 Introduction to Feedback Amplifiers The quantity βA that appears in the denominator of Eqn. (6.3) is called the loop gain or the return ratio, and is often denoted by the symbol ‘T’. One aspect of the importance of this quantity can be seen almost immediately from Eqn. (6.3). If T » 1 we have: A A 1 A f = --------------- ≈ ------ = -1 + βA βA β (6.4) In a feedback amplifier, the forward gain A is provided by the amplifier circuits (e.g. an op amp), while the feedback network that implements the feedback factor β is usually implemented by a passive network often containing only resistors. Eqn. (6.4) indicates that if T » 1 then the closed-loop gain becomes essentially independent of the amplifier itself and depends only on the values of passive components, which can be controlled as tightly as necessary. The physical significance of T as the “loop gain” can be seen from the block diagram in Figure 6-1. Consider a case with X s = 0 and the path between the output of the summing element and the input of the forward gain element broken. Now, inject a signal into the input of the forward gain element and measure the signal that is returned at the output of the summing element; the ratio of these two signals is – βA = – T . In other words, T is the negative of the gain around the loop measured in this way with the loop broken. Note from Eqn. (6.3) that if T is positive then A f < A . This is negative feedback and is the desired mode of operation. If T can be negative, we have a value for T fow which the denominator in Eqn. (6.3) iz zero and the closed-loop gain is infinite. This is positive feedback and is undesirable, and in fact disastrous, for amplifier applications. In fact, A and thus T are complex functions of frequency, so the comments in this paragraph apply, strictly speaking, only in midband where A and T are real. 6.2 Effects of Feedback Application of feedback affects amplifier performance in a variety of ways. Several of these are discussed in this section. 6.2.1 Gain variability We have already noted that if the loop gain is large then the closed-loop gain becomes independent of the open-loop gain. To see the effect of feedback on the variability of the gain, consider the following example. Example 6.1 Consider an amplifer with A = 1000 and β = 0.1 . Clearly, T = 100 and the closed loop gain is A A f = --------------- = 9.901 1 + βA while the ideal value for A f in the case of infinite loop gain is A f → ( 1 ⁄ β ) = 10 . If the value of A is doubled to 2000, the value of A f increases to 9.95. If the value of A is halved to 500, the value of A f is reduced to 9.80. Thus with T = 100 nominally, variation of A from one half to twice nominal causes the closed-loop gain to change by only –1% to +0.5%. It should be noted that A f varies monotonically with A, so long as the loop gain is positive. Often, the maximum value of A in any particular application can be assumed to be arbitrarily large, with only the mini- DRAFT 09:28 on 17 October 2006 6.2 Effects of Feedback 6-3 mum value of A being at issue in determining the variation of A f . For example, the nominal and minimum values of A f may be specifed for a design. One might then follow a very simple design procedure: 1. Select β equal to the inverse of the nominal value specified for A f . In other words, the “nominal” condition is taken to be that with A arbitrarily large. 2. Determine the minimum allowable value of A from the minimun value specified for A f by using ( A ) min ( A f ) min = ---------------------------1 + β ( A ) min 6.2.2 (6.5) Bandwidth If the open-loop gain A ( s ) is a single-pole transfer function with midband value A o and pole frequency ω o , so that Ao A ( s ) = --------------s 1 + -----ωo and β is real, it can be shown by substituting this expression into Eqn. (6.3) that the closed-loop gain is also a single-pole transfer function with: A fo A f ( s ) = ----------------s 1 + ------ω fo where Ao A fo = -----------------1 + βA o ω fo = ω o ( 1 + βA o ) (6.6b) (6.6a) According to Eqn. (6.6b), the effect of the feedback is to reduce the midband gain while increasing the bandwidth. Moreover, the gain-bandwidth product, i.e. the product of the midband gain and the bandwidth, remains unchanged, since from Eqn. (6.6b) it is clear that A fo ω fo = A o ω o . If the open-loop gain A ( s ) is a two-pole transfer function, the situation becomes more complicated. One can develop an expression for the poles of the closed-loop gain A f ( s ) , or one can employ a technique called root locus, which provides a graphical description of how the poles of the closed-loop gain move in the complex plane as the feedback factor β is varied. Either approach will show that, assuming the poles of A ( s ) are real, the poles of A f ( s ) are real for relatively small amounts of feedback but become complex as β becomes sufficiently large. Complex poles introduce peaking into the frequency response (recall the frequency response of the common-collector stage with a capacitive load shown in Figure 4-42(b)) and ringing into the time response; these phenomena are usually undesirable. As the applied feedback becomes arbitrarily large, so so the peaking and ringing. However, the poles of A f ( s ) remain in the left-half of the complex plane and so the overall response remains stable. If the open-loop gain has three or more poles, the situation becomes even more complicated, and general expressions for the poles of the closed-loop gain are extremely difficult or even impossible to obtain. How- DRAFT 09:28 on 17 October 2006 6-4 6 Introduction to Feedback Amplifiers ever, it is still possible to employ the root locus technique. This shows that as the amount of feedback is increased in a system with three or more open-loop poles, a point will almost certainly be reached at which one or more poles of the closed-loop response have crossed the imaginary axis and lie in the right-half of the complex plane. At this point the amplifier is unstable; in other words, it will generate signals on its own even when no input signal is present. An unstable amplifier is clearly useless as an amplifier. Essentially all practical amplifier circuits have at least three poles, so almost any real feedback amplifier can be potentially unstable. Instability is explicitly prevented by design in feedback amplifiers using a procedure called compensation, which is the process of placing the poles of the open-loop gain A ( s ) , or more generally those of the loop gain T ( s ) , such that the closed-loop poles remain in the left-half of the complex plane for the maximum expected amount of feedback. Compensation of feedback amplifiers is most often accomplished by establishing a dominant pole in A ( s ) that is much lower in frequency, by several orders of magnitude, than any other pole of A ( s ) . For op amps the most common form of compensation is the placement of a capacitor between the input and output of a stage with large negative voltage gain in the center of the amplifier (e.g. the capacitor C x between the input and output of the CE stage in the op amp circuit in Figure 5-7). The so-called “Miller effect” (associated with Miller’s theorem) permits a very small capacitance to establish a very low frequency dominant pole, and so this form of compensation is usually called Miller compensation. Some guidelines associated with compensation and ensuring stability are discussed in the next section. 6.3 Stability Considerations As indicated above, any real feedback amplifier may become unstable if the feedback factor β is made large enough. It will be important to be able to guarantee that an amplifier will remain stable, i.e. that the poles of the closed-loop gain A f ( s ) will remain in the left half of the complex plane, for its designed value of β, taking into account variations of device parameters and component values with temperature, process tolerances, and so on. The most common method for evaluating the stability of a feedback amplifier and for defining margins against instability is based on consideration of the log-magnitude and phase of the loop gain T ( s ) evaluated on the imaginary axis, i.e. with s = jω . 6.3.1 T(jω) and stability Consider the closed-loop gain evaluated on the imaginary axis: A ( jω ) A f ( jω ) = ----------------------1 + T ( jω ) (6.7) where T ( jω ) = βA ( jω ) , and β is assumed for our purposes here to be a real constant. If the closed-loop gain has a pole2 on the imaginary axis, say at s = jω o , then the denominator in Eqn. (6.7) must be zero at this point, so that T ( jω o ) = – 1 This can be rewritten in terms of the magnitude and phase of the loop gain: T ( jω o ) = 1 arg [ T ( jω o ) ] = – ( 2k + 1 ) 180° (6.8b) (6.8a) where k is an arbitrary integer3. In fact, one can make the following statement: 2. Of course, if the pole is not at the origin, there will actually be a complex-conjugate pole pair. 3. Recall that the phase of a complex quantity is determined only modulo 2π. DRAFT 09:28 on 17 October 2006 6.3 Stability Considerations 6-5 If there is a frequency ω o at which Eqns. (6.8b) are satisfied for the loop gain, then the closed-loop gain has a pole pair on the imaginary axis at s = ± jω o . Because T ( jω ) = βA ( jω ) , this statement and Eqns. (6.8b) can also be formulated in terms of β and the open-loop gain. Assuming that β is real, we can write: T ( jω ) = β A ( jω )  arg [ A ( jω ) ]; arg [ T ( jω ) ] =   arg [ A ( jω ) ] + 180 ° ; β>0 β<0 (6.9) Note from Eqns. (6.9) that the condition in (6.8b) on the magnitude of the loop gain depends on both the magnitude of the open-loop gain and the magnitude of β; in contrast, the condition in (6.8b) on the phase of the loop gain depends on the phase of the open-loop gain but only on the sign of β. Consider now the typical behavior of the loop gain of a feedback amplifier as a function of frequency; as an example, see the plots in Figure 6-2 below. At ω = 0 , the loop gain is real, positive, and usually large. With increasing frequency, the log-magnitude of the loop gain tends to decrease and the phase of the loop gain tends to become increasingly negative. There will be some frequency at which the log-magnitude of the loop gain first reaches 0dB; call this frequency ω 0dB . There will also be some frequency at which the phase of the loop gain first reaches – 180° ; call this frequency ω 180 . Clearly, if ω 0dB = ω 180 then by the rule stated above the closed-loop gain will have a pole pair on the imaginary axis at this frequency, and so the feedback amplifier will be unstable. This one case may seem not particularly interesting. However, with this as a starting point, it is possible to construct practical and reasonably general guidelines regarding stability based on the relative magnitudes of the frequencies ω 0dB and ω 180 and on the values of the log magnitude and phase of the loop gain at these frequencies. Consier the following: 1. From (6.9), the value of ω 180 depends only on the phase of the open-loop gain and not on the value of β, while the value of ω 0dB can be changed by changing the value of β. Moreover, because: Lm [ T ( jω ) ] = Lm ( β ) + Lm [ A ( jω ) ] (6.10) it can be seen that increasing the magnitude of β will increase the value of ω 0dB , while decreasing the magnitude of β will decrease the value of ω 0dB . 2. It can be shown that, for practical feedback amplifiers, increasing the magnitude of β will tend to move the critical pair of poles of the closed-loop gain to the right in the complex plane, while decreasing the magnitude of β will tend to move these poles to the left in the complex plane.4 Given the points noted above, consider a case with ω 0dB > ω 180 . In this case, we must have T ( jω 180 ) > 1 , because T ( 0 ) > 1 and ω 0dB is the frequency at which the log-magnitude of the loop gain first reaches 0dB. From (6.9), reducing the magnitude of β will reduce the magnitude of the loop gain without changing its phase. In fact, reducing the magnitude of β will reduce the value of ω 0dB without changing the value of ω 180 ; moreover, for an appropriately reduced magnitude of β the new value of ω 0dB can be made equal to that of ω 180 , so that for this reduced magnitude of β the closed-loop gain will have a pole pair on the imaginary axis at s = ± jω 180 . From point (2) above, reducing the magnitude of β has moved this pole-pair to the left in the complex plane. With can therefore conclude that at the starting point, i.e. with ω 0dB > ω 180 , the pole-pair was in the right-half of the complex plane and the closed-loop response was unstable. By reducing the magnitude of β further, we will have ω 0dB < ω 180 , and we will also have the pole-pair moved further to the 4. The “critical pair of poles” is the pair that is closest to the imaginary axis and that determines the stability of the closed-loop response. There are a few exceptions to the rule stated here, but they are not important for the discussion that follows. DRAFT 09:28 on 17 October 2006 6-6 6 Introduction to Feedback Amplifiers left into the left-half of the complex plane, so that the closed-loop gain is now stable. On this basis, we can state the following rule:5 • The closed-loop response will be stable if ω 0dB < ω 180 . We can go further and make some statements regarding the degree of stability we have in a design, or how close a design might be to becoming unstable, by considering the log magnitude and phase of the loop gain at the frequencies ω 0dB and ω 180 . We define the following: The phase margin M ϕ is defined to be the angle (in degrees) by which the phase of the loop gain at ω 0dB exceeds – 180° ; i.e. M ϕ = arg [ T ( jω 0dB ) ] + 180° (6.11) The gain margin M G is defined to be the value (in dB) by which the log magnitude of the loop gain at ω 180 is less than 0dB; i.e. M G = – Lm [ T ( jω 180 ) ] (6.12) The stability of a feedback amplifier is often quantified in terms of its phase margin and/or gain margin. A common design objective for a feedback amplifier is that its phase margin be at least 60° . In some cases, smaller values of phase margin may be acceptable. For a general purpose op amp with no specific application assumed, a design that achieves a phase margin of 90° with β = 1 may be required. Example 6.2 An amplifier has a three-pole open-loop response A ( s ) , Ao A ( s ) = ------------------------------------------------------------------------s s s  1 + --------   1 + --------   1 + --------   ω  ω  ω  p1 p2 p3 5 (6.13) with A o = 2 ×10 , f p1 = 200Hz , f p2 = 2MHz , and f p3 = 3MHz (and ω p1 = 2πf p1 , ω p2 = 2πf p2 , and ω p3 = 2πf p3 ). The amplifier is intended to be used in a feedback configuration such that A fo , the midband value of the closed-loop gain, is 4 (or 12dB). Extrapolating from Eqn. (6.4) and the discussion of the single-pole response in Section 6.2.2, we take the value of β from that of A fo using: 1 A fo ≈ -β so that β = 0.25 (and Lm ( β ) = – 12dB ). The log magnitude and phase of the open-loop gain A ( jω ) and the loop gain T ( jω ) = βA ( jω ) are plotted (versus f in Hz, with f = ω ⁄ 2π ) in Figure 6-2. Note that there is a constant difference of 12dB (6.14) 5. The reasoning used here leading to the rule to be stated is far from rigorous but is generally correct. The rule that is stated represents a sufficient condition for stability of the closed-loop response. DRAFT 09:28 on 17 October 2006 6.4 Feedback Amplifier Configurations 6-7 between the plot of Lm [ A ( jω ) ] and the plot of Lm [ T ( jω ) ] in the figure; this follows from Eqn. (6.10). Note also that the phase of A ( jω ) and the phase of T ( jω ) are identical, with no dependence on β. (more to come) 6.4 Feedback Amplifier Configurations We saw in Section 3.3 that there are four basic amplifier models: voltage, current, transconductance, and transresistance. There are four corresponding feedback amplifier configurations. With respect to the system model in Figure 6-1, the feedback configuration is defined by the output signal X o that is the input to the feedback network and by the feedback signal X f that is output from the feedback network and fed back to the amplifier input. For example, if X o is a current and X f is a voltage, then X s is also a voltage, the closed-loop gain A f is a transconductance, and the amplifier presumably is represented as a transconductance amplifier. In fact, there are many circuit details that do not appear in the system model in Figure 6-1. These include such features as input resistance and output resistance. They also include the means by which the output signal is “sampled” or “sensed” by the feedback network, and the means by which the feedbak signal is “summed” with the source signal to form the input to the forward gain element. There are two fundamental ways to “sample” or measure a signal in a circuit: (a) by shunt connection, and (b) by series connection. a) Measuring a signal using a shunt connection is measuring voltage. A feedback network that is connected in shunt at the amplifier output is sampling the output voltage; this connection is referred to as shunt sampling or voltage sampling. For an amplifier that uses voltage sampling, the output signal X o is a voltage. Moreover, the effects of feedback with voltage sampling will tend to make the output of the amplifier a better voltage source, by reducing the output resistance. b) Measuring a signal using a series connection is measuring current. A feedback network that is connected in series at the amplifier output is sampling the output current; this connection is referred to as series sampling or current sampling. For an amplifier that uses current sampling, the output signal X o is a current. Moreover, the effects of feedback with current sampling will tend to make the output of the amplifier a better current source, by increasing the output resistance. (dB) (deg) f (Hz) Lm(A) Lm(T) Lm(β) = –12dB arg(A) = arg(T) f (Hz) Figure 6-2. Log magnitude and phase of the open-loop gain and loop gain for Example 6.2. DRAFT 09:28 on 17 October 2006 6-8 6 Introduction to Feedback Amplifiers There are two fundamental circuit configurations that signals to be summed in a circuit: (a) by connection of voltages in a loop, or (b) by connection of currents at a node. a) Connection of voltages in a loop is a series connection. A feedback network whose output is connected in series with the amplifier input is feeding back a voltage from the amplifier output; this connection is referred to as series summing or voltage summing. For an amplifier that uses voltage summing, the feedback signal X f and source signal X s are voltages. Moreover, the effects of feedback with voltage summing will tend to make the input of the amplifier more ideal for connection to voltage sources, by increasing the input resistance. b) Connection of currents at a node is a shunt connection. A feedback network whose output is connected in shunt with the amplifier input is feeding back a current from the amplifier output; this connection is referred to as shunt summing or current summing. For an amplifier that uses current summing, the feedback signal X f and source signal X s are currents. Moreover, the effects of feedback with current summing will tend to make the input of the amplifier more ideal for connection to current sources, by reducing the input resistance. The two forms of output sampling and the two forms of input summing lead to four basic feedback amplifier configurations. We will look at two of them in the sections that follow by studying the two most common configurations of op amps with feedback. The analysis technique to be employed will be specific to these two configurations in the sense that it will be applied to the specific circuits rather than to generalized amplifier models. However, this technique and the results we will obtain from using it can be made more general and thus applicable to other feedback amplifier circuits and in particular to the two basic feedback amplifier configurations that will not be considered here. The analysis technique to be employed is driven by a desire to fit a circuit that includes resistances as well as independent and controlled sources into the mold defined by the system block diagram in Figure 6-1. For example, in the case of the voltage-sampling, voltage-summing configuration, this means: Given that the source signal X s is undoubtedly the source voltage connected to the amplifier and the output signal X o is undoubtedly the amplifier output voltage, identify a voltage that is the feedback signal X f , a voltage that is the forward amplifier input signal X i , a forward gain A, and a feedback factor β, such that these quantities are all related by Eqns. (6.1) and (6.2). The reason for fitting the circuit to the system block diagram, and thus for having to make these identifications, is that we can then take advantage of the powerful techniques that exist for the analysis and design of feedback systems. 6.5 Op Amps with Feedback The two feedback amplifier configurations that we will focus on in this chapter are the two most common op-amp feedback circuits. These are the non-inverting mode circuit, shown in Figure 6-3(a), and the RS Vs RL R2 R1 (a) Figure 6-3. RS Vo RL Vo Vs RF (b) The two basic op amp feedback configurations. (a) Non-inverting mode; (b) Inverting mode DRAFT 09:28 on 17 October 2006 6.6 The Op Amp with Non-Inverting Mode Feedback 6-9 Ro1 Vi1 Vo Vi1 Ri1 A1Vi1 Vo (a) Figure 6-4. (b) Op amp model to be used for analysis of the feedback configurations. inverting mode circuit, shown in Figure 6-3(b). These are analyzed in the following two sections. The incremental model that will be used for the op amp is shown in Figure 6-4. Note that this model is similar to the one developed for the simple BJT op amp that was considered in detail in Section 5.2. The one major difference is that the model in Figure 6-4(b) shows the gain relative to the differential input voltage rather than to the differential source voltage; i.e., it is an “intrinsic” model of the op amp that is independent of both source and load (recall the discussion in Section 3.3.5). While we did not in fact consider such models for multistage amplifiers, it turns out that they can be constructed for almost all op amp circuits of interest. Having an op amp model that in independent of the source configuration will be useful in the analysis that follows. 6.6 The Op Amp with Non-Inverting Mode Feedback An op amp with non-inverting mode feedback is shown in Figure 6-3(a). Referring to the figure, it can perhaps be seen that the feedback network is connected at the amplifier output in shunt, i.e. it is measuring the amplifier output voltage. It can also perhaps be seen that the output of the feedback network (the junction of resistors R 1 and R 2 ) is connected in a loop in series with the op amp input terminals and the voltage source V s . The configuration is indeed voltage-sampling and voltage-summing, and so according to the discussion above we should model it as a voltage amplifier. The circuit is redrawn in Figure 6-5(a) replacing the op amp with its incremental model from Figure 6-4(b). It is helpful to simplify the circuit as shown in Figure 6-5(b) using an approximation as follows. Assume that R 2 is much larger than the parallel combination of R o1 and R L . Then it would seem that the connection of the feedback network to the output of the amplifier does not load the output of the amplifier. What this means is that one can approximate the feedback network as being driven by an ideal voltage source equal to the output voltage V o ; this is what is shown in Figure 6-5(b). With this approximation, it becomes simple Ro1 Vi1 Ri1 A1Vi1 RL Vo Ro1 Vi1 Ri1 A1Vi1 RL Vo RS RS Vs Vs R2 R1 (a) Figure 6-5. Incremental model of the op amp with non-inverting feedback. R2 R1 Vo (b) DRAFT 09:28 on 17 October 2006 6-10 6 Introduction to Feedback Amplifiers RS Ro1 Ii Vs Vi Vi1 Ri1 A1Vi1 RL Vo Req Veq Figure 6-6. The circuit of Figure 6-5(b) with the feedback network replaced by a Thevenin equivalent circuit. to take a Thevenin equivalent circuit looking into the output of the feedback network, as shown in the figure. The result is shown in Figure 6-6, where:  R1  V eq = V o  ------------------  R 1 + R 2 R eq = R 1 || R 2 (6.15) We can now make the following observations. First, V eq is proportional to V o . Second, one can identify a voltage V i , as shown in the figure, such that V s = V i + V eq . So we can write the following:  R1  β =  ------------------  R 1 + R 2 V f = βV o = V eq V i = V s – V eq (6.16) It remains to find A = V o ⁄ V i , and then the closed loop gain A f = V o ⁄ V s . 6.6.1 Closed-loop gain With V i as shown in Figure 6-6, the open-loop gain is easily found. Note that: R i1   V i1 = V i  -----------------------------------  R S + R i1 + R eq so that: R i1    RL  A = A 1  -----------------------------------  ---------------------  R S + R i1 + R eq  R o1 + R L and with the feedback factor β as given in Eqn. (6.16), we simply have: A A f = --------------1 + βA Note in Eqn. (6.17) that the open-loop gain A is a function of the source and load resistances as well as of the op amp parameters. The feedback factor β, however, depends only on the elements in the feedback network. (6.17)  RL  V o = A 1 V i1  ---------------------  R o1 + R L DRAFT 09:28 on 17 October 2006 6.6 The Op Amp with Non-Inverting Mode Feedback 6-11 6.6.2 Input resistance The original non-inverting mode circuit in Figure 6-3(a) and the approximate incremental equivalent in Figure 6-6 are redrawn in Figures 6-7(a) and 6-7(b), respectively. The input resistance that the amplifier presents to the source V s is the input resistance with feedback, shown as R if in the figures. The quantity that is most easily related to the gain analysis presented above is the resistance shown in the figures as R if' ; this would be the input resistance with feedback with the source resistance R S considered to be part of the amplifier rather than part of the source. By definition, from Figure 6-7(b): Vs R if' = ----Ii (6.18) It should also be clear from the figure that R if and R if' are related by: R if' = R S + R if In addition, V i = I i ( R S + R i1 + R eq ) ; and: V s = V i + V eq = V i + βV o = V i + βAV i = V i ( 1 + βA ) Combining these relations yields: R if' = ( R S + R i1 + R eq ) ( 1 + βA ) (6.20) (6.19) Consider now the input resistance with the feedback disabled. Here, disabling the feedback is equivalent to setting β = 0 , so that V eq = 0 in Figure 6-7(b). We define: Vs R id' ≡ ---Ii Vi = ---- = R S + R i1 + R eq Ii (6.21) β=0 so that the resistance R id' is in fact the input resistance with the feedback disabled. Then, Eqn. (6.20) can be rewritten as: RS Ro1 Ii RS Vs RL Rif' Rif R1 (a) Figure 6-7. Vs Vo R2 Rif' Vi Ri1 Rif A1Vi1 RL Vo Req Veq (b) Finding the input resistance of the op amp with non-inverting mode feedback. DRAFT 09:28 on 17 October 2006 6-12 6 Introduction to Feedback Amplifiers R if' = R id' ( 1 + βA ) (6.22) In other words, the effect of the feedback on the input resistance of the circuit in Figure 6-7 is to increase it by the factor ( 1 + T ) . Specifically, this is the effect of the voltage-summing feedback connection at the amplifier input. As predicted in Section 6.4, the voltage-summing connection makes the amplifier more effective for connection to voltage sources by increasing its input resistance. Finally, the input resistance R if seen by the real voltage source can be found from Eqn. (6.19). Because R if' is usually much larger than R S , we also usually can take R if ≈ R if' . 6.6.3 Output resistance The output resistance of the op amp with noninverting mode feedback is indicated in Figure 6-8(a). The output resistance that is really of interest is that seen behind the external load, i.e. R of shown in the figure. The quantity that is most easily related to the gain analysis presented above is the resistance shown in the figure as R of' ; this would be the output resistance with feedback with the load resistance R L considered to be part of the amplifier rather than external to the amplifier. In Figure 6-8(b), the voltage source V s has been set to zero and a test source, the current source I x has been connected to the output to measure the output resistance. By definition from Figure 6-8(b): Vx R of' = ----Ix It should also be clear from the figure that R of and R of' are related by: R of' = R of || R L We now have V o = V x and V i = – V eq so that V i = – βV x and: – βV x R i1 V i1 = ----------------------------------R S + R i1 + R eq Writing a node equation at the output: Ro1 Ii (6.23) (6.24) (6.25) RS RS Vi1 Ri1 Vs RL R2 R1 (a) Figure 6-8. A1Vi1 Rof RL Ix Rof' Vx Vi Rof' Rof Req Veq (b) Output resistance of the op amp with noninverting feedback. The figure in (b) shows the measurement of the output resistance. DRAFT 09:28 on 17 October 2006 6.6 The Op Amp with Non-Inverting Mode Feedback 6-13 V x V x – A 1 V i1 A 1 V i1 1 1 I x = ----- + ------------------------- = V x  ----- + -------- – ------------R  R o1 RL R o1 L R o1 Substituting (6.25) into (6.26) yields: βA 1 R i1 Ix 1 1 ----- =  ----- + -------- + ------------------------------------------------R  ( R + R + R )R Vx L R o1 S i1 eq o1 or, using the expression for A in Eqn. (6.17): Ix 1 1 1 1 ----- =  ----- + -------- + βA  ----- + -------- R R Vx R o1 R o1 L L Inverting this to obtain R of' as defined in Eqn. (6.23), we can write the result as follows: ( R L || R o1 ) R of' = ------------------------1 + βA (6.26) (6.27a) (6.27b) (6.28) Consider now the output resistance with the feedback disabled. Again, disabling the feedback is equivalent to setting β = 0 , so that V eq = 0 in Figure 6-8(b). We define: Vx R od' ≡ ----Ix = R L || R o1 β=0 (6.29) so that the resistance R od' is in fact the output resistance with the feedback disabled. Then, Eqn. (6.28) can be rewritten as: R od' R of' = --------------1 + βA (6.30) In other words, the effect of the feedback on the output resistance of the circuit in Figure 6-7 is to decrease it by the factor ( 1 + T ) . Specifically, this is the effect of the voltage-sampling feedback connection at the amplifier output. As predicted in Section 6.4, the voltage-sampling configuration makes the amplifier a better voltage source by decreasing its output resistance. Finally, the output resistance R of seen inside the external load resistance can be found from Eqn. (6.24). Because R of' is usually much smaller than R L , we also usually can take R of ≈ R of' . Summary Overall, the noninverting-mode feedback has converted the op amp into an excellent voltage amplifier. The specific effects of the feedback are as follows: • The closed-loop voltage gain has been made essentially independent of the open-loop gain of the op amp and its variability due to temperature, process variations, etc. The closed-loop voltage gain has also been made independent of the source and load resistances. Instead, it depends entirely (to first order) on the resistances in the feedback network. • The input resistance is increased by the factor ( 1 + T ) . 6.6.4 DRAFT 09:28 on 17 October 2006 6-14 6 Introduction to Feedback Amplifiers • The output resistance in decreased by the factor ( 1 + T ) . 6.7 The Op Amp with Inverting Mode Feedback An op amp with inverting mode feedback was shown in Figure 6-3(a) and is redrawn in Figure 6-9(a). Referring to the figure, it can perhaps be seen that the feedback network is connected at the amplifier output in shunt, i.e. it is measuring the amplifier output voltage, exactly as for the non-inverting mode circuit discussed in Section 6.6. It can also perhaps be seen that the output of the feedback network (the left-hand end of resistor R f ) is connected to a node to which are also connected an input terminal of the op amp and the voltage source V s . This in turn would seem to imply that the input configuration is current-summing. That this is indeed the case may be more readily evident from the circuit in Figure 6-9(b), in which the voltage source has been replaced by its Norton equivalent circuit. The configuration is in fact voltage-sampling and current-summing, and so according to the discussion in Section 6.4 we should model it as a transresistance amplifier, i.e. the closed-loop gain will be A f = V o ⁄ I s , where I s = V s ⁄ R S . The circuit is redrawn in Figure 6-10(a), replacing the op amp with its incremental model from Figure 6-4(b); note the polarity of V i1 in the figures, given the ground at the non-inverting terminal of the op amp in Figure 6-9. Now, it is helpful to simplify the circuit as shown in Figure 6-10(b), just as was done for the non-inverting mode circuit, using an approximation as follows. Assume that R f is much larger than the parallel combination of R o1 and R L . Then it would seem that the connection of the feedback network to the output of the amplifier does not load the output of the amplifier. What this means is that one can approximate the feedback network as being driven by an ideal voltage source equal to the output voltage V o ; this is what is shown in Figure 6-10(b). With this approximation, it becomes simple to take a Norton equivalent circuit looking into the output of the feedback network, as shown in the figure. The result is shown explicitly in RS RL Vo Is RS Rf RL Vo Vs Rf Figure 6-9. An op amp with inverting mode feedback. In (b), the input voltage source Vs has been converted to its Norton equivalent circuit. (a) (b) Ro1 Is RS Ri1 Vi1 A1Vi1 RL Vo Is RS Ri1 Vi1 Ro1 A1Vi1 RL Vo Rf Rf Vo (a) Figure 6-10. Incremental model of the op amp with inverting mode feedback. (b) DRAFT 09:28 on 17 October 2006 6.7 The Op Amp with Inverting Mode Feedback 6-15 Figure 6-11(a), and with some rearrangement of the components in Figure 6-11(b). In the latter figure the current-summing is made particularly clear. Note that Vo I eq = ----Rf R eq = R f (6.31) We can now make the following observations. First, I eq is proportional to V o . Second, one can identify a current I i , as shown in Figure 6-11(b), such that I s = I i + ( – I eq ) . So we can write the following: 1 β = –  ----   R f I f = βV o = – I eq Ii = Is – If (6.32) It remains to find A = V o ⁄ I i , and then the closed loop gain A f = V o ⁄ I s . 6.7.1 Closed-loop gain With I i as shown in Figure 6-11(b), the open-loop gain is easily found. Note that: V i1 = – I i ( R S || R eq || R i1 ) so that:  RL  A = – A 1 ( R S || R eq || R i1 )  ---------------------  R o1 + R L and with the feedback factor β as given in Eqn. (6.32), we simply have: A A f = --------------1 + βA Note in Eqn. (6.33) that the open-loop gain A is a function of the source and load resistances as well as of the op amp parameters. The feedback factor β, however, depends only on the single resistance in the feedback network. Note also that both A and are β negative, so that T is positive. Ro1 Ii  RL  V o = A 1 V i1  ---------------------  R o1 + R L (6.33) Is RS Ri1 Vi1 A1Vi1 RL Vo Is Ieq Req RS Ri1 Vi1 Ro1 A1Vi1 RL Vo Req Figure 6-11. Ieq (a) (b) The inverting-mode circuit of Figure 6-10(b) with a Norton equivalent of the feedback path. The circuit in (b) is topologically equivalent to that in (a). DRAFT 09:28 on 17 October 2006 6-16 6 Introduction to Feedback Amplifiers Finally, we should recall the original circuit in Figure 6-9(a), driven by a voltage source. Most often, the actual gain of interest in ( V o ⁄ V s ) rather than ( V o ⁄ I s ) . Based on the transformation between Thevenin and Norton models for the source signal in Figure 6-9, we have Vo Af ----- = ----Vs RS Note also that the ideal value, i.e. for A → ∞ , of A f is 1 ( A f ) ideal = -- = – R f β so that we also have  V o  Rf  = –  -----   -----   V s  ideal  R S which is the familiar expression for the voltage gain of an op amp with inverting mode feedback. 6.7.2 Input resistance The original inverting mode circuit in Figure 6-9(a) and the approximate incremental equivalent in Figure 6-11(b) are redrawn in Figure 6-12. Note that there is a little rearrangement of the order of the parallel elements in the input circuit in Figure 6-12(b) compared with Figure 6-11(b); these two circuits are topologically equivalent, however. The input resistance that the amplifier presents to the source I s is the input resistance with feedback, shown as R if in the figures; this is also the input resistance that the amplifier presents to the voltage source V s in Figure 6-9(a) (see below). The quantity that is most easily related to the gain analysis presented above is the resistance shown in the figures as R if' ; this would be the input resistance with feedback with the source resistance R S considered to be part of the amplifier rather than part of the source. By definition, from Figure 6-12(b):  V i1 R if' = –  -------  Is  (6.36) (6.35b) (6.35a) (6.34) Ro1 RL Is RS Rif' Rif (a) Figure 6-12. Is RS Ieq Req Ri1 Vi1 A1Vi1 RL Vo Rf Rif' Rif (b) Finding the input resistance of the op amp with inverting mode feedback. DRAFT 09:28 on 17 October 2006 6.7 The Op Amp with Inverting Mode Feedback 6-17 It should also be clear from the figure that R if and R if' are related by: R if' = R S || R if In addition, V i1 = – ( I s + I eq ) ( R S || R eq || R i1 ) ; and: Is I s + I eq = I s – βV o = I s – βA f I s = I s ( 1 – βA f ) = --------------1 + βA Combining these relations yields: R S || R eq || R i1 R if' = --------------------------------1 + βA (6.38) (6.37) Consider now the input resistance with the feedback disabled. Here, disabling the feedback is equivalent to setting β = 0 , so that I eq = 0 in Figure 6-12(b). We define:  V i1 R id' ≡ –  -------  Is  = R S || R eq || R i1 β=0 (6.39) so that the resistance R id' is in fact the input resistance with the feedback disabled. Then, Eqn. (6.20) can be rewritten as: R id' R if' = --------------1 + βA (6.40) In other words, the effect of the feedback on the input resistance of the circuit in Figure 6-9 is to decrease it by the factor ( 1 + T ) . Specifically, this is the effect of the current-summing feedback connection at the amplifier input. As predicted in Section 6.4, the current-summing connection makes the amplifier more effective for connection to current sources by decreasing its input resistance. It is important to return to the original inverting mode circuit driven by a voltage source in Figure 6-9(a). This circuit and its equivalent driven by a current source are displayed again in Figures 6-13(b) and 6-13(a), RS RL Is RS Rif' Figure 6-13. RL Vo Rf Rif (a) Vs Rif'' Rif (b) Rf Input resistance of the op amp with inverting mode feedback driven by a Norton equivalent source (a) and a Thevenin equivalent source (b). respectively. The input resistance R if seen by the real voltage source in Figure 6-13(b) is the same as R if seen by the Norton equivalent of the source in Figure 6-13(a). This resistance can be found from R if' using Eqn. (6.37). Because R if' is usually much smaller than R S , we also usually can take R if ≈ R if' . It is sometimes DRAFT 09:28 on 17 October 2006 6-18 6 Introduction to Feedback Amplifiers also useful, however, to know the resistance indicated by R if'' in Figure 6-13(b). This resistance is clearly equal to: R if'' = R if' + R S Again, because R if' is usually much smaller than R S , we also usually can take R if'' ≈ R S . Finally, it is of fundamental importance to note that because the input resistance R if here is very small and not very large, the inverting mode circuit does not posess the property of being “a good circuit for connecting to voltage sources”. On the contrary, the voltage gain V o ⁄ V s is a strong function of the source resistance R S , as is clear in Eqns. (6.34) and (6.35b). In many applications, the resistance designated by R S in Figure 6-9 is assumed to be part of the feedback network, with the voltage source V s assumed to be ideal. Of course, no voltage source is truly ideal, and so in these cases the resistance designated by R S in Figure 6-9 will include the equivalent resistance of the voltage source in series with whatever resistance is explicitly included by design. 6.7.3 Output resistance The output resistance of the op amp with inverting mode feedback is defined exactly as for the non-inverting mode circuit as shown in Figure 6-8. The feedback configurations of the two circuits are the same at the output, i.e. both employ voltage sampling, but they are obviously different at the input, Nonetheless, the expression for output resistance of the inverting mode circuit is identical to that for the non-inverting mode circuit. With R of' defined to be the output resistance taking the load R L into account, consider: R od' ≡ R of' β=0 (6.41) = R L || R o1 (6.42) so that the resistance R od' is in fact the output resistance with the feedback disabled. Then it can be shown that: R od' R of' = --------------1 + βA (6.43) In other words, the effect of the feedback on the output resistance of the circuit in Figure 6-9 is to decrease it by the factor ( 1 + T ) . Specifically, this is the effect of the voltage-sampling feedback connection at the amplifier output. As predicted in Section 6.4, the voltage-sampling configuration makes the amplifier a better voltage source by decreasing its output resistance. Finally, the output resistance R of seen inside the external load resistance can be found from Eqn. (6.24). Because R of' is usually much smaller than R L , we also usually can take R of ≈ R of' . 6.7.4 Summary Overall, the inverting-mode feedback has converted the op amp into an excellent transresistance amplifier. The specific effects of the feedback are as follows: • The closed-loop transresistance has been made essentially independent of the open-loop gain of the op amp and its variability due to temperature, process variations, etc. The closed-loop transresistance has also been made independent of the source and load resistances. Instead, it depends entirely (to first order) on the resistance in the feedback network. DRAFT 09:28 on 17 October 2006 6.7 The Op Amp with Inverting Mode Feedback 6-19 • The input resistance is decreased by the factor ( 1 + T ) . • The output resistance in decreased by the factor ( 1 + T ) . DRAFT 09:28 on 17 October 2006 6-20 6 Introduction to Feedback Amplifiers DRAFT 09:28 on 17 October 2006 7.1 Structure of basic CMOS logic gates 7-1 7 CMOS Gates 7.1 Structure of basic CMOS logic gates The basic structure of CMOS logic gates is derived from that of the CMOS inverter (recall Figure 2-25 on page 2-25). This structure is shown in Figure 7-1. It consists of an array of NMOS devices, sometimes called the pull-down array, and an array of PMOS devices, sometimes called the pull-up array. The inputs to the gate are connected to both arrays, and the output is taken from the connection between the arrays. For those input conditions for which the output should be low (nominally at V OL = 0 ), there will be at least one path between the output and ground through ohmic NMOS devices, which “pulls the output down” to ground. For those input conditions for which the output should be high (nominally at V OH = V DD ), there will be at least one path between the output and V DD through ohmic PMOS devices, which “pulls the output up” to V DD . The following conditions must hold for static operation (i.e., for the inputs and output constant and not switching between states) of the structure in Figure 7-1: • For any state in which the output is pulled down through the NMOS array, there must be no path that is not an open circuit between the output and V DD through the PMOS array. • For any state in which the output is pulled up through the PMOS array, there must be no path that is not an open circuit between the output and ground through the NMOS array. If either of these conditions were violated, there would be states for which current would flow from V DD to ground, and the desired pull-up or pull-down would not work properly. As a consequence, we have the following for static operation, for every set of input conditions: 1. The drain current in every device is zero. 2. Every device is either ohmic or in cutoff, i.e. no device is saturated (because there is no operating point for a MOS transistor in saturation with i D = 0 ). 3. Any device that is ohmic operates with v DS = 0 (because the only operating point for a MOS transistor in the ohmic region with i D = 0 is at v DS = 0 ). VDD PMOS array inputs NMOS array output Figure 7-1. Basic structure of a CMOS logic gate. DRAFT 09:28 on 17 October 2006 7-2 7 CMOS Gates 7.2 A “Rule of Thumb” Given the considerations outlined above that govern the static operation of basic CMOS logic circuits, it is possible to state a rule of thumb that can be used in the analysis of these circuits. Consider a CMOS logic subsystem, of arbitrary complexity, powered from V DD and with nominal logic voltages V DD and ground. We might expect from the discussion above that the voltage to ground from any node in the circuit will be either 0 or V DD ; in particular this will be true for the voltage to ground from the gate of any device in the circuit. On this basis, the following rules can be used to make assumptions regarding the state of any device in the circuit for any set of logic levels at the inputs: • For an NMOS transistor, if the voltage from gate to ground is 0, the device is assumed to be off; if the voltage from gate to ground is V DD , the device is assumed to be ohmic with v DS = 0 . • For a PMOS transistor, if the voltage from gate to ground is 0, the device is assumed to be ohmic with v DS = 0 ; if the voltage from gate to ground is V DD , the device is assumed to be off. These rules are not perfect, but for the static CMOS logic circuit structures to be considered here, they lead to the correct assumptions almost always; and when they lead to an incorrect assumption, the resulting error is irrelevant. We’ll see an application of these rules in the next section. 7.3 A CMOS NOR gate Figure 7-2 shows a 2-input CMOS NOR gate. Also shown is the truth table for the gate assuming so-called positive logic, i.e. that V ( 0 ) = 0V and V ( 1 ) = V DD . Consider the first entry in the truth table, i.e. v A = v B = 0 . Let v Gn be the voltage to ground from the gate of device M n . Clearly, for this input condition we have v G1 = v G2 = v G3 = v G4 = 0 . Following the rule of thumb stated above, we will assume that M 1 and M 2 are off while M 3 and M 4 are ohmic with v DS = 0 . This apparent short circuit between V DD and the output provided through M 3 and M 4 results in v Y = V DD , which is indeed the correct output voltage according to the truth table. We can verify this condition by considering v GS and v GD for each device. The best way to proceed here is to try and confirm that the devices assumed to be off are indeed off, and in particular that there is an appropriate set of devices that are off VDD M4 NOR Truth Table vA 0 M3 vB 0 V DD 0 V DD vY V DD 0 0 0 0 V DD vY vB M1 vA M2 V DD Figure 7-2. A 2-input CMOS NOR gate and its truth table. Positive logic is assumed for the truth table. DRAFT 09:28 on 17 October 2006 7.4 Noise Margins 7-3 such that there is no path for any current to flow between the power supply and ground. For the circuit in Figure 7-2 with the specified input condition, clearly v GS1 = 0 and v GS2 = 0 , so both M 1 and M 2 are verified as being off. As a result, there is an open circuit between the output and ground through the NMOS array consisting of M 1 and M 2 , and thus there is no path for any current to flow in the circuit. This in turn forces the conclusion that if any of the other devices in the circuit has a v GS appropriate for conduction (e.g. v GS < V T for the PMOS devices), then such a device must be ohmic with i D = 0 and v DS = 0 . Referring again to the figure, since v B = 0 we have v GS4 = – V DD ; because we already know that i D4 = 0 , we now verify that M 4 is ohmic with v DS4 = 0 . With v A = 0 and v DS4 = 0 , we have v GS3 = – V DD ; because we already know that i D3 = 0 , we now verify that M 3 is ohmic with v DS3 = 0 . The assumptions made are now completely verified, as is the entry in the first row of the truth table. Consider now the second entry in the truth table, i.e. v A = 0 and v B = V DD . Clearly, for this input condition we have v G1 = v G3 = 0 and v G2 = v G4 = V DD . Following the rule of thumb stated above, we will assume that M 1 and M 4 are off while M 2 and M 3 are ohmic with v DS = 0 . In this case, the PMOS array is assumed to present an open circuit between V DD and the output as a consequence of the state of M 4 . The apparent short circuit between the output and ground provided through M 2 results in v Y = 0 , which is indeed the correct output voltage according to the truth table. We can verify this condition by again considering v GS and v GD for each device. We will again begin by attempting to confirm that the devices assumed to be off are indeed off, and in particular that there is an appropriate set of devices that are off such that there is no path for any current to flow between the power supply and ground. For the circuit in Figure 7-2 with the specified input condition, clearly v GS1 = 0 and v GS4 = 0 , so both M 1 and M 4 are verified as being off. As a result, there is indeed an open circuit between V DD and the output through the PMOS array consisting of M 3 and M 4 , and thus there is no path for any current to flow in the circuit. This in turn forces the conclusion that if any of the other devices in the circuit has a v GS appropriate for conduction, then such a device must be ohmic with i D = 0 and v DS = 0 . Referring again to the figure, since v B = V DD we have v GS2 = V DD ; because we already know that i D2 = 0 , we now verify that M 2 is ohmic with v DS2 = 0 , which in turn verifies the presence of the “pull-down” path from the output to ground through the NMOS array. Finally, we should consider M 3 . There is some difficulty here; because M 4 is off (and verified off), the voltage at the node between M 3 and M 4 is not easily determined, and so v GS3 is not easily determined. However, based on the verified state of M 2 , we have confirmed that v Y = 0 , and so we also know (refer to the figure again) that v GD3 = 0 . Clearly, M 3 cannot be ohmic! Since M 3 also cannot be in saturation (because i D3 = 0 ), we must have that M 3 is off. Here, the rule of thumb from Section 7.2 has made a mistake. However, the mistake is inconsequential. Because M 3 is in series with a device that is known to be off ( M 4 ), its state has no direct impact on the output voltage. 7.4 Noise Margins Noise margins for logic circuits are defined here with respect to the transfer characteristic of the basic inverter. Figure 7-3 shows the transfer characterisic for a standard CMOS inverter. The following voltages are defined with respect to this transfer function: • • • • V OH : This is the nominal value of the output voltage when the output is “high”. For the standard CMOS inverter, this is equal to V DD . V OL : This is the nominal value of the output voltage when the output is “low”. For the standard CMOS inverter, this is equal to zero. V IH : This is the minimum value of the input voltage that can be reliably interpreted as “high” and that will thus result in the output being “low”. V IL : This is the maximum value of the input voltage that can be reliably interpreted as “low” and that will thus result in the output being “high”. DRAFT 09:28 on 17 October 2006 7-4 7 CMOS Gates vO VOH slope = –1 slope = –1 VOL VIL VIH vI Figure 7-3. Inverter transfer characteristic showing voltages that define the noise margin. As noted, for the standard CMOS inverter V OH is equal to is equal to V DD , while V OL is equal to zero. The values of V IH and V IL are defined to be the values of the input voltage at which the slope of the transfer characteristic is equal to –1, as shown in Figure 7-3. Using these quantities, the noise margin in the high state, NM H , and the noise margin in the low state, NM L , can be defined as follows: NM H = V OH – V IH NM L = V IL – V OL (7.1) For the CMOS inverter, and for CMOS logic circuits derived from the inverter structure, the noise margins are relatively large and are also approximately equal. These are highly desirable properties. 7.5 Switching threshold of the CMOS NOR gate An important parameter associated with the static operation of CMOS logic circuits is the switching threshold V th , defined to be the input voltage, with all the inputs connected together, at which the output voltage and the input voltage are equal. For the CMOS 2-input NOR gate in Figure 7-2, we have: v A = v B = v Y = V th (7.2) The value of V th provides an indication of where with respect to input voltage the sharp transition occurs between the two output states, i.e. between the output low (nominally at 0) and the output high (nominally at V DD ). The switching threshold of the CMOS inverter can be found using the static analysis of the CMOS inverter presented in Section 2.4.3. Looking at the CMOS inverter circuit in Figure 2-25, it should be clear that with the input and output voltages being equal, both MOS transistors must be in saturation because each has v GD = 0 . Following the discussion in Example 2.6 and referring to the inverter’s transfer characteristic in Figure 2-28, we can see that V th = V IB . For the device parameters used in Example 2.6, it was found that V IB = 0.5V DD , so V th = 0.5V DD . This is the desired condition for the switching threshold, because it places DRAFT 09:28 on 17 October 2006 7.5 Switching threshold of the CMOS NOR gate 7-5 the sharp transition between the two output states halfway between the voltage levels for these states at the input. It can be shown that for the CMOS inverter the condition V th = 0.5V DD holds if:  k′W =  k′W ---------------- L N  L P and V TP = – V TN (7.3) where the ‘P’ and ‘N’ subscripts refer to the PMOS and NMOS devices, respectively. We can obtain the switching threshold for the 2-input CMOS NOR gate in Figure 7-2 without too much difficulty. This will lead to a condition on the geometry of the PMOS devices relative to that of the NMOS devices if it is desired that V th = 0.5V DD . We will assume that the two NMOS devices are identical and that the two PMOS devices are identical. Now, given that the two input voltages are equal and that these in turn are equal to the output voltage, as in Eqn. (7.2), devices M1, M2, and M3 must all be in saturation because they all have v GD = 0 . With respect to M4, observe that v GD4 = v GS3 with both inputs equal. Since v GS3 must be more negative than V TP (otherwise M3 would be off, in which case we could not have the output voltage equal to the input voltage), v GD4 is also more negative than V TP , and so M4 must be ohmic. Now, let i DD be the current flowing out of the power supply in Figure 7-2; clearly: i DD = – i D4 = – i D3 = i D1 + i D2 At the switching threshold: k′W i DD = i D1 + i D2 =  --------- ( V th – V TN ) 2  L N or i DD V th = V TN + -----------------k′W  ---------  L N For M3 we can write: 1 k′W i DD = – i D3 = --  --------- ( V th – V DD – v DS4 – V TP ) 2 2 L  P and for M4: v DS4 k′W i DD = – i D3 =  ---------  V th – V DD – V TP – ----------- v DS4  L  P 2  Some algebraic manipulation of Eqns. (7.6a) and (7.6b) yields: v DS4 4i DD ( V th – V DD – V TP ) 2 = 4  V th – V DD – V TP – ----------- v DS4 = ---------------- 2  k′W  ---------  L P (7.7a) (7.6b) (7.6a) (7.5b) (7.5a) (7.4) DRAFT 09:28 on 17 October 2006 7-6 7 CMOS Gates Taking the square root of the left-hand side and the right-hand side in Eqn. (7.7a), and keeping the negative square root to insure consistency of the result, find that: i DD V DD – V th + V TP = 2 -----------------k′W  ---------  L P (7.7b) Combining Eqn. (7.7b) with Eqn. (7.5b), the following is obtained for the switching threshold of the 2-input CMOS NOR gate in Figure 7-2: ξ V TN + ------ ( V DD + V TP ) 2 V th = ------------------------------------------------------ξ 1 + -----2  k′W -------- L P ξ = -----------------k′W  ---------  L N with (7.8) It can be seen from Eqn. (7.8) that V th = 0.5V DD if V TP = – V TN and ξ = 4 . Ordinarily, the value of k′ for the PMOS devices is about half that for the NMOS devices, because of the lower mobility of holes in a p-type channel compared with the mobility of electrons in an n-type channel. If all the devices have the same channel length, the channel width for the PMOS devices must then be eight times that for the NMOS devices in order to have ξ = 4 . 7.6 Switching Analysis of the CMOS Inverter In this section we will consider the switching analysis of the CMOS inverter shown in Figure 2-25 on page 2-25. In particular, we want to know how much time it takes for the output to change state in response to a change of state at the input; for example, given a transition at the input from 0 to V DD at time t = t o , how long does it take for the output voltage to decrease from V DD to a point where the output can be said to be in the low state? Clearly, this time interval is greater than zero, because of the presence of MOS transistor capacitances. Unfortunately, these capacitances are nonlinear functions of the device’s terminal voltages, and because we must consider switching from one extreme to the other of the inverter’s transfer characteristic incremental analysis is not appropriate. To deal with these capacitances, for hand analysis and also for highly simplified computer simulation, we make the following very simplistic but useful approximation: • All device capacitances of the inverter (or gate) under consideration, including the input capacitances of all gates with inputs connected to the output of this inverter (or gate), can be approximated by a single linear, lumped capacitance connected from the output of this inverter (or gate) to ground. • Given the above approximation, all MOS transistors in the inverter (or gate) under consideration are taken to be capacitance-free, i.e. they are described by the usual static nonlinear MOS transistor model. The CMOS inverter with capacitances can thus be viewed as shown in Figure 7-4, with a single linear capacitor, shown as C L in the figure, connected at the output. While the transistors are assumed to be capacitance-free, the analysis used in developing the transfer characteristic of the inverter in Section 2.4.3 is not directly applicable, because we now have current flowing in a load on the inverter. Referring to Figure 7-4, we write a node equation and also the terminal relation for the capacitor: i D1 + i D2 + i O = 0 dv O i O = C L -------dt (7.9) DRAFT 09:28 on 17 October 2006 7.6 Switching Analysis of the CMOS Inverter 7-7 VDD vGS2 M2 iD2 iO vGD iD1 vI vGS1 M1 vO CL Figure 7-4. A CMOS inverter with a load capacitance. Before proceeding with the analysis, some words are in order regarding how the time needed for the output to make a transition from one state to another is characterized. One approach is to consider rise and fall times of the output voltage, i.e. the rise time being the time for v O ( t ) to move from 0.1V DD to 0.9V DD when the input transition is from high to low, and the fall time being the time for v O ( t ) to move from 0.9V DD to 0.1V DD when the input transition is from low to high. A more common approach for CMOS logic circuits is to use the propagation delay times t PHL and t PLH defined as follows: • • t PHL : For an input transition from low to high, t PHL is the time from the point at which v I ( t ) is equal to 0.5V DD as the input rises to the point at which v O ( t ) is equal to 0.5V DD as the output falls. t PLH : For an input transition from high to low, t PLH is the time from the point at which v I ( t ) is equal to 0.5V DD as the input falls to the point at which v O ( t ) is equal to 0.5V DD as the output rises. Note that in the above discussion, it is assumed that V OL = V ( 0 ) = 0 and V OH = V ( 1 ) = V DD . 7.6.1 Input low-to-high transition Consider a step change in the input voltage from 0 to V DD at time t = t o , as shown in Figure 7-5. We vI(t) VDD to Figure 7-5. A low-to-high transition of the inverter input voltage. t will assume that the step is ideal, i.e. that the transition occurs in zero time and the step is perfectly vertical. DRAFT 09:28 on 17 October 2006 7-8 7 CMOS Gates Now, assume that the input has been at 0 for a very long time before t = t o , so that just before the input transition occurs the inverter has been in the steady-state with the input low. Thus, just before the transition occurs the output is at V DD . Call the instant just before the transition occurs (i.e., an infinitesimal amount of – time before t o ) t = t o . The circuit conditions at this time can be written as follows: v GS1 ( t o ) = 0 – v GS2 ( t o ) = – V DD – v O ( t o ) = V DD – v GD ( t o ) = – V DD – (7.10) noting that in the inverter circuit v GD1 = v GD2 = v GD ; and in addition: i D1 ( t o ) = 0 – i D2 ( t o ) = 0 – iO ( to ) = 0 – (7.11) Consider now the instant just after (i.e. an infinitesimal amount of time after) the input transition occurs, which + we will call t = t o . Clearly, we have: v GS1 ( t o ) = V DD + v GS2 ( t o ) = 0 + (7.12) Given that the transistors are assumed to be capacitance free, we must have that the PMOS device is off at + + t = t o , while the NMOS device should be conducting (ohmic or sat) at t = t o . For the NMOS device, we + must check v GD , and so we need to know v O ( t o ) . At this point, we invoke a basic property of the capacitor as a circuit element, namely: the voltage on a capacitor cannot change in zero time. In other words, we must have: vO ( to ) = vO ( to ) + + + – (7.13) Thus, v O ( t o ) = V DD , and so v GD ( t o ) = 0 ; as a result, the NMOS device is saturated (and not ohmic) just after the input transition occurs. Once we see this, we can proceed to describe the qualitative behavior of the circuit for t > t o as follows: • Immediately after the input transition, the PMOS device is off, the NMOS device is saturated, and the capacitor is discharged to ground through the NMOS device. While the NMOS device is saturated, its drain current, and thus the capacitor discharge current, is constant, because v GS1 remains constant. • While the capacitor is being discharged through the saturated NMOS transistor, the voltage on the capacitor is decreasing linearly with time. As this voltage decreases, v GD increases. A point will be reached, say at t = t 1 , at which v GD = V TN (where V TN is the threshold voltage of the NMOS transistor). At this point, the NMOS device is at the sat/ohmic boundary. • For t > t 1 , the NMOS device is ohmic. The capacitor continues to discharge through the NMOS transistor, but now it is through this transistor behaving as a nonlinear resistance in the ohmic region. This can now be made concrete. Given the definition of the time t 1 as the time at which the capacitor has discharged to the point that v GD = V TN , we can say that for t o < t ≤ t 1 the NMOS transistor is saturated, and its drain current can be written as: 1 k'W i D1 ( t ) = ( I D1 ) sat = --  -------- ( V DD – V TN ) 2 2 L  N to < t ≤ t1 (7.14) DRAFT 09:28 on 17 October 2006 7.6 Switching Analysis of the CMOS Inverter 7-9 Because the PMOS transistor is off, i D2 = 0 , and so i O ( t ) = – i D1 ( t ) . Thus we have the following simple differential equation for the output voltage in this time interval: dv O C L -------- = – ( I D1 ) sat dt Because ( I D1 ) sat is a constant, this equation is trivially integrated to yield: ( I D1 ) sat v O ( t ) = V DD – ------------------ ( t – t o ) C L (7.15) to ≤ t ≤ t1 (7.16) using the initial condition v O ( t o ) = V DD . We can now find t 1 . By definition, t 1 is such that v GD ( t 1 ) = V TN . Because v GS1 ( t 1 ) = V DD , we must have that v O ( t 1 ) = V DD – V TN . Substitution of this condition into Eqn. (7.16) yields:  CL  t 1 – t o =  ------------------ V TN  ( I D1 ) sat (7.17) Consider now t ≥ t 1 , with the NMOS transistor ohmic. We still have the PMOS transistor off, so we still have i D2 = 0 and i O ( t ) = – i D1 ( t ) . The drain current of the NMOS transistor satisfies the ohmic region characteristic: vO( t ) k'W i D1 ( t ) =  --------  V DD – V TN – ------------  v O ( t )  L  N 2  t1 ≤ t (7.18) given that v O = v DS1 . Substitution of this equation for i O ( t ) in the differential relation in Eqn. (7.9) results in a nonlinear differential equation, namely: dv O vO ( t ) k'W C L -------- = –  --------  V DD – V TN – ------------  v O ( t )  L  N dt 2  t1 ≤ t (7.19) As it happens, there exists a closed-form solution for this equation. To be able to write this solution conveniently, let us first recall that the incremental transconductance of the NMOS transistor in saturation with V GS1 = V DD is: k'W g M1 =  -------- V DD – V TN  L N Also, the ratio ( C L ⁄ g m1 ) has units of time, so we can define a time contant τ 1 as: CL τ 1 = -------g m1 (7.21) (7.20) Then the solution to the differential equation in Eqn. (7.19), with the initial condition v O ( t 1 ) = V DD – V TN , can be written as: DRAFT 09:28 on 17 October 2006 7-10 7 CMOS Gates 1 1 e v O ( t ) = 2 ( V DD – V TN ) ----------------------------------–( t – t1 ) ⁄ τ1 1+e –( t – t ) ⁄ τ t1 ≤ t (7.22) This equation can also be inverted; i.e., given a specific value of v O , with 0 < v O ≤ V DD – V TN , it is possible to find the value of t at which v O takes on this value. In particular: vO   t – t 1 = – τ 1 log  -----------------------------------------------  2 ( V DD – V TN ) – v O where log x is the natural logarithm. Example 7.1 In the CMOS inverter circuit in Figure 7-4, V DD = 3.3V and C L = 300fF . The devices have V TN = 0.8V , V TP = – 0.8V , and ( k'W ⁄ L ) N = ( k'W ⁄ L ) P = 640µA ⁄ V 2 . We are to find the proagation delay time t PHL , given an ideal low-to-high step at the input as in Figure 7-5. From the analysis above and the definition of t PHL , we can find this quantity as the difference t 2 – t o , where the input step occurs at t = t o , and t 2 is defined to be the time at which v O = 0.5V DD . First, we find t 1 , the time at which the NMOS transistor is at the sat/ohmic boundary. Note that ( I D1 ) sat = 2mA . Then, from Eqn. (7.17), we find that t 1 – t o = 120ps . It is worth noting that the rate of change of the output voltage during the linear discharge while the NMOS device is saturated is – ( I D1 ) sat ⁄ C L , which is equal to 6.67V/ns. Thus finding t 1 is equivalent to finding how much time it takes for the output voltage to fall by an amount equal to V TN at this discharge rate. To find t 2 , we use Eqn. (7.23) with v O = 0.5V DD = 1.65V ; the result is t 2 – t 1 = 133ps . Finally, t PHL = t 2 – t o = 120ps + 133ps = 253ps . A plot of the output voltage v O ( t ) for an input step occurring at t o = 100ps is shown in Figure 7-6. Input high-to-low transition Consider a step change in the input voltage from V DD to 0 at time t = t o , as shown in figy. As before, we will assume that the step is ideal, i.e. that the transition occurs in zero time and the step is perfectly vertical. The analysis now proceeds essentially as for the low-to high transition in Section 7.6.1. 7.6.2 (7.23) vI(t) VDD to Figure 7-7. A high-to-low transition at the inverter input. t DRAFT 09:28 on 17 October 2006 7.6 Switching Analysis of the CMOS Inverter 7-11 vO(t) t (ns) Figure 7-6. Inverter output voltage for Example 7.1. The vertical dashed line is at t = t 1 . The horizontal arrow indicates the tPLH interval for the example. Assume that the input has been at V DD for a very long time before t = t o , so that just before the input transition occurs the inverter has been in the steady-state with the input high. Thus, just before the transition – occurs, at t = t o , we have the following circuit conditions: v GS1 ( t o ) = V DD – v GS2 ( t o ) = 0 – vO ( to ) = 0 – v GD ( t o ) = V DD + – (7.24) and all the currents in the circuit are zero. Just after the input transition occurs, at t = t o , we have: v GS1 ( t o ) = 0 + + v GS2 ( t o ) = – V DD + + vO ( to ) = vO ( to ) = 0 + – (7.25) and so v GD ( t o ) = 0 . Thus, at t = t o the NMOS transistor is off, while the PMOS device is in saturation. The qualitative behavior of the circuit for t > t o can now be described, as it was for the input low-to-high transition: • Immediately after the input transition, the NMOS device is off, the PMOS device is saturated, and the capacitor charges to V DD through the PMOS device. While the PMOS device is saturated, its drain current, and thus the capacitor charging current, is constant, because v GS2 remains constant. • While the capacitor is charging through the saturated PMOS transistor, the voltage on the capacitor is increasing linearly with time. As this voltage increases, v GD decreases. A point will be reached, say at t = t 1 , at which v GD = V TP . At this point, the PMOS device is at the sat/ohmic boundary. DRAFT 09:28 on 17 October 2006 7-12 7 CMOS Gates • For t > t 1 , the PMOS device is ohmic. The capacitor continues to charge through the PMOS transistor, but now it is through this transistor behaving as a nonlinear resistance in the ohmic region. Now, for t o < t ≤ t 1 the PMOS transistor is saturated, and its drain current can be written as: 1 k'W i D2 ( t ) = ( I D2 ) sat = – --  -------- ( – V DD – V TP ) 2 2 L  P to < t ≤ t1 (7.26) Because the NMOS transistor is off, i D1 = 0 , and so i O ( t ) = – i D2 ( t ) . Thus we have the following simple differential equation for the output voltage in this time interval: dv O C L -------- = – ( I D2 ) sat dt Because ( I D2 ) sat is a constant, this equation is trivially integrated to yield: – ( I D2 ) sat v O ( t ) = --------------------- ( t – t o ) CL using the initial condition v O ( t o ) = 0 . We can now find t 1 . By definition, t 1 is such that v GD ( t 1 ) = V TP . Because v GS2 ( t 1 ) = 0 , we must have that v O ( t 1 ) = – V TP . Substitution of this condition into Eqn. (7.28) yields:  CL  t 1 – t o =  ------------------ V TP  ( I D2 ) sat noting that both ( I D2 ) sat and V TP are negative. Consider now t ≥ t 1 , with the NMOS transistor ohmic. We still have the NMOS transistor off, so we still have i D1 = 0 and i O ( t ) = – i D2 ( t ) . The drain current of the PMOS transistor satisfies the ohmic region characteristic: v DS2 ( t ) k'W i D2 ( t ) = –  --------  – V DD – V TP – ------------------ v DS2 ( t )  L  P 2  t1 ≤ t (7.30) (7.29) (7.27) to ≤ t ≤ t1 (7.28) and v O = V DD + v DS2 . Substitution of this equation for i O ( t ) in the differential relation in Eqn. (7.9) results in the nonlinear differential equation dv O v O ( t ) – V DD k'W C L -------- =  --------  – V DD – V TP – -----------------------------  ( v O ( t ) – V DD )   L  P dt 2 This equation can be rewritten as a differential equation in v DS2 ( t ) : dv DS2 v DS2 ( t ) k'W C L -------------- =  --------  – V DD – V TP – ------------------ v DS2 ( t )  L  P dt 2  t1 ≤ t (7.31b) t1 ≤ t (7.31a) DRAFT 09:28 on 17 October 2006 7.7 Power Dissipation 7-13 This is the same nonlinear differential equation as in Eqn. (7.19), with ( V DD – V TN ) replaced by ( – V DD – V TP ) . Therefore, the solution to Eqn. (7.31b) can be written in exactly the same way as that to Eqn. (7.19). First, use: k'W g m2 =  -------- – V DD – V TP  L P Then, following Eqn. (7.19): 1 2 e v DS2 ( t ) = 2 ( – V DD – V TP ) ----------------------------------–( t – t1 ) ⁄ τ2 1+e CL τ 2 = -------g m2 (7.32) –( t – t ) ⁄ τ t1 ≤ t (7.33) and since v O = V DD + v DS2 , this solution can be rewitten in terms of v O ( t ) : 1 2 e v O ( t ) = V DD – 2 ( V DD + V TP ) ----------------------------------–( t – t1 ) ⁄ τ2 1+e –( t – t ) ⁄ τ t1 ≤ t (7.34) Finally, an equation analogous to Eqn. (7.23) can be developed from Eqn. (7.34) that will give the value of t – t 1 for a given value of v O (so long as v O ≥ v O ( t 1 ) = – V TP . 7.7 Power Dissipation There are two types of power dissipation in CMOS logic circuits: 1. dynamic power: This is associated with gates switching from one state to another. Dynamic power itself consists of two components: (a) power associated with charging and discharging device and load capacitances (the switching discussed in the preceding section); and (b) a “switch-through” power associated with current flowing through PMOS and NMOS devices in series between V DD and ground because of the non-zero rise time of input step waveforms. 2. static power: This power is due to leakage currents flowing in devices that are nominally off. The leakage is associated with subthreshold conduction, and becomes significant only in the latest technology generation (90nm minimum drawn gate length) because of the low device threshold voltages. In the discussion that follows, we will be concerned only with dynamic power, and in particular only with that component of the dynamic power associated with charging and discharging device and load capacitances. This dynamic power has historically been the most important, perhaps even the only important, component of the power dissipated in CMOS logic circuits. It turns out that, for CMOS logic circuits built using the structure shown in Figure 7-1, a very simple and generally applicable expression can be derived for the dynamic charge/discharge power. DRAFT 09:28 on 17 October 2006 7-14 7 CMOS Gates VDD iDD PMOS array inputs NMOS array vO CL Figure 7-8. A generic CMOS logic gate with a load capacitance. The circuit structure in Figure 7-1 is redrawn in Figure 7-8, with the addition of a load capacitance. As with the switching analysis of the CMOS inverter in the preceding section, all the device capacitances are represented by a single equivalent linear capacitance at the output of the circuit. We will estimate the average power provided to the circuit by the V DD power supply to charge and discharge the load capacitance. To do this, we will assume that the gate’s inputs are arranged in such a way that output voltage is periodic, say with period T. An idealized periodic output waveform is shown in Figure 7-9. A less ideal version of this waveform would have the output at 0 at t = t o ; the output then rises toward V DD and reaches V DD by t = t o + t A ; the output then falls toward 0 and reaches 0 by t = t o + T ; and the process repeats periodically with period T. Note that during the interval from t = t o to t = t o + t A , the load capacitor charges through the PMOS array; during this interval, given the principles of operation of logic gates with the structure in Figure 7-1, the NMOS array is an open circuit. Note also that during the interval from t = t o + t A to t = t o + T , the load capacitor discharges through the NMOS array, while the PMOS array is an open circuit. Now, noting that the current provided to the circuit by V DD is i DD ( t ) , the average power is: to + T 1 P av = -T ∫ to V DD i DD ( t ) dt (7.35) Now, i DD ( t ) can be non-zero only during the interval when the capacitor is charging toward V DD . During the discharge interval, the PMOS array is an open circuit and so i DD ( t ) = 0 . Moreover, during the charging interval, i DD ( t ) is the charging current, because the NMOS array is an open circuit; so during this interval: vO(t) VDD to Figure 7-9. A periodic output waveform. to+tA to+T t DRAFT 09:28 on 17 October 2006 7.8 A More General Switching Analysis 7-15 dv O i DD ( t ) = C L -------dt Thus the equation for average power can be rewitten as: C L V DD P av = ----------------T to + tA ∫ to C L V DD dv O t +t -------- dt = ----------------- [ v O ( t ) ] o A dt T to (7.36) Since v O ( t o ) = 0 and v O ( t o + t A ) = V DD , and using f = 1 ⁄ T , the frequency of the periodic output waveform, we have the following very simple result: 2 P av = C L V DD f (7.37) 7.8 A More General Switching Analysis The switching-time analysis of the CMOS inverter presented above in Section 7.6, while introducing a dramatic simplification with respect to device capacitances, maintains the static nonlinear behavior of the devices. This is useful for several reasons; for example, we see how the NMOS device while it discharges the load capacitance and the PMOS device while it charges the load capacitance move from saturation into the ohmic region as the output voltage changes after the input step has occurred. Having made the approximation that the effects of all the nonlinear device capacitances can be modeled using a single linear capacitance loading the inverter output, it seems reasonable to ask if the effects of the static nonlinear behavior of the devices can be approximately modeled using a single linear resistance for each device. This would lead to an equivalent circuit for the inverter as shown in Figure 7-10. In the figure, R eqN is the linear resistance approximating the nonlinear static behavior of the NMOS device, and R eqP is the linear resistance approximating the nonlinear static behavior of the PMOS device. When the inverter input is high and the capacitance C L charges through the PMOS device, the switch at the top in the figure (associated with the PMOS device) is closed and the switch at the bottom in the figure (associated with the NMOS device) is open. Similarly, when the inverter input is low and the capacitance C L discharges through the NMOS device, VDD ReqP iD2 iD1 iO ReqN vO CL Figure 7-10. A linear equivalent circuit for approximate switching analysis of the CMOS inverter. DRAFT 09:28 on 17 October 2006 7-16 7 CMOS Gates the switch at the top in the figure is open and the switch at the bottom in the figure is closed. Assuming that estimates for R eqN and R eqP can be obtained from values of the device parameters and V DD , the switching time analysis is reduced to solving two single-time-constant circuits: the load capacitance charges with time constant R eqP C L and discharges with time constant R eqN C L . Close examination of the switching analysis in Section 7.6 will show that the time required to reach any particular value of output voltage, starting from the time at which the input step occurs, is proportional to C L and is inversely proportional to ( k'W ⁄ L ) P for the capacitor charging or to ( k'W ⁄ L ) N for the capacitor discharging. For the approximate model in Figure 7-10 to maintain this behavior, we need R eqN to be inversely proportional to ( k'W ⁄ L ) N and R eqP to be inversely proportional to ( k'W ⁄ L ) P . In fact, even when short-channel effects, which are needed to accurately describe device behavior with today’s submmicron CMOS technologies, are taken into account, it is still possible to construct estimates1 for R eqN and R eqP such that R eqN varies inversely with ( k'W ⁄ L ) N and R eqP varies inversely with ( k'W ⁄ L ) P . Given the above, it is possible to develop design guidelines for sizing devices in CMOS logic gates. One fundamental design objective to be met is that the transition times from low to high and from high to low should be about equal. After all, it is the larger of the two transition times that will determine the upper bound on the speed at which the circuit can be clocked (i.e. the rate at which the input logic level can change). For the inverter, it should be clear that to satisfy an objective that t PHL = t PLH we need R eqN = R eqP and thus also ( k'W ⁄ L ) N = ( k'W ⁄ L ) P . Because the value of k' for a PMOS device is typically about half that for an NMOS device (because of the difference between effective mobility for holes and effective mobility for electrons), we set W P = 2W N to meet the transition-time objective. The sizing guidelines outlined above can be applied to more complex CMOS logic circuits. Consider the 2-input NOR gate in Figure 7-2. A circuit model for this gate using linear resistances to approximate the static nonlinear device behavior is shown in Figure 7-11. Comparing the circuit in this figure with the that in VDD ReqP ReqP ReqN iO ReqN v O CL Figure 7-11. A linear equivalent circuit for approximate switching analysis of the CMOS 2-input NOR gate. 1. It should be noted that for short-channel devices with velocity saturation a dominant effect, factors other than k’ need to be taken into account. The equivalent resistances remain inversely proportional to (W/L). However, the width ratios turn out to be somewhat different for reasons beyond the scope of the present discussion.b DRAFT 09:28 on 17 October 2006 7.8 A More General Switching Analysis 7-17 Figure 7-2, it should be clear how each resistor+switch element represents one of the devices in the gate. Consider now a switching-time analysis of the 2-input NOR gate using the equvalent circuit in Figure 7-11. For a low-to-high transition at the output, the load capacitance must charge through the two PMOS devices in series, with both inputs to the gate being low. Thus the transition time t PLH will be proportional to the time constant 2R eqP C L . For a high-to-low transition at the output, the situation is a little more complicated, because there are three possible input states that will cause this transition, starting from the state with both inputs low: (a) one input goes high; (b) the other input goes high; (c) both inputs go high. The first two of these are identical, in that in either case the transition time t PHL will be proportional to the time constant R eqN C L . In the third case, however, the time constant will be ( R eqN ⁄ 2 )C L , and so the value of the transition time t PHL will be half that for the first two cases. In terms of defining a design objective, what counts is the worst-case transition time over all possible input state transitions. Essentially, we would like the maximum value of t PLH over all possible input state transitions that result in a low-to-high output transition to be equal to the maximum value of t PHL over all possible input state transitions that result in a high-to-low output transition. For the NOR gate modeled in Figure 7-11, there is only one input state transition that results in a low-to-high output transition, for which the time constant is 2R eqP C L as noted above. Also, there are three input state transitions that result in a high-to-low output transition, for which the ones with the maximum t PHL have time constant R eqN C L . Thus the design objective for the 2-input NOR gate is R eqN = 2R eqP . Given the difference between the value of k' for the PMOS device and that for the NMOS device noted above, the device sizing for the 2-input NOR gate should satisfy W P = 4W N . DRAFT 09:28 on 17 October 2006