Duke ECE 163 Lab Manual

Lab Manual for Integrated Electronic Circuits ECE 163 Jeff H. Derby Dept. of Electrical and Computer Engineering Duke University ii Copyright © 2004, 2002 by Jeffrey H. Derby. All rights reserved. DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual 1-1 Experiment 1: Frequency-Domain and Time-Domain Measurements on RC Networks The purpose of this experiment is to provide a review of frequency-domain and time-domain measurements on simple RC networks, in particular low-pass and high pass filters. In addition, use of the following instruments is introduced or reviewed: • • • • Function Generator Digital Multimeter Oscilloscope Network Analyzer PREPARATION The only advance preparation for this experiment is to glance through the operating manual for any of instruments listed above with which you are unfamiliar, and to read the overview of the HP 3577A Network Analyzer contained in Appendix A. Note the distinction in the sequel between v i as a waveform, i.e. a function of time, and V i as the amplitude or rms value of a single-frequency sine wave (and similarly for v o and V o ). PROCEDURE The low-pass and high-pass filters to be examined in this experiment are shown in Figure 1-1. In each network, C = 0.01µF and R = 10kΩ . Measure the value of R with the multimeter and the value of C with the capacitance meter. 1. Obtain a 100Hz sine wave from the function generator, with a 2.828V peak-to-peak signal level. Check the frequency and output signal level with the oscilloscope. a. Make the final adjustment of the function generator output with the multimeter (on AC Volts) to obtain a reading of 1Vrms. Verify the signal frequency using the counter. b. Use the function generator output as v i into the low-pass network. Connect the multimeter (still set to AC Volts) to the output of the low-pass network and record its reading as the rms output voltage V o . c. Without changing the output signal level, vary the sine wave frequency to 1, 2, 4, 8 ×10 Hz , n = 2, 3, 4 and finally to 100kHz. Record the rms output voltage V o at each frequency using the multimeter. d. Repeat the above steps using the function generator output as v i into the high-pass network. n R vi C vo (a) (b) C vi R vo Figure 1-1. Low-pass and high-pass RC networks. (a) Low-pass. (b) High-pass. DRAFT 22:1 on 24 January 2005 1-2 Experiment 1: Frequency-Domain and Time-Domain Measurements on RC Networks e. Compute and plot the log-magnitude in dB of the responses ( V o ⁄ V i ) for both networks on the same sheet of three-cycle semilog graph paper (or the equivalent using a computer plotting tool). Recall that  V o Vo Log Magnitude  -----  = 20log 10 ----- (dB) Vi  Vi  Make sure you have rms values for both input and output voltages, with measurements taken using the multimeter (measuring AC volts). 2. You will now measure the frequency response of the two networks using the network analyzer. As you should have seen from reading the description in Appendix A, this instrument incorporates the equivalent of both the sine-wave generator and the voltmeter that you used in the previous part. Make sure that the network analyzer is powered up. Note the functions of the various “hard-keys” on the front panel, and the manner in which they alter the functions of the “soft-keys” to the right of the CRT display. Adjust the frequency setting for a logarithmic sweep from 100Hz to 100kHz. Set the output level to – 25dBV . Make sure that the receiver settings for all three input channels (R, A, and B) are for 1MΩ input impedance, with the 20dB attenuators in. Also, you should be using 10X attenuating oscilloscope probes on the analyzer inputs; these will in the absolute voltage values indicated on the analyzer to be 20dB below (i.e., reduced by a factor of ten from) the actual values in the circuit, but the gain values indicated on the analyzer will be correct. a. Connect the analyzer output as v i into the low-pass network, the analyzer R input to measure v i , and the analyzer A input to measure v o (see Figure 1-2). b. Use the “Input” keys on the front panel to display the log magnitude of R and A in dBV. Note that 0dBV = 1Vrms. c. Now display the log magnitude and phase of ( A ⁄ R ) , which is the transfer function of the network. Make hard-copy plots of these quantities, following the instructions in the description of the network analyzer. Use the marker control keys on the front panel to locate precisely the frequency at which the log magnitude response is 3dB below its passband (or “midband”) value. d. Now connect a resistor R X with value 20kΩ between the network analyzer output and the low-pass network input, and reconnect the analyzer A and R inputs to the network, as shown in Figure 1-3. Display the log magnitude and phase of ( A ⁄ R ) and make hard-copy plots of these quantities. Use the marker controls to obtain the values of the log magnitude and phase of ( A ⁄ R ) at the frequencies 100Hz, 1kHz, 10kHz, and 100kHz, and record these values (do not estimate values from the plots; use the marker and read the explicit values displayed on the screen). Use these values to compute the input impedance Z in on the network at the four measurement frequencies with the following relation: R analyzer output to 'R' input C to 'A' input (a) Figure 1-2. C analyzer output (b) to 'R' input R to 'A' input Network analyzer connections for transfer function measurements. (a) low-pass; (b) high-pass. DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual 1-3 Zin RX analyzer output to 'R' input (a) Figure 1-3. Zin R to 'A' input C analyzer output RX to 'R' input (b) to 'A' input C R Network analyzer connections for input impedance measurements. (a) low-pass; (b) high-pass. The input impedance is indicated to the right of the arrows labeled Zin. RX Z in = -----------------------1 --------------- – 1 (A ⁄ R) Use a measured value of R X in your computation, recall that ( A ⁄ R ) is a complex quantity, and represent the values of Z in in terms of magnitude and phase. e. Repeat the above steps for the high-pass networks. 3. Set up the function generator to produce a square-wave output waveform with a period T = 1.0msec . Note the relationship between this value for the waveform period and the time constant τ of the RC networks. a. Use the square-wave output from the function generator as v i into the high-pass and low-pass networks. Observe and sketch the output waveforms from each network. Set the oscilloscope vertical gain to obtain the maximum height waveform, and set the time base to obtain more than one cycle but less than two cycles of the waveform on the screen. Obtain a print of the oscilloscope display. b. Measure the rise-time of the low-pass network, defined to be the time it takes the waveform to rise from 10% to 90% of its final value. Note that you can use a function key on the oscilloscope to obtain the measured rise-time. DISCUSSION 1. Compare the plots obtained in part 2 using the network analyzer with the frequency response semi-log plots you obtained in part 1. What relationship do you expect between the network time constant τ = RC and the 3dB frequency (the frequency at which the log magnitude response is 3dB below its in-band value)? Verify that this relationship holds for the circuits in thisexercise. 2. Verify that the expression given for Z in in part 2 in fact is equal to the input impedance of the network. From your computed values of Z in , determine for each of the two networks whether the input impedance is resistive or capacitive at 100Hz and 100kHz. Note that an impedance would be considered “resistive” if its phase were close to 0° and “capacitive” if its phase were close to – 90° . 3. For the waveforms you sketched in part 3, how do these waveforms relate to the network time constant τ? Find the ratio between τ and the rise time you measured for the low-pass network. Describe briefly the meaning of the network rise time, in terms of the network frequency response, by considering the frequency spectrum of a periodic square wave. DRAFT 22:1 on 24 January 2005 1-4 Experiment 1: Frequency-Domain and Time-Domain Measurements on RC Networks DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual 2-1 Experiment 2: The Diode-Connected BJT In this experiment we investigate the operation of the diode-connected BJT. PREPARATION A diode-connected BJT is a BJT with the base and collector shorted together. A npn diode-connected BJT is shown in Figure 2-1. iY iB iC vY Figure 2-1. A diode-connected npn BJT. The device to be used for this experiment is one of the three independent matched npn transistors contained in the CA3046 integrated transistor array. The SPICE model parameters for these transistors are conveniently provided by the manufacturer; these are given in Appendix B. The data sheet for the CA3046 array is in the file CA3045.pdf. 1. The SPICE parameters that characterize the static model for a BJT at room temperature are: IS, BF, IKF, ISE, NE, VAF, BR, RB, RC. Consult a SPICE reference (e.g. The SPICE Book or a Pspice manual), and note the significance of each of these parameters. 2. Run a simulation of the circuit in Figure 2-2 using Pspice. In particular, obtain a DC transfer characteristic (using the .DC command) from V S to V Y and I Y for a range of V S from 0 to 12V. Plot log 10 I Y vs. V Y , for V Y ranging from about 0.2V to the maximum value found in the simulation; you can generate this plot using Probe. 3. The circuit in Figure 2-3 will be used in the lab to measure the equivalent “small-signal” resistance of the diode-connected BJT, i.e. the equivalent incremental resistance of the linearized model at an operating point defined by ( V Y, I Y ) . The signal source v x represents a “test source” for measuring equivalent resistance. Since measuring the signal current drawn from the source is cumbersome, the resistance is 10kΩ IY VY VS Figure 2-2. Circuit for obtaining the V/I characteristic of a diode-connected BJT. DRAFT 22:1 on 24 January 2005 2-2 Experiment 2: The Diode-Connected BJT C > 1µF RX iy R vy vx VS Figure 2-3. Circuit for obtaining the incremental resistance of the diode-connected BJT. measured indirectly by connecting v x through a known series resistance ( R X in the figure) and then measuring the ratio v y ⁄ v x (where using the usual convention v y is the signal voltage across the device, i.e. the change from the operating point voltage V Y ). The capacitor C in the figure serves to allow the signal source to be connected to the device without upsetting the DC operating point. The value of C should be large enough so that it is approximately a short circuit compared to the series resistance R X at the test frequency (which will be 2kHz). The purpose of the resistor R in the figure is to permit adjustment of the DC operating point, primarily of the DC collector current, without shunting the device directly with a DC voltage source thereby upsetting the intended measuement. • Referring to Figure 2-3, develop a formula that will allow you to compute the incremental resistance of the device from measurements of v y ⁄ v x . PROCEDURE Throughout this experiment, use the 0-20V output of the HP DC power supply for V S . Use the function generator, with the output set to produce a sine wave at 2kHz, v x . Measure carefully the values of all resistors you use, since you will need these values in calculations. In particular, you will be measuring current by measuring voltage across a resistor through which the current flows. 1. Build the circuit shown in Figure 2-4. Vary the power supply voltage V S and resistance R so that you obtain values of I Y ranging from 1µA to 1mA. You can measure I Y by measuring the voltage across the 10kΩ resistance this voltage by the measured value of this resistance. It is easiest to keep the power supply voltage in the range of 5V to 15V, vary it within this range to make several measurements, and then change the value of R to make the next set of measurements. Using this approach, measure and record values of I Y and V Y at or near the following values of I Y : 1, 2, 4, 8, 10, 20, 40, 80, 100, 200, 400, 800, 1000 µA IY 10kΩ R VY VS Figure 2-4. Circuit for measuring the V/I characteristic of the diode-connected BJT. DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual 2-3 C > 1µF RX iy 10kΩ R vy vx VS Figure 2-5. Circuit for measuring the incremental resistance of the diode-connected BJT. Also, tabulate the values of R and V S that you use for each value of I Y . Plot your measurements as log 10 I Y vs. V Y . You can do this simply on three-cycle semi-log graph paper with I Y on the log axis, or you can use a computer graphing tool that will do this for you. 2. For each of the DC voltages you measured corresponding to the following currents: 10µA, 100µA, 1mA; set the power supply output voltage and resistance R to obtain a value of V Y 5mV greater than that you had measured, and record the new value of I Y . Estimate the value of the incremental device resistance at the three current levels (10µA, 100µA, 1mA) as ∆v Y (which is 5mV) divided by ∆i Y . 3. Build the circuit shown in Figure 2-5, with the function generator connected for v x . For each of the following values of I Y : 10µA, 100µA, 1mA; measure the incremental resistance of the device using the method outlined in the preparation above. For this measurement, the output level of the function generator should be adjusted so that the ac signal voltage across the device is about 2mV rms. Note that you can use the same values of R and V S that were used in step 1 above for the desired values of I Y . Note also that the measurement procedure works best when the value of R X is approximately equal to that of the resistance being measured. In this part, select R X so that it is no smaller than about one-tenth and no greater than about ten times the resistance being measured. Since the incremental resistance of the device varies by two orders of magnitude over the range of currents for which the measurement is made, you should choose for R X a value approximately equal to that of the incremental resistance of the device at I Y = 100µA . DISCUSSION 1. Describe briefly the significance of each of the SPICE parameters listed in the preparation above that characterize the static BJT model at room temperature. 2. From the simulated and measured log 10 I Y vs. V Y plots you obtained, estimate the value of the effective scale current I S of the BJT connected as a diode. Compare the simulated and measured plots, and comment on how they compare with what is predicted by theory. 3. Compare your measurements of incremental resistance using the two methods in the procedure. In addition, compare the measured values with values predicted by theory. DRAFT 22:1 on 24 January 2005 2-4 Experiment 2: The Diode-Connected BJT DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual 3-1 Experiment 3: Simple BJT Current Sources In this experiment we investigate the design and operation of simple BJT current sources. PREPARATION The basic BJT current source, often referred to as a “current mirror”, is shown in Figure 3-1. The operation of the circuit is based on matching of the transistors. For this experiment, the CA3046 integrated npn BJT array will be used. The SPICE model parameters for these transistors are provided in Appendix B; the data sheet is in the file CA3045.pdf. You can refer to a SPICE reference for the significance of the various parameters. In the circuit of Figure 3-1, R L is the resistance of the load on the current-mirror output, and V X is the DC voltage at the top end of this load. Assuming that Q1 and Q2 are identical and Q2 remains in the active region, the fact that Q1 and Q2 have the same V BE causes their collector currents to be equal as well (neglecting consequences of the Early effect given that they may have different values of V CB ). Refer to Section 2.2.1 of the handout lecture notes. Note in particular that the output resistance of the circuit (the inverse of the ratio of the change in output current resulting from a small change in v CE2 , for example) is approximately equal to the ratio of the Early voltage (the SPICE model parameter VAF) to the output current I C2 . 1. The circuit of Figure 3-1 is to operate with V CC = 12V , R L = 1kΩ , and V X = 5V . The output current is to be 0.5mA. Assume that V BE = 0.6V in the active region. Compute the appropriate value of R. Verify that Q2 will be operating in the active region. For the nominal value of β F use the value given for the parameter BF in the SPICE model. 2. The circuit of Figure 3-1 is to be modified as shown in Figure 3-2 to have two independent outputs. Assume all three transistors are matched. Using the value of R you already found for the single-output circuit and nominal β F , compute the values of the two output currents. 3. Devise a simple modification to the circuit of Figure 3-2 resulting in a single-output current mirror whose output current is approximately equal to two times the “setup” current in resistor R. 4. An ideal current source has infinite output resistance. As noted above, the output resistance of the circuit in Figure 3-1 is limited by the Early effect. This output resistance can be increased by placing equal resistors in series with the BJT emitters, as shown in Figure 3-3. The effect is the same as for a common emitter transistor stage with unbypassed emitter resistance. Note that here it is the sum V BE + ( I C + I B )R E that is the same for the two devices. With matched devices and equal emitter resis- +VCC1 iR +VX iC2 R RL Q1 Q2 vCE2 Figure 3-1. The basic BJT current mirror. DRAFT 22:1 on 24 January 2005 3-2 Experiment 3: Simple BJT Current Sources +VCC1 iR +VX1 iC2 +VX2 iC3 R RL1 RL2 Q1 Q2 Q3 Figure 3-2. A BJT current mirror with two independent outputs. tors R E , the two collector currents remain equal. That the output resistance here is higher than for the original circuit can be seen qualitatively from the following discussion. In the original circuit, increasing V X will increase I C2 with no change in V BE because of the finite output resistance of Q2 (Early effect). In the circuit of Figure 3-3, this increase in I C2 increases the voltage drop across the resistor in series with the Q2 emitter. Because the sum of this voltage drop and V BE2 is held constant by Q1, V BE2 is reduced, thereby counteracting the original increase in I C2 and causing the actual increase in I C2 to be smaller than in the original circuit for the same increase in V X . This is an example of negative feedback. A useful increase in output resistance can be obtained with R E chosen so that the voltage drop across it is several times ( kT ⁄ q ) . Compute a value for R E so that the voltage drop across it is 10 ( kT ⁄ q ) at room temperature for the design output current of 0.5mA. Note that the value of R will remain as in the original circuit of Figure 3-1. 5. Simulate the circuits in Figure 3-1 and Figure 3-3 using SPICE. a. With R L = 1kΩ and V X = 5V , have SPICE obtain the operating point of the circuit. Verify that the value of output current predicted by SPICE is reasonably close to the design objective. b. Have SPICE plot a DC transfer characteristic of the output current i C2 in R L vs. the output voltage from collector of Q2 to ground. You can do this by setting R L to zero and executing a .DC analysis varying V X . The output current will be the negative of the current through the source V X as defined by SPICE. +VCC1 iR +VX iC2 R RL Q1 RE Q2 RE Figure 3-3. A BJT current mirror with increased output resistance. DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual 3-3 PROCEDURE For all circuits, use the 0-20V output of the HP DC power supply set to 12V for V CC , and use the 0-6V output of the power supply for V X . Throughout, DC currents should be measured by measuring voltages across appropriate resistors. Make sure you measure the resistor values. 1. Build the circuit of Figure 3-1. For V X = 5V and R L = 1kΩ , measure the “setup” current in resistor R and the output current in R L . Reduce R L to about 10Ω and vary V X from 5V down to 0V, taking measurements of the output current in R L and the output voltage v CE2 , and plot the results (the purpose of having a small R L for this measurement is to protect the device; you can also measure the current by measuring the voltage across it). 2. Build the circuit of Figure 3-2. Measure the setup current in resistor R and the two output currents for R L1 = R L2 = 1kΩ and V X1 = V X2 = 5V . Use the same power supply for both V X1 and V X2 . 3. Build the modified version of the circuit in Figure 3-2 that you devised. For a load consisting of R L = 1kΩ and V X connected to the single output, measure the setup current in R and the output current in R L and verify that the latter is approximately twice the former. 4. Build the circuit of Figure 3-3. For V X = 5V , measure the setup current in resistor R and and the output current in R L . Reduce R L to about 10Ω and vary V X from 5V down to 0V, taking measurements of the output current in R L and the output voltage from collector of Q2 to ground, and plot the results. DISCUSSION 1. For all circuits, compare measured results with computed values obtained in the preparation as well as results provided by SPICE. 2. For the two circuits for which you measured and plotted output current vs. output voltage, explain the key features of the curves you plotted. Estimate the output resistance of the circuits from the slope of the curves. Compare the performance of the two circuits. 3. Explain the operation of the modified version of the circuit in Figure 3-2 that you devised. Given the relationship between emitter-junction area and scale current I S for a BJT, describe how the same result (an output current equal to twice the “setup” current) could be obtained with two BJTs instead of three. DRAFT 22:1 on 24 January 2005 3-4 Experiment 3: Simple BJT Current Sources DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual 4-1 Experiment 4: The Differential Pair In this experiment we examine the DC and AC characteristics of the BJT differential pair with resistive load. PREPARATION The circuit shown in Figure 4-1 is a BJT differential pair with resistive load. The current source driving the emitters of the pair is implemented using a simple current mirror. For the circuit shown in Figure 4-1: 1. Compute the value of R 1 such that the DC collector current of Q4 is 0.5mA. Neglect the base currents of Q3 and Q4, and use the value of I S specified in the SPICE model for the CA3046 npn transistor array (see Appendix B). Remember that for an npn BJT operating in the active region, kT I C V BE ≈ ----- log ---q IS 2. Compute the value of the collector resistors R C such that the voltage from each collector to ground is half the collector supply voltage V CC of 10 V, with the circuit balanced ( I C1 = I C2 ). 3. Using nominal values of β o , r b , and V A from the data sheet (look at the SPICE model and the curves on the data sheet; β o is sometimes called h fe [it seems to be mistakenly referred to as h FE in the data sheet in the file CA3045.pdf] and for purposes of this experiment can be taken to be equal to the SPICE parameter BF; r b is RB in the SPICE model), compute the differential gain A dds and common-mode gain A ccs for the circuit in Figure 4-1 at midband, with the output voltage for each defined as in the lecture notes on differential pair circuits (Section 4.10.1). Compute also the differential and common-mode gains with the output voltage taken between the collector of Q2 and ground, i.e. ( V c2 ⁄ V sdm ) and ( V c2 ⁄ V scm ) , respectively. Assume that r o → ∞ for all BJTs except Q4; the value of r o for Q4 is equal to ( V A ⁄ I C4 ) , and this is the effective output resistance of the equivalent DC current source feeding the +10V RC RC iC1 vC1 vC2 iC2 RS vS1 R1 Q3 Q1 Q2 RS vS2 Q4 –10V Figure 4-1. A basic BJT differential pair with resistive load. DRAFT 22:1 on 24 January 2005 4-2 Experiment 4: The Differential Pair emitters of Q1 and Q2. Use R S = 100Ω . Also, recall the the voltages V sdm and V scm are defined to be: V sdm ≡ V s1 – V s2 1 V scm ≡ -- ( V s1 + V s2 ) 2 4. Program the circuit in Figure 4-1 using Pspice, using the resistor values you computed. Verify that the operating point of the circuit, found by setting v S1 = v S2 = 0 in the simulation, matches the design objectives. Use Pspice to obtain a transfer characteristic from v S1 to the collector currents i C1 and i C2 , with v S2 = 0 . Note that with v S2 = 0 , v SDM = v S1 . PROCEDURE Please note that throughout the procedure, when you are asked to measure a signal voltage the measurement is to be made with the multimeter, set to measure AC voltage. You should use the oscilloscope to monitor AC signals to make sure they are (or at least appear to be) undistorted (but note that in some cases the signals may be too small to see clearly on the scope). Guidelines for building these circuits are appended below on page 4-4. 1. Build the circuit shown in Figure 4-2 using one CA3046 transistor array. Note that you can use the two devices already connected as a differential pair for Q1 and Q2 in this circuit. Use the values for R 1 and R C you obtained in the preparation. Verify that I C4 is approximately 0.5mA; the most effective way to do this is to insert a 100Ω resistor in series with the collector of Q4 below the connection of the emitters of Q1 and Q2 and then to measure the DC voltage across this resistor (the 100Ω resistor is shown in the circuits in Figures 4-2, 4-3, and 4-4; it will not affect the operation of the circuit and should be left in place for all parts of this experiment). 2. The input offset voltage of a BJT differential pair may be defined to be the differential base-emitter voltage needed to cause the collector currents to be equal; a non-zero input offset voltage is the result of mismatch between the devices. In your circuit, use the 0-6V output of the power supply as shown in the +10V RC IC1 RC IC2 0 - 6V 1MΩ 1kΩ R1 Q3 Q1 Q2 10Ω 100Ω Q4 –10V Figure 4-2. Measuring the input offset voltage of a differential pair. The input offset voltage results from mismatch in the devices Q1 and Q2. If the devices were perfectly matched, the collector currents would be equal when the base-emitter voltages are equal. DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual 4-3 +10V RC 100Ω Vs R1 Q3 100Ω Q4 Q1 Q2 RC Vc2 100Ω –10V Figure 4-3. Measuring the differential gain. figure and adjust this power supply output voltage so that the collector currents of Q1 and Q2 are equal. Estimate the input offset voltage by measuring the difference between V BE1 and V BE2 with the collector currents equal. Measure collector currents by sensing the voltage across the collector resistors. Note that you may have to reverse the polarity of the connection to the 0-6V supply, depending on the polarity of the input offset voltage for the devices you are using. You can measure the difference between V BE1 and V BE2 by measuring the DC voltage from the base of Q1 to the base of Q2. Assuming that you have measured the values of the two collector resistors, you can compute the DC voltage measured from the collector of Q1 to the collector of Q2 when the two collector currents are equal (if the collector resistors are equal, this voltage is zero), and then you can adjust the output of the 0-6V supply so that the measured voltage between the two collectors is equal to what you have computed. 3. Replace the 1MΩ resistor in Figure 4-2 with a 5KΩ resistor. By varying the output of the 0-6V supply (and its polarity when necessary), measure I C1 and I C2 as functions of the differential input voltage ( V BE1 – V BE2 ) , for this voltage in the range of –200 mV to +200 mV. Plot the transfer characteristics you have measured, i.e. I C1 and I C2 vs. the differential input voltage. Make sure you take measurements at a sufficient number of points to see the details of the transfer characteristic. 4. Add a signal generator to the circuit and remove the DC voltage adjustment, as shown in Figure 4-3, matching the two 100Ω resistors as well as you can. Measure the DC voltages at the collectors of Q1 and Q2 and verify that they are approximately equal. At 2kHz, measure the voltage gain ( V c2 ⁄ V s ) as shown. Noting that V s1 = V s and V s2 = 0 for the measurement as shown in Figure 4-3, relate this gain to the differential gain found in the preparation. Monitor the output voltage with an oscilloscope to make sure that the circuit is operating linearly. 5. Connect the signal generator as shown in Figure 4-4, again making sure the two 100Ω resistors are as well matched as possible. At 2kHz, measure the voltage gain ( V c2 ⁄ V s ) as shown. Noting that V s1 = V s2 = V s for the measurement as shown in Figure 4-4, relate this gain to the common-mode gain found in the preparation. Monitor the output voltage with an oscilloscope to make sure that the circuit is operating linearly. Note that you may need a significantly larger source voltage here than in the previous part. Note also that any circuit imbalances that cause a non-zero input offset voltage are assumed to be small enough to be neglected in this measurement. DRAFT 22:1 on 24 January 2005 4-4 Experiment 4: The Differential Pair +10V R C R C 100Ω Vs R 1 Q1 Q2 100Ω 100Ω Q4 –10V Vc2 Q3 Figure 4-4. Measuring the common-mode gain. DISCUSSION 1. Compare your computed results from the preparation and those predicted by Pspice simulation with your measured results. 2. Compare your measured value of input offset voltage with the range for this parameter specified on the CA3046 data sheet. GUIDELINES FOR BUILDING THE DIFFERENTIAL PAIR CIRCUITS These notes provide guidelines for building the differential pair circuits in Experiment 4. Figure 4-5 shows a good layout for the core of these circuits. What is shown is the assignment of transistors in the circuit to transistors in the IC packages, the interconnections between the transistors, and a few of the resistors; not all the external connections are shown (e.g., power supply connections are not shown). The IC package (the npn array) is shown in top view, as it is shown on the data sheet, with pin 1 at top left and pin 14 at top right. The dashed lines represent the horizontal sets of pin sockets in the breadboard to either side of the place where the IC is plugged in to the breadboard. The solid lines with connection dots at each end are wires inserted in the pin sockets to connect pairs of pins of the IC package. The notation “C1” in the figure above indicates the colRC C1 B1 C3 E3 R1 E1,E2 B3 B2 C2 RC C4 E4 B4 Figure 4-5. Layout for the differential pair circuits. DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual 4-5 lector of Q1 as shown in the figure in the lab manual (e.g. Figure 4-2), etc. Thus, for example, there is a wire shown connecting the base and collector of Q3, and there is a wire shown connecting the base of Q3 to the base of Q4; etc. Note that these wires can be made very short. In fact, they SHOULD be made very short; this will reduce the chances for wires to touch and short or for wires to be accidentally pulled out of the pin sockets. Note also that the wire connecting the collector of Q4 with the emitters of Q1 and Q2 is shown going across the package; in fact, it can also be short and can run just above the package. DRAFT 22:1 on 24 January 2005 4-6 Experiment 4: The Differential Pair DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual 5-1 Experiment 5: Design and Evaluation of a BJT Common-Emitter Stage In this exercise we will design a simple BJT common-emitter (CE) amplifier stage, verify the design using SPICE, and evaluate it experimentally in the laboratory. Measurements of voltage gain will be made over a range of frequencies, and effects of device capacitances will be observed. Examination of an isolated CE stage requires circuitry to bias the stage, i.e. to insure that the BJT has a stable operating point in the active region. This circuitry, which generally includes a number of resistors and capacitors, is appropriate for an implementation using discrete transistors and passive components. In this course, however, we are interested primarily in circuit structures that are appropriate for integrated-circuit implementations. Thus, the CE stage investigated in this experiment is configured in a manner similar to that commonly used for CE stages in integrated amplifiers, i.e. it is driven by an actively loaded differential pair. The differential pair, which has a naturally established stable operating point (recall Experiment 4), also sets up a stable operating point for the CE stage in a natural way. PREPARATION The circuit to be built in the lab for this experiment is shown in Figure 5-1. The CE stage is made up of Q5 and resistance R C . It is driven by the differential pair Q1-Q2 loaded by Q3-Q4 and fed by current source Q6-Q7. Note that the differential pair differs from the circuit examined in Experiment 4 and from the differential pair circuits with active load discussed in the lecture notes. The differences result from the lack of availability of matched, integrated pnps, from imperfect matching of all the devices in the CA3046 npn array, and from the need to focus on the behavior of the CE stage without its being affected by the presence of the differential pair. +10V 2kΩ 2kΩ Q6 RI RS Vs RE Q1 Q7 RE Q2 RS 100Ω 10kΩ 0.1µF VZZ RC Vo Q3 Q4 Q5 –10V Figure 5-1. A CE stage driven by a differential pair. DRAFT 22:1 on 24 January 2005 5-2 Experiment 5: Design and Evaluation of a BJT Common-Emitter Stage rb5 GM1Vs Figure 5-2. Ro1 rπ 5 Vπ 5 Cµ5 Cπ5 g V m5 π5 ro5 Ccs5 RC Vo Dynamic incremental model of the complete circuit in Figure 5-1. In the circuit in Figure 5-1, there are emitter resistors (labeled R E in the figure) in series with the emitters of the differential-pair devices. The purpose of these emitter resistors is to dramatically reduce the dependence of the differential pair’s behavior on device parameters. This will permit the characteristics of the CE stage to be easily estimated from measurements on the overall circuit. In fact, it can be shown that the dynamic incremental model (i.e., including device capacitances) of the circuit in Figure 5-1 is essentially as shown in Figure 5-2, at least over the range of frequencies that will be of interest in this experiment. In particular, the entire differential pair can be represented by the voltage-controlled current source G M1 V s with output resistance R o1 , with 1 G M1 = ----RE R o1 = r o4 (5.1) The CA3046 npn array will be used for the npn devices in the circuit. The pnps will be 2N3906 discrete BJTs. Make sure that the substrate pin on the CA3046 package is connected to the negative DC supply voltage in the circuit. From the SPICE model for the CA3046, we can obtain the following information: β F = β o = 145 (nominal) τ b = 277psec V A = 100V rb = 0 (5.2) C JE = 1.03pF (at V BE = 0) C JC = 0.992pF (at V BC = 0) Because ‘CCS’ is not specified in the SPICE model, we would assume that C cs = 0 (the default value assumed by SPICE). The operating point for the CE stage is to be at a collector current of 0.5mA, i.e. I C5 = – 0.5 mA . It can be shown that this objective will be met, to first order (i.e. neglecting base-width modulation) and with the npn deviced perfectly matched, if the DC output current of the current source ( I C7 ) is equal to 0.5mA. As a first approximation, the value R I = 16.8kΩ is chosen to meet this objective. We also take R E = 10kΩ and R S = 1kΩ . Note that because of imperfect matching of β F between the device to be used as Q5 and the devices to be used as Q3 and Q4, it may be necessary to use a DC voltage at one of the differential-pair inputs to indirectly adjust the DC collector current of Q5 to it’s design value; this DC voltage is shown as V ZZ in Figure 5-1. However, the initial design and simulation will be carried out assuming that the devices are perfectly matched and with V ZZ = 0 . Proceed now as follows: 1. Select a value for R C such that the DC operating-point voltage to ground at the circuit’s output, i.e. at the collector of Q5, is 0V. 2. Starting with the circuit in Figure 5-2, construct an incremental model for the circuit at the desired operating point at midband, i.e. with the device capacitances assumed to be open circuits. Use the nominal value of β o from the SPICE model. Compute the midband voltage gain ( A VSO ) o ≡ ( V o ⁄ V s ) midband . Compute the output resistance of the circuit at midband. DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual 5-3 3. Consider now the dynamic incremental model including the device capacitances of Q5 as shown in Figure 5-2. Find C µ = C JC at the operating point using the following (valid for an npn BJT): CJC C µ = C JC ( V BC ) = ------------------------------------ 1 + V BC  MJC ----------   VJC (5.3) where CJC is the value of C JC at V BC = 0 (i.e., 0.992pF from the SPICE model). For the CA3046 devices, MJC = 0.33 and VJC = 0.5V (also from the SPICE model). To find C JE at the operating point, it is difficult to use the equivalent to Eqn. (5.3) because this equation loses validity when the junction is forward biased. A reasonable approximation is to take: C JE ( V BE ) ≈ 2CJE (5.4) where CJE is the value of C JE at V BE = 0 (i.e., 1.03pF from the SPICE model). Find C DE at the operating point using C DE = τ b g m . Finally, C π = C JE + C DE . Also, note the value of f T at the operating point, computed as f T = g m ⁄ ( C π + C µ ) . Now, using the Miller’s theorem approximation, estimate the upper 3dB frequency of the voltage gain A VSO ≡ V o ⁄ V s for this circuit. 4. Assume that C µ is increased by 20pF (approximately what would result if a 20pF capacitor were to be connected between the base and collector of Q5). Again using the Miller’s theorem approximation, estimate the upper 3dB frequency of the voltage gain A VSO ≡ V o ⁄ V s for the circuit with the additional capacitance. 5. Program the circuit on SPICE (e.g., using Pspice). a. Verify the operating point. Vary the value of R I to get I C5 = 0.5mA . b. Obtain the log magnitude and phase of the voltage gain A VSO ≡ V o ⁄ V s vs. frequency using a logarithmic sweep from 1kHz to 10MHz. c. Obtain the output impedance of the circuit over the same frequency range. To do this, you can connect an ideal AC current source to the output (e.g. “IX ngnd nout AC 1 DC 0”) and have SPICE find the resulting voltage across it. d. Repeat the simulations in (b) and (c) with a 20pF capacitor connected externally between base and collector of Q5. PROCEDURE Construct the circuit shown in Figure 5-1. Use 2N3906 discrete BJTs for the pnp devices. Use the CA3046 array for the npn devices, as follows: • Use the devices labeled Q1 and Q2 in the CA3046 data sheet (pins 1, 2, and 3, and pins 5, 4, and 3) for the devices shown as Q3 and Q4 in Figure 5-1. • Use the device labeled Q3 in the CA3046 data sheet (pins 8, 6, and 7) for the device shown as Q5 in Figure 5-1. • Connect the substrate pin on the CA3046 package (pin 13) to the negative DC supply voltage in the circuit. Use the specified values for R E and R S . Match the values of the two R E resistors as closely as possible (ideally to within 2% to 3%). Use the value for R I that resulted from the simulations in step (5a) of the prepa- DRAFT 22:1 on 24 January 2005 5-4 Experiment 5: Design and Evaluation of a BJT Common-Emitter Stage ration. Use the value for R C that you found in step (1) of the preparation. Try to use a careful layout to minimize the effects of wiring on high frequency measurements; leads just an inch or two in length can add as much as 10pF of stray parasitic capacitance to a circuit. Be especially careful with the base and collector leads of the CE stage. Use the low voltage output of the power supply for V ZZ , and start with V ZZ set to zero. 1. Apply power to your circuit with V ZZ set to zero. Verify the DC operating conditions of the differential pair; i.e., verify that the output current of the current source (the collector current of Q7) is 0.5mA by measuring the voltage across the 2kΩ resistor in series with the emitter of Q7 (and assuming emitter and collector currents are equal in magnitude), and verify that the collector currents of Q1 and Q2 are equal to 0.25mA by measuring the voltages across the two R E resistors (again assuming emitter and collector currents are equal in magnitude). Adjust the value of R I so that the measured currents have the desired values. 2. Measure the DC collector current of Q5 by measuring the voltage across the resistor R C . Adjust V ZZ to obtain I C5 = 0.5mA . Note that you may need to reverse the polarity of V ZZ . As a general rule, if I C5 is less than 0.5mA with V ZZ = 0 , then V ZZ should be positive; while if I C5 is greater than 0.5mA with V ZZ = 0 , then V ZZ should be negative. Once V ZZ is properly adjusted, measure the collector currents of Q1 and Q2 again (as in step 1 above). 3. Connect a sinusoidal signal as V s with a frequency of about 5kHz and amplitude of 1mV rms. Observe the output voltage with an oscilloscope to verify linear operation. Estimate the voltage gain at the signal frequency, by measuring V s and V o with the AC-voltmeter function of the multimeter. Note that this is the midband gain of the amplifier. 4. Increase the amplitude of the input signal, observing the output on the oscilloscope. Note the extremes of output signal voltage (maximum variation from the operating point) at which the output waveform begins to appear distorted. 5. Use the HP Network Analyzer to obtain a measurement of the circuit’s voltage gain vs. frequency: a. Adjust the analyzer’s frequency setting for a logarithmic sweep from 1kHz to 10MHz. Set the output level to -60dBV (1mV rms). Make sure that the receiver settings for all the analyzer’s input channels are for 1MΩ input impedance with 20 dB attenuators in. Use the probes connected to these inputs with their switches set to 10x attenuation. b. Turn off the power supply for your circuit. Connect the analyzer output as V s and connect analyzer inputs ‘R’ and ‘A’ to measure V s and V o , respectively. Restore power to your circuit. Verify that the DC operating conditions remain correct. Connect the oscilloscope to V o and verify that the circuit is operating linearly. c. Using the analyzer’s front panel keys, display the log magnitude (in dB) and phase of ‘A/R’, which is the gain of the amplifier, on trace 1 and trace 2, respectively. Use the marker control keys on the front panel to locate the upper 3dB frequency of the amplifier and also to find the log magnitude of the gain at 500kHz. Make a hard copies of these plots making sure that the scaling of both the horizontal and vertical axes is clearly indicated. d. Add an external capacitor of about 20pF between base and collector of the BJT and repeat step (c). Check the output waveform on the oscilloscope to make sure circuit operation remains linear. 6. Use the HP Network Analyzer to obtain a measurement from whch the circuit’s output impedance vs. frequency can be computed, using the configuration in Figure 5-3: DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual 5-5 +10V 2kΩ 2kΩ Q6 RI RS Vs RE Q1 Q7 RE Q2 RS 100Ω 10kΩ 0.1µF VZZ RC 0.1µF Vo 20kΩ Vx Q3 Q4 Q5 –10V Figure 5-3. Circuit for measuring the output impedance of the CE stage. a. Turn off the power supply for your circuit. Remove the extra 20pF capacitor. Referring to Figure 5-3, connect the analyzer output as V x and connect analyzer inputs ‘R’ and ‘A’ to measure V x and V o , respectively. Adjust the analyzer’s frequency setting for a logarithmic sweep from 1kHz to 1MHz., and set the output level to -20dBV (100mV rms). Restore power to your circuit. Verify that the DC operating conditions remain correct. Connect the oscilloscope to V o and verify that the circuit is operating linearly. b. Using the analyzer’s front panel keys, display the log magnitude (in dB) and phase of ‘A/R’, which is the ratio of V x to V o , on trace 1 and trace 2, respectively. Make a hard copies of these plots making sure that the scaling of both the horizontal and vertical axes is clearly indicated. Using the marker control keys on the front panel, find and record the values of the log magnitude an phase at the frequencies 1kHz, 10kHz, 100kHz, and 1MHz. c. Add an external capacitor of about 20pF between base and collector of the BJT and repeat step (b). d. Using the values you recorded in parts (b) and (c), compute the output impedance of the CE stage at the listed frequencies by noting that: Vo Zo ----- = ------------------------Vx Z o + 20kΩ (5.5) where Z o is the output impedance of the circuit. Note that the 0.1µF capacitor is assumed to be a short circuit at all measurement frequencies. DRAFT 22:1 on 24 January 2005 5-6 Experiment 5: Design and Evaluation of a BJT Common-Emitter Stage DISCUSSION 1. Compare the results predicted by hand analysis, the simulation results, and the measured values, for operating point, midband voltage gain, upper 3dB frequency of the voltage gain, and output impedance. 2. Comment on the effects of adding the 20pF capacitor. 3. Compare the circuit gain-bandwidth product (midband voltage gain times upper 3dB frequency) with the value of f T for the transistor, with and without the external 20pF capacitor. DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual 6-1 Experiment 6: The 741 Operational Amplifier In this experiment we examine the characteristics of the 741 op amp, and explore its use in several common applications. PRELIMINARY REMARKS The 741 was one of the first integrated op amps, originally designed some 25 years ago. It remains a popular, general-purpose op amp and is available from a number of IC manufacturers. A data sheet for the LM741 from National Semiconductor is in the file LM741.pdf; a data sheet for the LM747 from National Semiconductor, which includes two independent 741 op amps in a single package, is in the file LM747.pdf (this data sheet is included because it actually has more detailed information that that for the LM741). A simplified schematic of the 741 is shown in the data sheets. Referring to this figure, you will see that the 741 is a bipolar op amp consisting of a differential input stage with active load, a “Darlington” (common-collector followed by common-emitter) gain stage, and a complementary-symmetry common-collector output stage. You may notice that the 741’s input stage seems rather more complicated than an ordinary differential pair. In fact, the 741 was designed long before complementary bipolar technologies became available. Standard, non-complementary bipolar technologies include high-quality npn transistors but only low-β, low- f T pnp transistors. The input stage of the 741 is indeed a differential pair with active load, with a structure that cleverly employs the poor-quality pnps in the best way possible. An op amp such as the 741 has a very high voltage gain at low frequencies; also, the bandwidth of this voltage gain (i.e. its upper 3dB frequency) is very low. Referring to the 741 data sheet in the file LM747.pdf (see the plot labelled “open-loop transfer characteristics vs. frequency”) you will see that low-frequency volt5 age gain is about 106dB (or 2 ×10 ), while the upper 3dB frequency is about 5Hz. The usefulness of an op amp is generally in configurations with negative feedback, in which there is a closed loop from the output back to the input. The negative feedback reduces the gain to a useful value, increases its bandwidth, and stabilizes the gain against variation of device parameters within the op amp. The two most common feedback configurations for op amps are the non-inverting and the inverting modes, shown in Figure 6-2(a) and Figure 6-2(b), respectively. In the paragraphs that follow, a highly simplfied summary of the analysis of these circuits is presented that is adequate for the laboratory exercise at hand. We will represent the op amp here as the voltage-controlled voltage source A 1 V i1 , with infinite input resistance and zero output resistance, as shown in Figure 6-3. (Note that we will concern ourselves here with V i1 as the differential input voltage, and A 1 as differential gain; we will not consider common-mode gain and CMRR in this experiment). We also state the formula for the true closed-loop gain A f of a feedback system: V+ Vi1 Vo V– Figure 6-1. An op amp. The input voltage Vi1 is the differential input voltage of the op amp. The pins labeled V+ and V– are the positive and negative power supply connections, respectively (note that these pins are not shown on most of the figures that follow). DRAFT 22:1 on 24 January 2005 6-2 Experiment 6: The 741 Operational Amplifier RS Vs RL R2 R1 (a) Figure 6-2. RS Vo RL Vo Vs RF (b) An op amp with non-inverting mode (a) and inverting mode (b) feedback. Vi1 Vo Vi1 A1Vi1 Vo (a) Figure 6-3. A simple op amp model. (b) A A f = ----------1+T (6.1) In this equation, A is the open-loop gain, and T is the loop gain; the loop gain is equal to the product of the open-loop gain and the feedback factor β (not the same as the β of a BJT). For the non-inverting configuration, we can identify these quantities once we redraw the circuit in Figure 6-2(a) using the op amp model in Figure 6-3, and taking a Thevenin equivalent circuit looking back towards the output from the inverting (–) input of the op amp. The resulting circuit is shown in Figure 6-4. RS Vs Vi1 A1Vi1 RL Vo Req Veq Figure 6-4. Equivalent circuit for the op amp with non-inverting mode feedback. Referring to the figure, we first make the following identifications: DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual 6-3 R eq = R 1 || R 2 and we then have the following: Vo A f = ----Vs  R1  V eq = V o  ------------------  R 1 + R 2 Vo A = ------- = A 1 V i1 R1 β = -----------------R1 + R2 (6.2) For the inverting configuration, we redraw the circuit in Figure 6-2(b) using the op amp model in Figure 6-3, taking a Norton equivalent circuit looking back towards the output from the inverting (–) input of the op amp, and also replacing the voltage source V s by its Norton equivalent circuit. We do this because in the inverting configuration, the true closed-loop gain, given by Eqn. (6.1), is V o ⁄ I s and not V o ⁄ V s . The resulting circuit is shown in Figure 6-5. For the inverting configuration in the figure, we first make the following identifications: Vs I s = ----RS and we then have: Af Vo ----- = ----Vs RS Vo A f = ----Is A = – A 1 ( R S || R f ) 1 β = – ---Rf (6.3) Vo I eq = ----Rf R eq = R f For any feedback amplifier, including the inverting and non-inverting configurations considered here, in the limit as T becomes infinite, A f approaches 1 ⁄ β . The op amp gain A 1 is, of course, a function of frequency. Plots of the log magnitude and phase of A 1 for a typical 741 op amp are included in the data sheet (labelled “open-loop transfer characteristics vs. frequency”). As noted above, these plots show that the upper 3dB frequency of A 1 is only 5Hz. In fact, very low open-loop bandwidth is a common characteristic of op amps. When negative feedback is to be applied to any circuit or system, there is the possibility that the resulting closed-loop circuit or system will be unstable or oscillate if the open-loop response has three or more poles. An op amp such as the 741 typically has at least three poles that contribute to its open-loop response. One way of insuring stability of the closed-loop amplifier is for the open-loop gain to have a dominant pole, i.e. a pole that is much lower in frequency than all other open-loop poles. To insure stability for some particular value of the feedback factor β (and thus for some particular value of ideal closed-loop gain), the dominant pole must be placed so that the following condition is satisfied: Is RS Ieq Req Vi1 A1Vi1 RL Vo Figure 6-5. Equivalent circuit for the op amp with inverting mode feedback. DRAFT 22:1 on 24 January 2005 6-4 Experiment 6: The 741 Operational Amplifier As the magnitude of the loop gain T decreases with increasing frequency ω (or f), it must fall below unity before the phase of the loop gain T becomes more negative than – 180° . Phase margin and gain margin are quantities that indicate how close to instability a feedback amplifier may be. These quantities are defined as follows (see Figure 6-6): 1. Phase margin is the amount by which the phase of the loop gain is less negative than – 180° , at the frequency at which the magnitude of the loop gain is unity. The more positive the phase margin, the better the margin against instability. 2. Gain margin is the amount (in dB) by which the log magnitude of the loop gain is more negative than 0dB, at the frequency at which the phase of the loop gain is – 180° . The more positive the gain margin, the better the margin against instability. Given A 1 ( s ) , the op amp gain as a function of frequency, in either analytical or graphical form, as well as the values of the other circuit componentd, it is easy to estimate the phase and gain margins for either feedback configuration. It is simply a matter of writing the loop gain T = βA , with β and A as in Eqn. (6.2) or (6.3) as appropriate. The process of insuring stability by placing poles (and perhaps zeros) of the open-loop gain properly is called compensation. The most common form is Miller compensation, which takes advantage of the so-called Miller effect associated with a high-gain stage to establish a low-frequency pole using a small capacitor. The 741’s pole at about 5Hz is established using a 30pF capacitor integrated in the chip. Figure 6-6. Gain and phase margins. DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual 6-5 One detrimental effect of compensation is that it limits the rate at which the output voltage can change, based on the maximum rate at which the compensation capacitor can be charged and discharged inside the op amp. This phenomenon is called slew-rate limiting. For very small output amplitudes, slew-rate limiting has no impact and the useful bandwidth of the closed-loop amplifier is the closed-loop bandwidth found as the upper 3dB frequency of the closed-loop gain A f ( s ) . For larger output amplitudes, while the output waveform will remain undistorted at low frequencies, at higher frequencies distortion will be observed due to slew-rate limiting. This phenomenon is the result of the inability of voltages inside the amplifier to change as rapidly as necessary; in the 741 op amp, the current available to charge and discharge the 30pF compensation capacitor is limited, and do the rate of change of the voltage across this capacitor is also limited. The slew rate of an op amp is usually measured using a rectangular wave input signal with the op amp connected as a “voltage follower” (unity-gain, non-inverting configuration), as shown in Figure 6-x2. PREPARATION Parts of the preparation require the use of Pspice to simulate circuits using the 741 op amp. Fortunately, it is not necessary to code explicitly the entire 741 circuit. Libraries of so-called op amp macromodels (essentially, equivalent circuits incorporating both linear and nonlinear effects) are available from many vendors. Individual macromodels may be included in Pspice simulations using subcircuit elements or by explicit references using the Pspice schematic editor. A macromodel for the 741 op amp is available in the library nat_semi.lib that is accessible by Pspice; a listing is provided in Appendix C. To include the macromodel in a Pspice input (.cir) file, use the following: Xname +inputnode -inputnode +powersupplynode -powersupplynode outputnode .LIB nat_semi.lib Note that ‘X’ is the Spice identifier for a subcircuit, which is how the macromodel is specified. In your Pspice simulations, take the DC power supply voltages to be +10V and –10V. 1. Using Eqns. (6.1), (6.2), and (6.3), show that in the limit as A 1 → ∞ , inverting: Vo Rf ----- = – ----Vs RS Vo R2 non-inverting: ----- = 1 + ----Vs R1 (6.4) 2. The circuit shown in Figure 6-8 will be used to measure the gain A 1 of the op amp. Program this circuit using Pspice. Obtain plots of the log magnitude and phase of A 1 using a logarithmic frequency sweep Figure 6-7. Slew rate with a voltage follower. DRAFT 22:1 on 24 January 2005 6-6 Experiment 6: The 741 Operational Amplifier from 1Hz to 10MHz (e.g.: .AC DEC 10 1 10MEG). From your plots, estimate the upper 3dB frequency of A 1 and the frequency at which its magnitude is equal to 1. 3. Assume a configuration in which T = A 1 , for example a non-inverting mode circuit with β = 1 . Using the plots you obtained from the Pspice analysis in step 2, estimate the phase margin of the 741 in this configuration. 4. Design a non-inverting mode amplifier, driven from a source resistance R S = 10kΩ , to have a closed-loop gain ( V o ⁄ V s ) equal to 4, i.e. 12dB. See Figure 6-2(a) and Figure 6-4. Use the ideal relation given in Eqn. (6.4). Select R 1 and R 2 so that: •the gain requirement is satisfied •the parallel combination R 1 || R 2 is equal to R S (this minimizes the effect of input bias current, i.e. base current of the input-stage transistors on output offset voltage) Using the plots you obtained from the Pspice analysis in step 2, estimate the phase margin of this amplifier. 5. Program the circuit you designed in step 4 using Pspice. Obtain plots of the log magnitude and phase of the closed-loop gain ( V o ⁄ V s ) using a logarithmic sweep from 100Hz to 10MHz. From your plots, estimate the value of the upper 3dB frequency of the closed-loop gain ( V o ⁄ V s ) . 6. Design an inverting mode amplifier, driven from a source resistance R S = 10kΩ , to have a voltage gain ( V o ⁄ V s ) equal to –4, i.e. 12dB. See Figure 6-2(b) and Figure 6-5. Use the ideal relation given in Eqn. (6.4). The design is simply a matter of selecting : R f to satisfy the gain requirement. Using the plots you obtained from the Pspice analysis in step 2, estimate the phase margin of this amplifier. 7. Program the circuit you designed in step 6 using Pspice. Obtain plots of the log magnitude and phase of the closed-loop gain ( V o ⁄ V s ) using a logarithmic sweep from 100Hz to 10MHz. From your plots, estimate the value of the upper 3dB frequency of the closed-loop gain ( V o ⁄ V s ) . 8. Assume that the op amp gain A 1 ( s ) can be approximated by a single-pole transfer function, with the single pole being the dominant pole at the upper 3dB frequency. Thus: A 1o A 1 ( s ) ≈ ---------------s 1 + ------ωH 100k Ω 100k Ω 100k Ω 1kΩ Vi1 1kΩ Vo (6.5) Vs Figure 6-8. Circuit for measuring the op amp gain. DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual 6-7 +10V or –10V R R' 100Ω Vi1 1kΩ Vo Figure 6-10. Circuit for measuring the input offset voltage of the op amp. where A 1o is the zero-frequency value of A 1 and ω H is its upper 3dB frequency (in radians per second). Using Eqns. (6.1), (6.2), (6.3), and (6.5), write Vo A fo ----- ≈ -----------------Vs s 1 + -------ω Hf (6.6) where A fo is the zero-frequency value of the closed-loop gain ( V o ⁄ V s ) and ω Hf is its upper 3dB frequency (in radians per second). Using estimates of A 1o and ω H from your plots in step 2, estimate the value of ω Hf for each of the two amplifiers you designed. PROCEDURE Throughout the procedure, power supply connections for the op amp are to be made as shown in Figure 6-9. The 1µF capacitors are used to minimize the effects of power supply noise and other non-ideal characteristics of the power supplies. 1. The input offset voltage V IO of the op amp is defined to be the differential DC input voltage V I1 required to force the DC output voltage to be zero. Using the circuit shown in Figure 6-10, measure V IO for your 741 op amp. Note that resistor R should be about 100kΩ while resistor R' should be about 100Ω. Note also that V IO will vary from device to device; the worst-case (maximum) value is specified on the data sheet. Finally, note that V IO may be of either polarity; depending on its polarity for your device, you may have to use the –10V supply or the +10V supply as the input voltage connected at the left-hand end of resistor R as shown in the figure. You may also have to adjust the values of the fixed resistor R and the variable resistor R' . 2. Using the circuit shown in Figure 6-8, measure the gain A 1 of the op amp. This measurement is made using the HP network analyzer, with the analyzer output connected as V s , the analyzer ‘R’ input con+10V 1µF Vi1 Vo 1µF –10V Figure 6-9. Power supply connections for the op amp. DRAFT 22:1 on 24 January 2005 6-8 Experiment 6: The 741 Operational Amplifier nected to the inverting (–) input of the op amp (across the 100Ω resistor), and the analyzer ‘A’ input connected to the op amp output (across the 1kΩ load resistor). Use a logarithmic frequency sweep from 100Hz to 10MHz. Observe the output voltage waveform on an oscilloscope to make sure that the output voltage remains undistorted at all frequencies (the output amplitude should never exceed 100mV peak). Plot both the log magnitude and phase of A 1 . Keep in mind that the analyzer is actually measuring – A 1 , so you will have to subtract 180° from the measured phase. 3. Build the non-inverting circuit you designed in step 4 of the preparation. Using the network analyzer, measure and plot the log magnitude and phase of the closed-loop gain from 1kHz to 10MHz. The analyzer output is connected as V s , the analyzer ‘R’ input is measuring V s , and the analyzer ‘A’ input is connected to the op amp output (across the 1kΩ load resistor). Observe the output voltage waveform on an oscilloscope to make sure that the output voltage remains undistorted at all frequencies (the output amplitude should never exceed 100mV peak). Indicate the upper 3dB frequency of the closed-loop gain on your plots. Now, using a function generator as V s and with an oscilloscope measuring tha amplifier output voltage, determine the maximum output amplitude for which the output voltage remains undistorted, first for an input sine wave at 1kHz and then for an input sine wave at 50kHz. 4. Build the inverting circuit you designed in step 6 of the preparation. Repeat the measurements you made on the non-inverting circuit for this inverting-mode amplifier. 5. The voltage follower configuration in Figure 6-11 will be used to measure the slew rate of the 741. Con1kΩ vS(t) 1kΩ vO(t) Figure 6-11. A voltage follower configuration for measuring the slew rate. nect the function generator as v S ( t ) . Set the function generator to produce a 1kHz square wave with a peak-to-peak amplitude of 50mV. Observe the output voltage v O ( t ) on an oscilloscope, and obtain a print of the oscilloscope display. Increase the peak-to-peak amplitude to 4V, and again observe the output and obtain a print of the oscilloscope display. Your plots should look something like those in Figure 6-x2. Estimate the slew rate as the slope of the approximately linear rising and falling edges of the output waveform corresponding to the 4V peak-to-peak input. Note that you will have to adjust the oscilloscope triggering and sweep time so that the details of the transitions in the output waveform are visible. DISCUSSION 1. Compare your measured value of V IO with the worst-case value specified on the data sheet. 2. Compare the characteristics of the measured op amp gain A 1 with those obtained via simulation. 3. Compare the measured values of low-frequency gain and 3dB bandwidth for the two feedback amplifiers with the values predicted by your calculations and the values obtained via simulation. In addition, comment on the variation of maximum undistorted output amplitude with frequency for the two feedback amplifiers, based on your measurements. DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual 6-9 4. Compare the values of slew rate you measured with those specified in the data sheet. Using your measured values, estimate the maximum frequency for which a sine wave with a 6Vpeak output amplitude would remain unaffected by slew rate (consider the maximum rate-of-change of this sine wave; up to what frequency does this rate-of-change remain less than the slew-rate value?). Take into account the fact that the slew rate is equal to the maximum possible rate-of-change of the output voltage. DRAFT 22:1 on 24 January 2005 6-10 Experiment 6: The 741 Operational Amplifier DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual 7-1 Experiment 7: CMOS NAND Logic Circuits In this experiment we will examine the static and dynamic characteristics of CMOS NAND logic circuits. PREPARATION The basic CMOS inverter circuit is shown in Figure 7-1. The circuit can be converted into a 2-input CMOS NAND gate as shown in Figure 7-2. The circuit in the figure employs positive logic, with V ( 0 ) = 0V and V ( 1 ) = 5V . The truth table for this circuit, which is that of a NAND function (AND followed by inversion), is also shown in Figure 7-2. Note from its truth table that if one input of a 2-input NAND is connected to a logic ‘1’, the gate acts as an inverter with respect to the other input. Similarly, the gate acts as an inverter if the two inputs are connected together. The CD4011, a so-called “quad 2-input NAND” (i.e. it contains four independent 2-input NAND gates in a single package) will be used in this experiment. The data sheet for the CD4011 is in the file CD4011.pdf. Note from the data sheet that the CD4011 is described as a “buffered” NAND gate. This means that each gate in the chip consists of the basic NAND gate shown in Figure 7-2 followed by a pair of inverters. The inverters act as buffers, permitting off-chip loads to be driven and establishing a very sharp transition in the transfer characteristic. +5 M2 M1 vI vO Figure 7-1. A CMOS inverter. +5 NAND Truth Table M4 M3 A 0 B 0 1 0 1 Y 1 1 1 0 M2 vY vB A B M1 V(0) = 0V V(1) = 5V Y 0 1 1 vA Figure 7-2. A 2-input CMOS NAND gate, its circuit symbol, and its truth table. DRAFT 22:1 on 24 January 2005 7-2 Experiment 7: CMOS NAND Logic Circuits 1. Using the truth table for the 2-input NAND in Figure 7-2, verify that if either input is set to a logic ‘1’, the gate acts as in inverter with respect to the other input. 2. Obtain the typical values at 25°C of V OL , V OH , V IL , and V IH from the data sheet (in the “DC Electrical Characteristics” table), for positive logic (logic ‘0’ is 0V, logic ‘1’ is V DD = 5V ). From these values, estimate the nominal noise margins NM H and NM L . 3. Estimate the worst-case values of the noise margins at 25°C from the worst-case (minimum or maximum, as appropriate) values of V OL , V OH , V IL , and V IH given in the data sheet. 4. Look at the figures in the data sheet that show the transistion times t THL and t TLH , and those that show the propagation delay times t PHL and t PLH . Note the values specified for these parameters in the accompanying table (labeled “AC Electrical Characteristics”) for V DD = 5V , and the fact that these values depend on load capacitance C L (with C L = 50pF for the typical values listed in the table. Note also that the values specified result from an input pulse with 20nsec rise and fall times. The transition and propagation delay times are defined as follows: • t THL : time for output voltage to fall from 90% to 10% of the total output swing ( V OH – V OL ) . • t TLH : time for output voltage to rise from 10% to 90% of the total output swing ( V OH – V OL ) . • t PHL : period from the point at which a rising transition at the input reaches 50% of V DD to the point at which the resulting falling transition at the output reaches 50% of ( V OH – V OL ) . • t PLH : period from the point at which a falling transition at the input reaches 50% of V DD to the point at which the resulting rising transition at the output reaches 50% of ( V OH – V OL ) PROCEDURE Use a DC power supply set to +5V as V DD for this experiment. Connect the V SS pin to ground. 1. Measure the transfer characteristic of one of the four gates in the package. Set up the gate as an inverter by connecting one of its inputs to V DD . Vary the DC voltage connected to the other input from 0 to 5V, and measure the output voltage. Adjust the input voltage step size so that you see the details of the transition from high to low at the output. Note that because of the buffering within the chip, the transition in the transfer characteristic will be extremely sharp. 2. Repeat the previous part, connecting the cariable DC coltage to the input previously held fixed at +5V and vice versa. 3. Using one of the four gates in the package, verify statically its operation as a NAND gate as follows: For each of the four input combinations in the truth table in Figure 7-2, set up the input conditions by connecting the inputs to the +5V supply or ground as appropriate, and measure the DC output voltage. 4. The switching speed of the CMOS NAND gate will be measured by connected the gates as inverters in cascade, as shown in Figure 7-3. Use the function generator for v S ( t ) . Set the function generator to produce a 100kHz square wave with an amplitude of 0 to 5V, and connect it to one input of the first gate with the other input of the gate connected to the +5V power supply (see the figure). Observe on the oscilloscope the input of the first gate (i.e. v S ( t ) ) and the outputs of the first, second, and third gates. Obtain prints of the oscilloscope display showing details of the low-to-high and high-to-low transitions for these four waveforms. You may need to adjust the scope trigger settings differently for each of these; using the function generator output as an external trigger signal to the scope may be helpful. From the displayed waveforms, estimate the following: a. Delay time from the low-to-high transition at the input of the first gate to: DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual 7-3 vO1(t) vO2(t) vS(t) +5 +5 +5 vO3(t) Figure 7-3. Measuring the switching speed of CMOS NAND gates. •the high-to-low transition at the output of the first gate •the low-to-high transition at the output of the second gate •the high-to-low transition at the output of the third gate b. Delay time from the high-to-low transition at the input of the first gate to: •the low-to-high transition at the output of the first gate •the high-to-low transition at the output of the second gate •the low-to-high transition at the output of the third gate Measure all delay times from the 50% points on the waveform transitions (see the definitions in step 4 of the preparation above). Note that for the speed measurements here, it makes no difference which input of a gate is used as the actual input and which is connected to the +5V supply. 5. Connect two of the NAND gates with inputs cross-coupled, as shown in Figure 7-4. Verify that the circuit behaves as a Set/Reset latch, as follows: a. Power up the circuit with S and R connected to +5V. Measure the voltages at the outputs (Q and Q ). Note that the circuit can come up in either of two stable states: Q = 5V and Q = 0 , called the set state; or Q = 0 and Q = 5V , called the reset state. b. If the circuit came up in the reset state, attempt to set the latch by reducing the voltage st the S input to 0. Verify that the circuit is now in the set state by measuring the output voltages. Restore the voltage at the S input to 5V, and verify that the circuit remains in the set state by measuring the output voltages. Now, with the voltage at the S input held at 5V, attempt to reset the latch by reducing the voltage at the R input to 0V. Verify that the circuit is now in the reset state by measuring the output voltages. Restore the voltage at the R input to 5V and verify that the circuit remains in the reset state. c. If the circuit came up in the set state, carry out the previous step in reverse order; i.e., first reset the latch using R , and then set it using S . S Q R Figure 7-4. A simple Set/Reset latch. Q DRAFT 22:1 on 24 January 2005 7-4 Experiment 7: CMOS NAND Logic Circuits DISCUSSION 1. From your measured transfer characteristics, estimate the points on the characteristics at which the slope is –1 (if the transitions are extremely sharp, then these are the points at which the transitions occur). From these points, estimate the values of V OL , V OH , V IL , and V IH ; also, estimate the noise margins NM H and NM L . Do this for each of the two inputs from which you measured a transfer characteristic, and compare the results. Also, compare your measured results with the values you obtained from the data sheet. 2. Comment on the switching times you measured. In particular, compare the delay times you measured with the typical values in the data sheet. From the delay time of the first gate in the chain (i.e. from v S ( t ) to v O1 ( t ) ), estimate the net load capacitance on the output of this gate assuming the following approximate relationship: t PLH ≈ 80ns + ( 0.90ns/pF ) ( C L ) with C L in pF. 3. Comment on the operation of the latch circuit. DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual A-1 Appendix A. Overview of the HP3577A/B Network Analyzer Introduction The HP3577A/B network analyzers are instruments that can measure the frequency-domain characteristics of a passive or active electrical network over the frequency range of 5Hz to 200MHz. The built-in generator produces a signal that is connected as the input signal to the network under test. The network output, or any other voltage in the network, can be monitored using one of the three analyzer inputs, namely R, A, and B.1 The analyzer can sweep the generator output frequency either linearly or logarithmically through a preset range, while maintaining the detectors at all three inputs tuned to the output frequency as it is swept. The resulting measurements are stored internally in the analyzer as digital complex values. The two-trace CRT can be configured to display these values in a number of different formats, e.g. real and imaginary parts or log magnitude and phase vs. linear or log frequency. Polar plots are also available. Front Panel and Display The HP3577 is menu-driven. The different menus are selected using the “hard-keys”, or push-buttons, on the front panel. When a hard-key is pressed, its associated menu is displayed along the right-hand side of the CRT. Try pressing one of the hard-keys, say the one labelled FREQ near the upper right-hand corner of the front panel, and watch the display change. The desired menu function can then be selected by pressing the appropriate soft-key (one in the column of eight unlabelled push-buttons to the right of the display). When a soft-key is pressed, it becomes active and its menu display lights up. The display itself is divided into several sections. As already noted, the menu section is along the right-hand side of the display next to the soft-keys. In the upper left-hand side of the display, the reference level (dashed line on the screen) value and scale in units/division are given for each trace. To the right of this is the marker information block. The marker frequency is displayed in Hz as is the y-coordinate value for this frequency. The selected input and function being displayed (based on settings from the INPUT and DISPLY FCTN hard-keys) are also shown for each trace. The two traces are superimposed on the screen graticule. Also within the graticule area is the data-entry block. This appears when a soft-key is active, and in it is displayed the current value of the parameter or a new value as it is being entered. Besides the display, the front panel is divided into five sections. These are Display Format, Source, Receiver, Instrument State, and Data Entry. Each of these sections contains hard-keys associated with the functions for that section. A general summary of these functions follows: • The Display Format section controls what is displayed for each of the two traces on the CRT display. • The Source section controls sweep type, sweep range, and amplitude for the analyzer’s output signal. • The Receiver section controls the characteristics of the analyzer’s three inputs, including input impedance and attenuation. • The Instrument State section controls the plotting of data and other miscellaneous functions. • The Data Entry section, consisting of a ten-digit keypad, a continuously variable entry control, and increment keys, is used to enter and modify most of the user-settable parameters in the instrument. These parameters can be altered while their associated soft-keys are active. When a soft-key is pressed, the menu item and its present value are displayed in the data-entry block within the graticule area of the CRT display. New data can now be entered from the keypad. When this method is used, the menu is changed to show a selection of units after the first character is entered from the keypad. The new entry is displayed in the data-entry block as it is typed in. The entry is completed and 1. Note that the HP3577B has no ‘B’ input. DRAFT 22:1 on 24 January 2005 A-2 “entered” by selecting the desired units for the entry from the menu, using the adjacent soft-key. Data can also be entered using the increment (up-arrow) and decrement (down-arrow) hard-keys. Finally, the knob may also be used for data entry. The hard-key above the knob toggles it between marker-control and data-entry modes. Rotating the knob increases or decreases the current value of the selected parameter, depending on the direction of rotation. Setting Up a Measurement The instrument parameters that must be configured as part of setting up a measurement include input, display function, sweep type, frequency, and amplitude. For each of these, depressing the specific hard-key will cause the associated menu to be displayed on the CRT; then, use the soft-keys to configure select the desired setting. INPUT and DISPLY FCTN must be chosen separately for each trace if both traces are selected, in which case the soft-keys alter the parameters of the active (highlighted) trace. Trace 1 is the default. With either trace active, depressing the INPUT hard-key causes a menu to be displayed that includes A, B, A/R, etc. Selecting A using the adjacent soft-key will cause functions associated with the signal received at input A to be displayed. Selecting A/R will cause functions associated with the ratio of the signal at input A to the signal at input R, i.e. essentially the gain from the point in the circuit connected to input R to the point in the circuit connected to input A, to be displayed. The function to be displayed is selected using (you guessed it!) the DISPLY FCTN hard-key. Depressing this key results in the display of a menu that includes log magnitude, phase, real part, imaginary part, etc. A typical gain measurement might have A/R selected as the input for both traces (with inputs R and A connected to the appropriate points in the circuit), with one trace displaying log magnitude and the other displaying phase. For either trace, the SCALE hard-key is used to set the vertical scale of the graticule, including units (e.g., V, mV, dB, dBV, etc.) and units/division. SCALE is also used to set the value of the reference level and its position on the screen. Since the true y-axis values are not marked on the graticule itself, the value of the y-coordinate for any point on a plot must be determined either from the vertical scaling and the position and value of the reference level, or by moving the marker to that point (see below). Sweep type, frequency, and amplitude must be the same for both traces unless “alternate sweep” is chosen from the SWEEP TYPE menu. In most cases, this alternate sweep feature is not needed. For typical gain measurements, a log frequency sweep is generally selected from the SWEEP TYPE menu. The upper and lower limits of the sweep are selected by depressing the FREQ hard-key. To enter the starting frequency for the sweep, depress the soft-key adjacent to “start frequency” on the menu and then key in a value from the data-entry keypad; the menu will automatically change to display a choice of units, and the entry is completed by depressing the appropriate soft-key. The upper limit for the sweep is set in the same way, using the “stop frequency” stop key. The amplitude of the analyzer’s generator output signal is set from the AMPTD menu. Available units include V, mV, and dBV; it should be recalled that ‘dBV’ is a logarithmic measure of voltage with a reference of 1Vrms, i.e. 0dBV = 1Vrms . Using the Marker The marker provides information about the coordinates of points on the trace. This information is displayed above the right-hand side of the graticule. The user controls the frequency of the point at the marker by either rotating the data-entry knob of using the increment/decrement hard-keys when the soft-key marker-position is active. The marker may be set to a user-selected reference position by depressing the “zero marker” soft-key from the MKR menu. The MKR→ hard-key causes a menu to be displayed that provides several DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual A-3 extremely useful functions. Depressing the “MKR → MAX” (or “MKR → MIN”) soft-keys causes the marker to move automatically to the point on the active trace with the maximum (or minimum) y-coordinate value. The “marker search” soft-key displays another menu that is used to find a target value of the trace. The soft-key adjacent to the “marker target” entry is used to set this target value, and the marker can then be moved to the right or the left to this value by depressing the “MKR → R TARG” or “MKR → L TARG” soft-key. Note that if the marker has been “zeroed” at a reference position, the target value will be understood to be an offset from the trace value at the marker reference position. For example, consider using marker functions to find the upper 3dB frequency of a low-pass log magnitude response displayed on the CRT. To begin, move the marker to a frequency in the passband of the response; for a low-pass response, this would most likely be at the left-hand end of the trace. Set the marker reference at this point using the “zero marker” soft-key from the MKR menu as described above. To move the marker to the upper 3dB frequency, depress the MKR→ hard-key and then the “marker search” soft-key. Set the “marker target” parameter to –3dB using the data-entry keypad. Finally, depress the “MKR → R TARG” soft-key. This will set the marker automatically at the upper 3dB frequency (assuming it is within the range of the frequency sweep displayed on the screen). In order to have the marker position displayed in absolute instead of offset frequency, return to the MKR menu and turn the “marker offset” off. Plotting with the HP Plotter To plot from the analyzer display, the analyzer’s GPIB interface must be in “talk-only” mode. This is done by depressing the SPEC FCTNS hard-key, and toggling the “talkonly on-off” soft-key so that “talk-only” is on. The plotter’s GPIB interface must be in “listen-only” mode, which can be accomplished by setting all the address switches on the plotter’s rear panel to ‘1’. Make sure that paper has been properly loaded into the plotter before starting to plot. The analyzer’s plot menu, is displayed when the PLOT hard-key is depressed. The CRT display can be plotted in its entirety, exactly as seen, using the “plot all” function on the plot menu. Alternatively, parts of the display can be selected for plotting by choosing the appropriate menu entries. “Extra” markers can be added to a plot at points of interest using the “plot marker 1” and “plot marker 2” soft-keys; this produces a cross-hair marker with coordinate information written adjacent to it. Each of the abovementioned soft-keys initiates a separate plotting process, but the HP plotter will overlay all the plots to produce a coherent result. The “config plot” soft-key produces a menu from which pen numbers (and thus colors) and line types can be selected. Some Practical Considerations In the experiments in this laboratory manual, the HP3577 network analyzer is used to measure the frequency-domain characteristics of linear active and passive networks, in the frequency range from 10Hz to about 10MHz. We generally consider the analyzer’s signal generator to be an ideal voltage source, and connect a specified source resistance between the generator output and the rest of the circuit. We can do this, despite the fact that that the generator has a non-zero output impedance (nominally 50Ω), because we can reference gain measurements to the point at which the the generator output is connected to the circuit by also connecting this point to the R input of the analyzer. Because we want the analyzer to measure signal voltages in a circuit without disturbing the operation of the circuit, we must configure the analyzer inputs to have an input impedance of 1MΩ rather than 50Ω (the default value); this is done using the menus that appear when the ATTEN hard-key is depressed. To increase the input impedance further (to about 10MΩ), it is a good idea to use 10X oscilloscope probes on the inputs. While the compensation of the probes may not perfectly match the capacitances at the analyzer inputs, it should be close enough for accurate measurements up to about 10MHz (and if necessary the compensation of the probes can be adjusted). The 10X probes will introduce 20dB of attenuation (scaling by 0.1), so that the DRAFT 22:1 on 24 January 2005 A-4 signal amplitude at the analyzer input will be 20dB below that at the probe in the circuit. This is also a beneficial effect, since tha analyzer inputs overload at a relatively small input signal level. If the inputs tend to overload even with the 10X probes in place, an additional 20dB of attenuation can be introduced in the analyzer, using the menus that appear when the ATTEN hard-key is depressed. Remember that when you use a 10X probe on an analyzer input, the signal level at that input displayed be the analyzer will be 20dB below its true value; on the other hand, the analyzer will automatically compensate for the use of its internal 20dB attenuators. DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual B-1 Appendix B. Integrated BJT Arrays The bipolar transistors (BJTs) in the laboratory exercises in this manual are the Intersil CA30461 npn integrated transistor arrays. Data sheets for the npn devices are in the file CA3045.pdf. The CA3046 consists of five matched npn devices; two of the devices have their emitters connected together, while the others are completely independent. The matching is achieved by fabricating transistors with nominally identical geometries adjacent to one another in an integrated circuit. Because the devices are well matched, they can be used to construct differential pairs, current mirrors, and other circuits that are the basic building blocks of bipolar IC structures and that rely on device matching for proper operation. The SPICE model for the npn devices in the CA3046 is: .MODEL CA3046 NPN IS=10.0E-15 BF=145.76 VAF=100 IKF=46.747E-3 + ISE=114.23E-15 NE=1.4830 BR=.1001 RC=10 + CJE=1.0260E-12 MJE=.33333 CJC=991.79E-15 + MJC=.33333 TF=277.09E-12 TR=10.000E-9 1. The same parts are available from other vendors with different part numbers (e.g. National LM3046). DRAFT 22:1 on 24 January 2005 B-2 DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual C-1 Appendix C. LM741 Op Amp Macromodel The Pspice macromodel for the LM741 op amp, taken from the library file nat_semi.lib, is as follows: *////////////////////////////////////////////////////////////////////// * (C) National Semiconductor, Inc. * Models developed and under copyright by: * National Semiconductor, Inc. *///////////////////////////////////////////////////////////////////// * Legal Notice: This material is intended for free software support. * The file may be copied, and distributed; however, reselling the * material is illegal *//////////////////////////////////////////////////////////////////// * For ordering or technical information on these models, contact: * National Semiconductor’s Customer Response Center * 7:00 A.M.--7:00 P.M. U.S. Central Time * (800) 272-9959 * For Applications support, contact the Internet address: * amps-apps@galaxy.nsc.com *////////////////////////////////////////////////////////// *LM741 OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM741/NS 1 2 99 50 28 * *Features: *Improved performance over industry standards *Plug-in replacement for LM709,LM201,MC1439,748 *Input and output overload protection * ****************INPUT STAGE************** * IOS 2 1 20N *^Input offset current R1 1 3 250K R2 3 2 250K I1 4 50 100U R3 5 99 517 R4 6 99 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=2.55 MHz C4 5 6 60.3614P * DRAFT 22:1 on 24 January 2005 C-2 ***********COMMON MODE EFFECT*********** * I2 99 50 1.6MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 1E-3 1 *Input offset voltage.^ R8 99 49 40K R9 49 50 40K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.63 D1 9 8 DX D2 10 9 DX V3 10 50 1.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 9 5 6 2.1E-3 *Fp1=5 Hz R5 98 9 95.493MEG C3 98 9 333.33P * ***************POLE STAGE*************** * *Fp=30 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 5.3052E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=300 Hz G4 98 16 3 49 3.1623E-8 L2 98 17 530.5M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 450U 1 E1 99 23 99 15 1 R16 24 23 25 D5 26 24 DX V6 26 22 0.65V R17 23 25 25 D6 25 27 DX V7 22 27 0.65V V5 22 21 0.18V D4 21 15 DX V4 20 22 0.18V D3 15 20 DX L3 22 28 100P RL3 22 28 100K * DRAFT 22:1 on 24 January 2005 ECE163 Lab Manual C-3 ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=625) * .ENDS *$ DRAFT 22:1 on 24 January 2005