# Fractional N PLLs

### Pages to are hidden for

"Fractional N PLLs"

```					Fractional N PLLs
Presented by:
Dean Banerjee, Wireless
Applications Engineer
Overview

• Fractional N PLL Architectures
– Delta Sigma Fractional PLLs
• Z Transform Review
• Delta Sigma Noise Shaping Concepts
• Performance Differences
– Phase Noise
– Spurs
– Summary of Differences
Fractional N Example

1000 kHz
Output
1/R         φ
Kφ
1/5                                   900.2 MHz
10 MHz                                      VCO
Crystal
Reference

1000 kHz

1/N
900 1/5

Fractional N Operation
Note that if one was able to make N in the resolution of 1/5, then the
comparison frequency could be 5 times larger, as shown. In other words, a
1000 kHz reference frequency is used instead of a 200 kHz reference
frequency.

Fractional N Modulus
The fractional N modulus is the denominator in the fraction. In this case,
since the fractional part can be 1/5, 2/5, 3/5, 4/5, or 0, the modulus is 5. Note
it is desirable to have a larger fractional modulus, since it allows a higher
comparison frequency.

Comparison Frequency and Channel Spacing
The comparison frequency is the frequency presented to the phase detector. In
the case of an integer PLL, the comparison frequency and the channel spacing
are the same. However, for a fractional PLL, these two will be different. In
the above example, the comparison frequency is 1000 kHz, yet the channel
spacing is 200 kHz.
Fractional N Implementation

• Uses Fractional N Averaging
900              First Time
900              Second Time
900              Third Time
900              Fourth Time
901              Fifth time
900.2            Average Value

• Although the Average Value is correct,
compensation is necessary to correct for the
instantaneous phase error. This phase error
gives rise to fractional spurs. They would be at
offsets that are increments of 200 kHz in this
example.

Fractional N Averaging
The way that a fractional N value is realized when the N counter is actually a
bunch of flip flops (which are integer dividers) is by oscillating between two
or more values. This method is called fractional N averaging. In this
example, the PLL divides by 900 for the first comparison cycle. Then again it
divides by 900 for the second, third, and fourth comparison cycles. Now for
the fifth comparison cycle, the divider value switches to 901. The average of
all these values is 900.2. By doing this method, the proper frequency will be
achieved, but there will be instantaneous phase errors that give rise to huge
fractional spurs. These are spurs that occur at the channel spacing, which is
200 kHz in this case. In order to reduce these spurs, compensation is
necessary.
The Need for Compensation
1/R
φ
Kφ

900.2 − 900
ε =
900. 2 MHz

1/N

Desired
Divider
Output

Actual
ε          2ε                3ε          4ε
Divider
Output

0 uS        1 uS        2 uS              3 uS          4 uS   5 uS

Fractional Compensation
This diagram assumes that the VCO output frequency is 900.2 MHz. The
theoretical output of the desired 900.2 divider is shown in the blue graph. The
period is 1 uS and the frequency is 1 MHz. Note that the N counter squares up
the input signal so only the rising edges are relevant, which are represented by
the arrows. Now the actual divider divides by 900 instead of 900.2 for the first
cycle. Because it is dividing by a number that is too small, the resulting
frequency at the output will be slightly higher than it should. The period is
therefore shorter by a small time increment, which works out to be 0.222 nS.
This phase error accumulates for the second, third, and fourth cycles. Now for
the fifth cycle, the actual divider divides by 901. The resulting period of the
output signal is therefore longer than 1 uS and it turns out that this phase error
cancels at the fifth cycle. After the fifth cycle, the process repeats.
Fractional Compensation
METHOD 2:
Crystal                                  Current
Reference                               Compensation

1/R                                Loop                 VCO
φ
Kφ            Filter               Output
METHOD 1:

∆t
Delay
Compensation

Σ         1/N

METHOD 3:
Delta Sigma
Compensation

Fractional compensation is an art, and implementation is important. If
compensation were perfect, there would be no fractional spurs and no added
phase noise. However, this is not the case. Newer fractional PLLs have
learnings that help designers improve the fractional compensation as to lower
fractional spurs and reduce phase noise. The basic methods used are as
follows:

Method 1: Delay Compensation Technique
Because the root cause of the fractional spur is a phase error at the phase
detector, the most intuitive way to fix this is with a phase delay. This is the
routine used in National’s LMX2350/52/53/54/64. The delay technique tends
to add a little phase noise, but gives more control over the fractional spurs.

Method 2: Current Compensation Technique
Competitors PLLs such as the Philips SA8026 use current compensation
technique. This technique involves allowing the phase error to get to the phase
detector and then canceling out the erroneous currents produced with another
current. The advantage of this technique is that it tends to add less phase noise
than delay compensation, but it is very difficult to deal with the variations of
this current over temperature and process. It also requires the user to do a
manual calibration for this current.

Method 3:        Delta Sigma Compensation
This is a more complicated form of digital spur compensation and is discussed
in later slides.
Overview

• Fractional N PLL Architectures
– Delta Sigma Fractional PLLs
• Z Transform Review
• Delta Sigma Noise Shaping Concepts
• Performance Differences
– Phase Noise
– Spurs
– Summary of Differences
∆Σ Modulators

1/R                                Loop                 VCO
φ
Kφ            Filter
Crystal                                                               Output
Reference

Σ        1/N

1st Order Modulator:      0, +1
2nd Order Modulator:     -2, -1, 0, +1
3rd Order Modulator:     -4, -3, ... +2, +3
4th Order Modulator:    -8, …, +7
Nth Order Modulator:    -2^N … 2^N-1

Delta Sigma Modulators
First Order Modulator
The first order modulator has already been covered. In this case, the PLL
alternates between two values. This can be viewed as taking a nominal value
and adding either 0 or 1 to it. In the example that has been used, 0 would
correspond to 900 and 1 would correspond to 901. The first order delta sigma
modulator is considered a trivial case and does not have any sort of
compensation.
Second Order Modulator
The second order modulator achieves the result by alternating between four
values ( 2^2 = 4). For instance, to produce a fractional value of 900.2, it
would alternate between 898, 899, 900, and 901. Again, the lowest value is
mapped to 0. So this is viewed as taking 900 and adding –2, -1, 0, or 1 to it.
The effect of this it is that it reduces the fractional spurs.
Third and Higher Order Modulators
Higher order modulators just alternate between more values in order to reduce
the fractional spurs even more.
1 Minute Z Transform Course

X(z) = ∑ n=0 x(n) • z −n
∞

• Not exactly, but sort of like a discrete
version of the Laplace transform
• z-1 represents 1 clock cycle delay

This definitely does not do justice to the Z transform, but just understanding
the clock delay part is enough to introduce sigma delta PLLs. Note that n is a
discrete integer, but z is continuous variable. Z transforms find their way into
discrete signals and systems. They can also be used to solve difference
equations. It’s actually more accurate to say that the Z transform of x(n) can
be interpreted as the Fourier transform of x(n)*r^(-n), but this is beyond the
scope of this presentation.
Throughout this presentation, it should be understood that x[n] represents the
sequence in the time domain and X(z) represents the Z transform of x[n]. So
to refer to the signal in the time domain, x[n] is used, and to refer to this in the
Z domain, X(z) is used. It is useful sometimes to switch back and forth
between the time domain and the Z domain because the time domain is more
intuitive, but the computations are easier to do in the Z domain.
Accumulator in Z Domain

• X(z) is the input
• Add Previous value to current value
• Transfer Function:
X(z)
Y(z) =
1 − z −1

X(z)                                                Y(z)
Σ
+       +

z −1
−

Let’s think about the above diagram. Y(z) represents the current value of the
output and X(z) represents the input. When Y(z) is multiplied by z-1 in the
feedback path, this means it is what it was in the previous clock cycle. The
relationship can be expressed in the time domain as follows:
y[n] = x[n] + y[n-1]
Now this can be arranged as:
y[n] – y[n-1] = x[n]
The term on the left hand side is a finite difference, which is the discrete
analogy to a derivative (dy/dt). The solution to this in the continuous domain
is y is the integral of x plus a constant. In the discrete domain, it is y is the
summation of x plus a constant.
y[n] = sum{x[k], k=1,2,…n} = x[1] + x[2] + … x[n]

Now in the Z domain the relationship can also be derived
Y(z) = X(z) + Y(z)*z-1
This can be arranged as follows:
Y(z) = X(z) / (1-z-1)
Note that multiplying by something by 1/(1-z -1) is the equivalent of taking a
summation.
First Order ∆Σ Noise Model

E(z):
Quantization Noise
Fractional             Accumulator model
Value                   in Z domain
+
X(z)                       1                   +
Σ                                         Σ               Y(z)
+
−
1 − z −1
-
−
z −1

The above diagram shows what a first order delta sigma modulator looks like
in the Z domain. It is easiest to understand this by use of an example.
Consider having an N divider value of 900.2. This makes the fractional word
0.2. So the time domain input to this device would be: x[n] = 0.2. Now if
quantization noise were zero, then e[n] = 0. Working this through we would
derive that:
y[n] = 0.2
Now the problem comes in that the PLL dividers can not directly synthesize
this fractional value of 0.2. There the output y[n] must be either 0 or 1 for
every n. In this case, the error caused by this is called quantization noise,
represented by E(z). The table below shows a sample output sequence. Note
that the units of all numbers are in cycles, which is a dimmensionless unit.

x[n]                 Accumulator                   e[n]                   y[n]
N Value
0.2                                                0.2
-0.2                                                0
900
0.2                                                0.4
-0.4                                                0
900
0.2                                                0.6
-0.6                                                0
900
0.2                                                0.8
-0.8                                                0
900
0.2                                                1.0
-0.0                                                1
901
∆Σ Noise Shaping Equations

Y(z) = [ X(z) - Y(z) ] • 1 + E
Y(z) = X(z) + E • (1 - z -1 )

Finite Difference --
Loop Filter will filter.
Discrete analogy to
high pass filter
Desired Signal

This slide takes the block diagram from the previous slide and works out the
transfer function. The first line is derived by studying all signals at the output.
The second line is just a rearrangement of the first line. In the second line, we
see that the desired output signal is passed through unchanged and and a finite
difference is applied to the phase quantization error, E(z). Taking a finite
difference is the discrete analogy of taking a derivative. If the function is
constant, a derivative is zero. Therefore, the finite difference can be viewed as
a form of high pass filtering.
High Order ∆Σ Modulators

• Increasing the order of a Σ∆ modulator (adding more integrators to the
modulator) enhances the noise shaping effect.
Y(z) = X(z) + (1 - z -1 ) 3 • E
• More Loop Filtering is necessary
– i.e. Loop Filter Order = Sigma Delta Order + 1

3rd Order ∆Σ Modulator
Quantization Noise Power

2nd Order ∆Σ Modulator
(Not to Scale)

1st Order ∆Σ Modulator
Unshaped Noise Level

Fcomp/2

Equation for Higher Order Modulators
For higher order modulators, higher order finite differences are taken of the
quantization error term. For a kth order modulator, the exponent is k. The
effect of this is the high pass filtering property is increased.

Filtering Requirements for Higher Order Modulators
Now recall that the noise in a delta sigma modulator is not being filtered, but
rather re-shaped. The concept is that the loop filter of the PLL can filter out
the higher order quantization noise. Quantization noise manifests itself in the
form of fractional spurs. Higher order modulators are theoretically better,
because they push out the fractional spur energy (quantization noise) to higher
frequency. However, they do require more filtering. If the filtering is
insufficient, then additional fractional spurs that occur at frequencies that are a
fraction of what the traditional fractional spurs come in. The equation:
Loop Filter Order = Sigma Delta Order + 1
is a consequence of applying the constraint that the noise must degrade at a
rate of 20 dB/decade outside the loop bandwidth. For the 1st order modulator,
the noise increases at a rate of 20 dB/decade. Therefore the filter must
attenuate at 40 dB/decade. A second order filter has a pole at 0 and another at
T1, therefore it has 40 dB/decade roll-off . For the 3rd order modulator, the
noise increases at a rate of 60 dB/decade. Therefore the filter must attenuate
at 60 dB/decade. The 3rd order filter has a pole at 0 and the poles T1 and T3,
and therefore has 60 dB/decade roll-off.
∆Σ Filtering Example

40

30

20

10                                                         NSM Stock Price
1st Order Modulator
0                                                         3rd Order Modulator
1

6

11

16

21

26

31

36

41

46

51
-10

-20

-30

• For this example, the National stock price was used to represent the
quantization noise and was high pass filtered through a sigma delta
modulator

This shows an example of where the delta sigma modulator equations were
applied to the stock price of National Semiconductor. With the first order
modulator, much of the high pass filtering should be evident in the fact that
the DC component is gone. The third order modulator has higher frequency
components than the output of the first order modulator.
Overview

• Fractional N PLL Architectures
– Delta Sigma Fractional PLLs
• Z Transform Review
• Delta Sigma Noise Shaping Concepts
• Performance Differences
– Phase Noise
– Spurs
– Summary of Differences
Phase Noise Potential
Comparison
PN1Hz     -214.0  -213.0   -214.8  -217.8  -207.0  -208.8   -215.0
FcompKnee 15000      1400     1200    1200    1000    4000    10000
MaxKphi
-60.01000    4000     4000    4000    1600   16000     1600
KphiKnee    1000    1400     1000      0      50      800     2000
MaxMod -65.0 1       1         1       1      16      128   4000000
Part    LMX2326 LMX2310 LMX2330U LMX2346 LMX2354 LMX2364 LMX2470
1 -70.0 -61.0  -61.7     -63.8   -67.8  -68.8   -79.5    -101.5
LMX2326
5       -68.0  -68.7     -70.8   -74.8  -75.6   -86.0    -101.5
10 -75.0-71.0  -71.7     -73.8   -77.8  -78.3   -88.5    -101.5     LMX2310
Phase Noise

50      -78.0  -78.5     -80.6   -84.6  -83.3   -92.5    -101.5
100 -80.0-81.0  -81.4     -83.5   -87.5  -84.8   -93.4    -101.5     LMX2330U
500      -87.8  -87.4     -89.3   -93.3  -86.4   -94.3    -101.5
LMX2346
1000      -90.7  -89.4     -91.2   -95.2  -86.6   -94.5    -101.5
-85.0
5000      -96.7  -92.1     -93.7   -97.7  -86.8   -94.6    -101.5     LMX2354
10000      -98.8  -92.6     -94.1   -98.1  -86.8   -94.6    -101.5
-90.0                                                   LMX2364
-95.0                                                   LMX2470

-100.0
-105.0
1   10         100         1000         10000
Channel Spacing (KHz)

Fractional vs. Integer PLL Phase Noise
A common question regarding fractional PLLs is what is the real advantage in
phase noise. Indeed fractional PLLs should have better phase noise due to the
smaller N counter value, but the fractional compensation does add phase noise.
When the channel spacing is very small, fractional PLLs provide the most
benefit because they allow higher comparison frequencies. However, a study
of many PLLs shows that raising the comparison frequency does improve
phase noise to a point, but eventually there are diminishing returns from this.
Also, practical issues such as illegal divide ratios in prescalers and the crystal
frequency limit how high the comparison frequency can be increased. When
the channel spacing is low, fractional parts ( shown in various shades of blue)
outperform integer parts by the most margin. However, when the channel
spacing becomes larger ( > 200 kHz ), then it is not always the case that
the phase detector has diminishing returns. This slide is labeled “Phase Noise
Potential”, because it disregards issues with illegal divide ratios with
prescalers and assumes the crystal reference is at least 20 MHz. If a higher
offset is used, the phase noise benefits of using a fractional PLL will be larger.
This data assumes a 4 kHz offset frequency for phase noise measured for a 1
GHz VCO.
Spur Comparison
( Typical Charge Pump Leakage)

0.0
-20.0
LMX2326
-40.0
LMX2310
Spur Level (dBc)
-60.0                                          LMX2330U
-80.0                                          LMX2346
-100.0                                          LMX2354
LMX2364
-120.0
LMX2470
-140.0
-160.0
1   10       100        1000   10000
Channel Spacing (KHz)

At lower channel spacings, the fractional parts outperform integer parts,
because the leakage currents cause excessive spurs. Between 10 kHz and
about 300 kHz, some integer PLLs outperform fractional PLLs. At very high
channel spacings, fractional parts again become better because their spurs roll
off faster with channel spacing. This data assumes a 10 kHz loop bandwidth
and a 1 GHz VCO. As in the case with phase noise, fractional PLLs provide
the greatest benefit for applications with small channel spacings.
Fractional Spur Games

• By avoiding particular fractional numerators,
fractional spurs can be significantly
reduced. This requires good frequency
planning.
• Becomes possible with parts that have high
fractional moduli ( >100) and parts with
higher comparison frequencies.
• Only possible in some particular
applications, like CDMA.

In CDMA applications, it is common to use a fractional denominator of 1968.
It turns out that the smallest fractional numerator required is 7 for some
frequency plans. As a result, the fractional spurs are excellent. Some
competitors make claims on how great their fractional spurs are, but this is not
really the worst case for the part. In some applications, fractional spurs can be
significantly reduced by good frequency planning.
Fractional Spur Games

LMX2364 Uncompensated Fractional Spurs vs.
Fractional Numerator

0.0
-18.3                                               -18.8
-20.0                 -28.0                    -28.2
Spur Level

-40.0
-60.0
-80.0
-100.0
0        20           40          60           80      100
FNUM

This shows the impact of fractional numerator on spurs for a fractional
denominator of 100. For instance, if you can avoid using a numerator of 1 or
99, your spurs are reduced about 10 dB. In general, it is most fair to consider a
fractional numerator of 1 as the first case and study the first fractional spur.
Fractional N vs. Integer N

– Better Phase Noise
– Potential to play fractional spur games
– Best for applications with narrow channel
spacings
• Pitfalls
– Potential for Cycle Slipping
• Make sure your Fractional N PLL has cycle
slipping reduction circuitry.
– More Difficult to Use
– Cost

Fractional PLLs are not for every application. For applications where the
channel spacing is already very wide, their benefit is less. If the comparison
frequency is raised too high, cycle slipping can also result and degrade the
lock time.

```
DOCUMENT INFO
Shared By:
Categories:
Stats:
 views: 44 posted: 10/20/2010 language: English pages: 20