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					Eric Cheung

Personal
Home Address: 1175 W Blaine St, Apt 67, Riverside, CA 92507            Date of Birth: 11/27/1980
Cell Phone Number: (310) 972 – 8854                                    Email: chuncheung@cs.ucr.edu
Education
University of California, Riverside, CA              September 2004 – Present
Ph.D. Computer Science
Degree Expected 2009
GPA: 4.00
University of California, Los Angeles, CA            September 2002 –June 2004
B.S. Computer Science and Engineering
Latin honor: Summa Cum Laude
GPA: 3.91
Dean’s list for four straight quarters
De Anza College, Cupertino, CA                       September 2000 – June 2002
Computer Science
GPA: 4.00
Dean’s list for six straight quarters
Working Experience
Link_A_Media Device, San Jose, CA                    June 2005 – September 2005
Summer Internship, Digital Group
Responsible to develop test plans for several components in a SoC design. Use Synopsys VCS for simulation,
debugging and measuring coverage. Integrate Denali memory models into the design for more accurate simulations.
Teaching Experience
University of California, Riverside, CA             September 2004 – Present
Teaching Assistant, Department of Computer Science
Supervise undergraduate computer science lab sections. Grade homework and projects. Topics include basic
programming techniques, SystemC and Tensilica.
University of California, Los Angeles, CA            January 2003 – June 2004
Reader, Department of Electrical Engineering & Department of Physics & Astronomy
Analyze general and specific weaknesses of students. Assist in grading homework.
Strengths
Strong problem-solving, conceptualization, realization and organization skills
Detail-oriented, curious and enthusiastic
Comfortable in environment where initiative, creativity and individual exploration are encouraged
Technical Skills
Embedded Systems:               Synopsys VCS, Synopsys Design Compiler, ARM processors, VHDL, Verilog,
                                SystemC, Tensilica Xtensa
Computer Architecture:          Computer Architectures, Branch Prediction, Dynamic Scheduling
Programming Languages:          C/C++, STL, Java, Perl, MIPS Assembly, 8086 Assembly
Theory:                         Algorithm, Time and Space Complexity, P/NP problems, Numerical Computation
Network:                        Network Programming, TCP/IP
Operating Systems:              Windows XP/2K/ME/98/95, Linux, Unix
Applications:                   Microsoft Office (Word, Excel, PowerPoint)
School Projects
Profile and annotate energy information in C program with high-level synthesis (VHDL, Synopsys Design Compiler)
Implement Byzantine Fault Tolerate algorithm for distributed systems in SSFNet simulator (Java, SSFNet)
Simulate Tomasulo dynamic schedule computer architecture algorithm (C++, STL, Qt, Linux)
Manipulate FAT file system in a image file (C, Dos)
Use multithreading to simulate operating system scheduling (C, Linux)
Design a Multi-cycle processor (Xilinx FPGA, VHDL)
References
Provided upon request