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					                              ABSTRACT


       Low density parity check (LDPC) codes have been widely
considered as error detection and error correction codes for next generation
communication system. LDPC codes are typically characterized by a
relatively high-complexity description, since a considerable amount of
memory is required in order to store their girth, which can be represented
either by the connections of the edges in their Tanner graph or by the non-
zero entries in their parity-check matrix (PCM).

      Output of the communication channel is input to the LDPC codes that
is 8 bit data to check data. Good error detection codes using LDPC Codes
requires parity check matrix, characteristics of LDPC codes and efficient
error detection architecture. The architecture main blocks are H-matrix,
LDPC testing, regular/irregular, tanner graph. By using these blocks, error
detection operations are performed. In this architecture the power
requirement of LDPC codes is less.

     This project is implemented on Field-Programmable Gate Array
(FPGA) using the VHDL coding and simulated using ModelSim 6.0 for
functional verification. The synthesis of the implemented design is carried
out using XILINX ISE 9.1i tool. The design is implemented in Spartan-3
FPGA kit. The Place and Root simulation results are also provided for the
design.




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posted:10/8/2010
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