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The Challenge for Next Generation Network Processors_1_

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					                        The Challenge for
                        Next Generation Network Processors
                        Agere, Inc.

                                                        Abstract
          Networking hardware manufacturers face the dual demands of supporting ever-increasing bandwidth re-
          quirements, while also delivering new features, such as the ability to implement Quality of Service (QoS)
          and Service Level Agreement (SLA) monitoring. As a result, hardware vendors are increasingly in need
          of a network processor solution that allows them to meet these demands while allowing them to shorten
          time-to-market cycles and thus gain a competitive advantage.
          This paper will provide an overview of how network processor technology has evolved and why current
          processor technology is insufficient to meet future demands. Agere’s “Wicked Smart” approach will be
          shown to offer vendors new hope for delivering a new class of product that combines the performance
          benefits of ASICs with the ease of configuration of software-based devices.


                                                                   terface), multiple or single Token Ring, or even various
                                                                   types of serial ports. On the software side, dozens of
      THE HISTORY OF NETWORK                                       different software versions are available to support
                                                                   highly specific individual requirements.
            PROCESSORS


                                                                                  PHY
Software Based Routers                                                                           RAM            ROM

Up until the late 1990's, most network routers were based
on an architecture similar to a personal computer. A                              PHY PHY
central processing unit performed tasks such as for-
warding table lookups, access control filtering, and proc-
essing of routing updates. The central processor received
instructions from the router operating system that ran in                                             CPU
random access memory (RAM), along with basic in-
structions sometimes stored in read-only memory                         Traditional architectures used CPUs con-
(ROM). The advantage to this architecture was that all                  nected to physical interfaces and memory via
instructions were stored in software; therefore new fea-                a system bus. Through software, these sys-
tures could be added simply by upgrading the system                     tems could perform almost any function on in-
                                                                        coming data.
software, much like a PC. Routers could also easily be
designed with additional interfaces such as support for            The drawback to software-based routers is their limited
V.35 or HSSI (High Speed Serial Interface), without                ability to scale to support the demands of higher band-
having to touch the basic processor architecture.                  width and additional features. For example, most soft-
                                                                   ware-based routers currently available can only support
For vendors, this meant that their basic router architec-
                                                                   wire-speed throughput for less than a single OC-3 at 155
ture could support a variety of configurations as well as
                                                                   Mbps or in some extreme cases, up to a single OC-12 at
different versions of the same basic operating system.
                                                                   622 Mbps. For many software-based routers, delivering
This made it possible for vendors to quickly develop new
                                                                   support for non-blocking performance for more than a
products with a short time-to-market window, and that
                                                                   handful of Fast Ethernet ports is simply out of the ques-
often were geared to very small segments of the market.
                                                                   tion. When these same routers are then asked to per-
A perfect example of this approach was (and still is) the          form complex traffic filtering, policy based routing, or
Cisco 2500 product line. This software based router uses           collection of traffic statistics, their performance suffers
a central processor unit to perform routing instructions           further, and greatly reduces their maximum throughput.
based on software configurations stored in non-volatile
                                                                   Software based routers are typically deployed in a col-
RAM. The Cisco 2500 series is available in a variety of
                                                                   lapsed backbone architecture with local LAN segments
specialized hardware configurations depending on spe-
                                                                   connecting to Ethernet (or Token Ring) ports on the
cific application requirements such as multiple or single
                                                                   router. The router is responsible for forwarding traffic
serial ports, multiple or single AUI (attachment unit in-
                                                                   between segments and for controlling the transmission of
Agere, Inc.                                       The Challenge for                                              Page 1
                                          Next Generation Network Processors
                                                September 10, 1999
broadcast packets. However, as networks have grown,                          works) and many of the Gigabit Ethernet startup compa-
this architecture has become expensive to maintain and                       nies (Yago, Rapid-City, Packet Engines, etc.). These
the router is often a performance bottleneck. New, higher                    switches combined the speed and scalability of ASIC-
speed technologies such as Gigabit Ethernet and Packet                       based traffic processing with the intelligence of tradi-
over SONET can quickly overwhelm the ability of tradi-                       tional software-based routers. Most of these Layer 3
tional software-based routers to process packets fast                        switches were actually hybrids of software routers and
enough. In addition, most software-based routers still                       ASIC-based switches that improved performance by us-
require complex, manual configuration, which adds to                         ing ASICs for frame forwarding, but general purpose
network management complexity.                                               CPUs for control functions (e.g. calculating routes).
                                                                             Another example of this approach is Cisco's NetFlow
The Emergence of ASICs                                                       technology. In a NetFlow network, distributed multi-
In 1990 a new device appeared called the "EtherSwitch"                       layer LAN switches (Catalyst 5000s) provide the frame-
and a new market was born. Developed by Kalpana1, the                        forwarding function and are dependent upon a software-
EtherSwitch was essentially a Layer 2 multi-port bridge2.                    based router for all route calculations. The router for-
Like a bridge, the EtherSwitch learned what devices                          wards path information across the network to each of the
were connected to each port, and only forwarded unicast                      multi-layer switches that the switches then store, so that
traffic to the port to which the destination device was                      the router can be bypassed for future communications.
connected.
                                                                             With very high packet forwarding rates (on the order of
Many Layer 2 switches employed custom Application-                           tens of millions of packets/sec.), Layer 3 switches have
Specific Integrated Circuits (ASICs), Digital Signal                         also become sufficiently inexpensive that their use is
Processors (DSP) or Reduced Instruction Set Computing                        becoming commonplace in the backbone of enterprise
(RISC)-based processors, to forward and control traffic                      building/campus networks. Many Layer 3 switches now
in hardware. In some products, ASICs were combined                           provide support for standard routing protocols such as
with RISC processors to allow the switch to support ad-                      OSPF and RIP, high speed interfaces such as Packet over
ditional features as code was developed. In some ways,                       SONET (POS) and Gigabit Ethernet, and even wide-area
this approach combines the best of both worlds between                       network T1/T3 interfaces. With this support, Layer 3
software and hardware based processing.                                      switches are often used to replace existing networks of
                                                                             software-based routers and Layer 2 switches. Layer 3
The use of ASICs was a major paradigm shift for hard-
                                                                             switches provide tremendous benefits in performance
ware manufacturers. Rather than using software-based
                                                                             and ease of management, especially if VLANs or Layer
processing, and improving performance by increasing the
                                                                             2 traffic filtering are currently in use.
speed of the central processor, hardware manufacturers
found that they could achieve tremendous performance                         While ASIC-based switching has allowed for a new gen-
improvements by creating specialized chips that were                         eration of very high-speed routers and switches, there is
manufactured with embedded instructions and that could,                      a downside to this approach, in that once instructions or
therefore, perform forwarding decisions directly in                          logic have been embedded into silicon, it is difficult to
hardware. This created a new market for chip manufac-                        change them to add new features or to improve perform-
turers as well, as they began to market "off-the-shelf"                      ance. This means that manufacturers must replace the
chips that hardware manufacturers could quickly inte-                        ASICs to enable new functionality, unlike traditional
grate into their new products in order to slash time-to-                     software-based routers and switches in which new fea-
market cycles.                                                               tures can be added by a simple upgrade to the operating
                                                                             system. Errors in the ASIC design during product devel-
While early switching products from companies like
                                                                             opment can result in substantial time-to-market delays
Kalpana could only make traffic forwarding decisions
                                                                             since it sometimes takes months to get a new set of
based on information contained at Layer 2, it wasn't long
                                                                             ASICs produced by a silicon foundry.                    Also,
before switches capable of making forwarding decisions
                                                                             implementation of many advanced features such as com-
based on information at Layers 3 and above arrived on
                                                                             plex quality of service routing, identification of upper
the market. The “Layer 3 Switch” was initially marketed
                                                                             layer flows, gathering of accounting information, or ac-
by companies such as Bay Networks (now Nortel Net-
                                                                             cess control filtering still requires traffic to be processed
                                                                             in software, reducing the performance benefits of the
1
  Kalpana, Inc., is considered to be the inventor of Ethernet switching,     ASIC-based architecture.
and designed and manufactured internetworking products that increased
the throughput of Ethernet networks. Kalpana was acquired by Cisco
Systems in 1994.                                                             Current Network Evolution
2
  “Layer 2” refers to the OSI networking model layer two. The Open           The rise of low-cost, ASIC-based, Layer 2 switches has
Systems Interconnection (OSI) networking model was created by the            had a direct impact on the evolution of the modern net-
ISO (International Organization for Standardization), a worldwide            work architecture. Before Layer 2 switches, the standard
federation that promotes international standards.
                                                                             LAN architecture consisted of shared 10 Mbps connec-
Agere, Inc.                                                 The Challenge for                                              Page 2
                                                    Next Generation Network Processors
                                                            September 10, 1999
tions to each PC or server, with learning bridges used to          for each type of service are going away. Not only do
reduce unicast traffic and to segment collision domains.           they want devices that can rapidly support emerging
With the advent of low cost Layer 2 switches (as well as           technologies, they also want devices that can scale to
inexpensive 10/100 NICs) coupled with the invention of             meet ever-increasing demands for higher bandwidth.
100 Mbps Ethernet, the standard LAN architecture has
become switched 100 Mbps to each desktop. New tech-
nologies such as Gigabit Ethernet (and Gigabit Ethernet
over copper) are causing the demand for bandwidth to
                                                                       THE DEFINITION OF NETWORK
increase at an even more rapid rate.                                         PROCESSORS
Within the WAN, new technologies such as Packet over               In the days of software-based routers and bridges there
SONET and Dense Wave-Division Multiplexing                         was no need for a specialized network processor. A
(DWDM) are rapidly increasing the amount of band-                  physical processor (PHY) decoded the incoming packet
width that can be supported by a single strand of fiber,           from the network and passed data onto the central proc-
and the amount of potential bandwidth that network                 essor, which made traffic forwarding decisions based on
service providers can offer to their customers. Many               instructions provided within complex software code.
network service providers are migrating their backbones            However, in order to provide acceptable performance to
to support individual channel speeds as high as OC-48              handle higher speed technologies such as Fast and Giga-
(2.5 Gbps) or even OC-192 (10 Gbps). Even greater                  bit Ethernet, specialized network processors are needed.
speeds loom on the horizon.                                        These processors are highly specialized integrated cir-
New local loop technologies such as Digital Subscriber             cuits that handle the wire-speed data path and perform
Line (DSL) and cable modems are removing the 56 Kbps               protocol classification and analysis.
barrier for home users, while offering new options for             Network processors sit on the data path between the
business users. To meet these new demands for band-                physical interface processor and the backplane. Typical
width, new companies such as Qwest, Frontier Commu-                functions performed by network processors include:
nications, IXC, Level 3 and Enron are laying vast new
fiber networks based on DWDM that will eventually                  • Segmentation Assembly and Reassembly (SAR) -
provide so much bandwidth that many analysts are fore-               Frames are disassembled, processed, and then reas-
casting a bandwidth “glut” in the not so distant future.             sembled for forwarding.

With bandwidth rapidly becoming a commodity that                   • Protocol Recognition and Classification - Frames are
many consumers are buying based on price, carriers see               identified based on information such as protocol type,
the need to implement advanced features to differentiate             port number, destination URL or other application or
their services. Examples of these types of new carrier               protocol-specific information.
services available now, or soon to be available include:           • Queuing and Access Control - Once frames have been
• Offering multiple quality-of-service levels to provide             identified, they are placed in appropriate queues for
  lower latency and delay to mission-critical traffic,               further processing (e.g., prioritization or traffic shap-
                                                                     ing). Frames are also checked against security access
• Service Level Guarantees of up to 99.999% availabil-               policy rules to see if they should be forwarded or dis-
  ity, and/or                                                        carded.
• Integrated services such as the ability to carry voice,          • Traffic Shaping and Engineering – Some protocols or
  video and data over a single connection.                           applications require that, as traffic is released to the
From the point of view of carriers, they want to be able             outgoing wire or fiber, it is “shaped” to ensure that it
to provide these new services as quickly as possible for             meets required delay or delay variation (jitter) re-
as low of a cost as possible. To provide this support,               quirements. Other requirements specify the priority of
carriers must be able to support new technologies within             traffic between different channels or message types.
their networks such as Multi-Protocol Label Switching              • Quality of Service (QoS) – in addition to appropriately
(MPLS), H.323 voice over IP, and integration with leg-               shaping traffic for QoS, frames may need to be tagged
acy ATM infrastructures. Carriers must also implement                for fast processing subsequent devices within the net-
complex billing and security systems as well as systems              work (e.g. 802.1P or IP TOS).
to support SLA verification and management.
Many carriers are now deploying devices at the customer
edge that are capable of interfacing with a variety of dif-
ferent types of traffic such as IP, ATM, DSL, SONET,
frame relay and analog voice. Carriers have rapidly dis-
covered that the days of deploying a specialized device

Agere, Inc.                                       The Challenge for                                             Page 3
                                          Next Generation Network Processors
                                                 September 10, 1999
                                                                    Performance
 THE BASIC REQUIREMENTS OF A                                        For the last several decades, the development of inte-
     NETWORK PROCESSOR                                              grated circuits has followed "Moore's Law" which states
                                                                    that the number of gates, and hence the processing
From a network equipment manufacturer’s point a view,               power, of an integrated circuit doubles roughly every
the network processor is a key component they can use               eighteen months. With the increasing deployment of
to differentiate their products from those of their com-            high-speed bandwidth technologies such as Gigabit
petitors. By delivering products with advanced network              Ethernet and DWDM, this rate of improvement in speed
processor capabilities, they can offer features and per-            might not be fast enough to support future performance
formance enhancements that make their products supe-                requirements. Therefore, one of the primary require-
rior to those of their competitors. Therefore, hardware             ments for network processors is to be able to rapidly
vendors will actively seek out network processor tech-              scale their performance capabilities to support ever-
nologies that can provide them with this advantage.                 increasing bandwidth requirements: Gigabit Ethernet /
Some of the differentiating factors in various network              OC-12 today, OC-48 in the near future, and OC-192 /
processors include programmability, performance, man-               10-times-Gigabit Ethernet and higher down the road.
agement, and routing, as described below.

Programmability                                                                       Network Demands
The network processor must be easily programmable in                                  Moore’s Law
order to support customization of feature sets and the
rapid integration of new and existing technologies. For
example, a vendor wishing to provide a product that can
classify traffic flows based on Layer 4 information will
demand a network processor that allows them to support
this functionality.
As time-to-market cycles are critical to the success of
any product, programmability tools that speed customi-                  Network speed and bandwidth demands are
                                                                        dramatically out-pacing advancements in silicon
zation of network processor feature sets are essential.
                                                                        processing.
Hardware manufacturers don't want to find themselves in
a situation where they are still debugging or testing proc-         In addition, network processors must evolve to be able to
essors when their competitors have already brought                  track and support thousands of simultaneous connections
competing products to market. In order to meet this de-             in order to support such technologies as MPLS and qual-
mand, network processor manufacturers must strive to                ity of service for the H.323 standard3 for voice over IP.
supply programming and testing tools that are as simple             Support for large numbers of connections is also a re-
as possible to use. These programming tools should be               quirement to support features such as ATM or frame
based on a simple programming language that allows for              relay switched virtual circuits.
reuse of code wherever possible.                                    Network processors must be able to support a variety of
In addition, programming tools must provide extensive               protocols such as ATM, IP, AAL5 and control mecha-
testing capabilities that provide intelligent debugging             nisms such as MPLS. In many cases, network processors
features, such as descriptive codes and definitions, as             must also provide support for legacy protocols such as
well as code-level statistics for optimization. Testing             IPX and SNA.
tools must be able to simulate real-world conditions and            Finally, network processors must be able to support large
provide accurate measurements of throughput and other               bandwidth connections, multiple protocols, and advanced
performance measurements.                                           features without becoming a performance bottleneck.
Programming tools should be based on a graphical user               That is, network processors must be able to provide wire-
interface (GUI) that integrates with current GUIs such as           speed, non-blocking performance regardless of the size
Windows NT or the UNIX-based Common Desktop En-                     of the pipe, the type of protocol or the features that are
vironment (CDE). This working environment should                    enabled.
also provide analysis and simulation tools so manufac-
turers can perform extensive real-world simulation test-            Management
ing.                                                                Network processors must provide support for services
And as with any programmable object, the network proc-              such as SLA management and enforcement (as described
essor must provide an extensive software developer's kit
that contains detailed documentation for all APIs (appli-           3
                                                                      H.323 uses dynamic port mappings for call data, requiring devices to
cation programming interfaces).                                     track these ports in order to apply a quality of service level.

Agere, Inc.                                        The Challenge for                                                     Page 4
                                           Next Generation Network Processors
                                                 September 10, 1999
above). Network processors must be able to gather per-               nation URL information, but also the ability to quickly
formance and traffic-flow statistics that can then be col-           tag these packets for subsequent processing by other
lected by a billing or accounting system using such                  network processors.
common protocols as RMON (Remote Monitoring) and
SNMP (Simple Network Management Protocol).
Network processors also play a key role in enforcing                                  APPROACHES
various classes of service that service providers may of-
                                                                     When designing new products, network hardware manu-
fer. For example, a service provider may provide a
                                                                     facturers may choose among a variety of different tech-
tiered service whereby mission-critical traffic such as e-
                                                                     nologies to handle network processing. These choices
commerce has a guaranteed delay of less than 80 milli-
                                                                     included using ASICs, RISC, augmented RISC, or hy-
seconds, while all other traffic is delivered with a best-
                                                                     brid approaches. Each of these choices is discussed be-
effort guarantee. To enforce this policy, traffic must be
                                                                     low.
identified and classified as it enters the service provider's
network. These tasks are typically performed within the
network processor. Hence, the network processor must                 Application Specific
be able to classify packets into multiple classes of serv-           Integrated Circuit (ASIC)
ice, each with their own quality of service requirements.            The application specific integrated circuit, as its name
It is typical in most networks that this classification oc-          implies, is designed from the start for a very specific
curs at the network boundary, where traffic either leaves            application. This is in contrast to a typical microproces-
or enters the network. Another function that typically               sor that is designed with the flexibility to perform a vari-
occurs at this boundary is traffic filtering using access-           ety of functions.
control lists or some other policy enforcement mecha-                Since an ASIC is designed for a very specific set of
nism. For example, Internet service providers typically              tasks, its design can be optimized to carry out those tasks
block incoming traffic with a source IP address that is              as efficiently as possible. Unlike traditional microproc-
part of the range of private IP addresses specified within           essors, ASICs don't have to be designed around the low-
RFC 1918 (RFC 1918 sets aside a group of IP addresses                est common denominator in order to be able to perform a
that should never be routed on the public Internet). If the          wide variety of tasks. ASICs typically perform the tasks
traffic is coming from the private range of IP addresses,            they are designed to do at performance levels much
it is discarded. Much like the identification and classifi-          greater than a general-purpose microprocessor.
cation process for managing quality of service, this proc-
ess also should ideally take place within the network                However ASICs are not well-suited to situations where a
processor.                                                           variety of tasks must be performed. In the networking
                                                                     world, ASICs are typically used to forward traffic at very
By performing management tasks such as identification,               high rates of speed, but they are usually unable to per-
classification, and accounting within the network proces-            form additional traffic management tasks such as classi-
sor, hardware vendors can take advantage of the special-             fication, access control and/or accounting. In most
ized nature of these processors to provide a large                   current implementations, a separate central processor
performance boost to their products.                                 typically performs those types of tasks.
                                                                     Once an ASIC is designed and manufactured, it is very
Routing
                                                                     difficult to change it. Unlike traditional microprocessor
After identifying, classifying, and accounting for traffic           architectures, ASICs cannot be modified with a simple
flows, network processors must be able to make for-                  software upgrade to the operating system – functions are
warding decisions based on pre-programmed informa-                   embedded into the chip during the design and manufac-
tion. For example, an organization may have a policy                 turing process. Upgrading or adding new features to
that all HTML traffic destined for its e-commerce servers            ASIC-based components typically requires the replace-
should receive the highest priority through the network.             ment of the ASICs themselves. This can lead to longer
As this traffic enters the network, it is identified, classi-        time-to-market cycles for subsequent changes.
fied, and accounted for by the network processor at the
edge of the network.
                                                                     Reduced Instruction
Once the classified traffic moves through the network,               Set Computing (RISC)
other network processors must be able to quickly identify            Microprocessors such as the Intel 286/386/486/Pentium I
the traffic type and recognize that it needs to be for-              series have been based on the Complex Instruction Set
warded ahead of all other traffic such as e-mail or simple           Computing (CISC) model. This approach embeds a
web-surfing. To enforce this policy requires not only                large complex set of instructions within the processor to
network processors that are capable of looking deep                  make the processor extremely versatile to program. Pro-
within a traffic flow to determine application and desti-            grammers can take advantage of the large instruction set
Agere, Inc.                                         The Challenge for                                             Page 5
                                            Next Generation Network Processors
                                                   September 10, 1999
to create complex, custom-tailored applications to fit a           this is by using ASIC and RISC-based processors within
variety of applications. However, due to the complex               the same product. In these types of devices, a central
instructions that must be processed, CISC-based proces-            RISC based processors typically acts as the core proces-
sors are difficult to scale to meet the increased perform-         sor and specific tasks are moved out to ASIC-based line
ance demands that network applications require.                    cards.
The alternative approach to CISC is called "Reduced                An example of this is the Cisco Express Forwarding
Instruction Set Computing" or RISC. RISC processors                model in which the central processor calculates routes
are designed with support for a much simpler and smaller           and downloads a complete copy of this routing informa-
set of instructions that allows them to perform processing         tion into line interface cards. The interface cards then
tasks at speeds much greater than their CISC counter-              use ASICs to switch traffic between themselves at very
parts, while still preserving much of the support for              high rates of speed.
flexible programming that applications require.
                                                                   However this approach runs into the limitations previ-
Compared to ASICs, RISC processors are easily pro-                 ously described for ASIC-based architectures, namely
grammable. A RISC-based network processor follows                  that ASIC-based line cards can't be easily upgraded nor
the traditional software-based model and therefore re-             can they easily support new features.
tains the advantages (high level of programmability and
                                                                   This continues to leave hardware manufacturers in a
flexibility) while also retaining the disadvantages (slower
                                                                   quandary.    The basic requirement continues: "how to
performance, since decisions are made in software) of
                                                                   combine the flexibility of RISC with the performance of
that model.
                                                                   ASICs” within a single platform. Fortunately, Agere has
The performance of RISC processors has been improved               a solution.
over the years by taking advantage of Moore’s law (dou-
bling of transistor density every 18 months). The de-
creased transisitor geometries allow both higher
transisitor counts, and increased clock rates.
                                                                                "WICKED SMART"
Most modern software-based routers use a RISC proc-                Agere’s Functional Processor
essing core (although in some configurations tasks are
                                                                   Agere's functional processor truly combines the flexibil-
off-loaded to ASIC-based line cards). This RISC archi-
                                                                   ity of RISC with the performance of ASIC. The unique
tecture makes these routers capable of supporting a large
                                                                   "Payload Plus" architecture uses a patented technology
variety of protocols and features; however they do not
                                                                   called "Pattern Matching Optimization" to achieve
scale well as additional features are added or additional
                                                                   greater than 5x performance improvement over even
bandwidth requirements are imposed. For example, acti-
                                                                   advanced RISC processors. This performance reaches
vating features such as Access-Control Lists (ACL) or IP
                                                                   the level of fixed function ASICs while allowing the
accounting on a RISC-based router under heavy load can
                                                                   flexibility and programmability of RISC. The Payload
cause the product to quickly reach its maximum proces-
                                                                   Plus architecture is able realize these performance gains
sor utilization level, hurting traffic throughput. For more
                                                                   by using less overhead, fewer clock cycles, and more
details on the architectural limitations of RISC Network
                                                                   data processing per clock cycle than augmented RISC.
Processors, please see the Agere white paper entitled
“Building Next Generation Network Processors.”                     Compared to competitive products based on advanced
                                                                   RISC processors, only Agere's Payload Plus architecture
Parallel Processing                                                is capable of supporting bandwidth speeds of OC-192
                                                                   and beyond while still maintaining the flexibility and
Most current CPUs are based upon the Von Neumann
                                                                   programmability of a traditional RISC processor.
architecture, in which processors process information
serially, one instruction at a time. Research continues            The Agere functional processor is segmented into two
into parallel processing in which processors can perform           components, the “Fast Pattern Processor” and the
multiple instructions simultaneously.                              “Routing Switch Processor.” The Fast Pattern Proces-
                                                                   sor" (FPP) takes data from the PHY chip and performs
For more details on the architectural limitations of par-
                                                                   protocol recognition and classification as well as reas-
allel network processors, please see the Agere white pa-
                                                                   sembly. The FPP can classify traffic based on informa-
per entitled “Building Next Generation Network
                                                                   tion contained at Layers 2 through 7. Based on parallel
Processors”.
                                                                   processing algorithms, the FPP can provide ATM re-
                                                                   assembly and can support table lookups with millions of
Hybrid Approaches                                                  entries and variable entry lengths.
For hardware vendors, the "Holy Grail" is the flexibility
                                                                   From the FPP, traffic moves to the Routing Switch Proc-
of RISC with the performance of ASICs. One approach
                                                                   essor (RSP) which handles queuing, packet modification,
that hardware vendors have tried in order to accomplish
Agere, Inc.                                       The Challenge for                                           Page 6
                                          Next Generation Network Processors
                                                 September 10, 1999
traffic shaping, application of quality of service tagging,         Agere's FPL provides developers with an enormous ad-
and segmentation.                                                   vantage over complex to develop RISC code and allows
                                                                    developers to shorten time-to-market cycles thus reduc-
The FPP and RSP interface with the "Agere System In-
                                                                    ing life-cycle development expenses. Through its func-
terface" (ASI). The ASI is the management component
                                                                    tional approach, FPL provides a high level of reuse of
of the processor and provides support for RMON and
                                                                    code in multiple applications.
tracks state information. The ASI also controls the
movement of data between the FPP and RSP to ensure                  Agere's programming environment also delivers a full
that it moves at wire speed rates.                                  suite of testing and simulation tools that allow develop-
                                                                    ers to fully test applications before deployment. Agere's
                                                                    "Integrated Development Environment" (IDE) provides
               FPP                   RSP                            developers with a complete software developer's kit in-
                                                                    cluding traffic generation tools for real-world simulation
                                                                    and testing.
                         ASI                                        For more information on the advantages of FPL, see the
                                                                    Agere white paper entitled “The Case for a Classification
                                                                    Language.”

                        µP
                                                                                        SUMMARY
                                                                    The demands places on network processors are expected
                                                                    to rapidly scale over the next several years due to de-
       APPLICATION OF AGERE’S                                       mand for bandwidth as well as demands by carriers to
       FUNCTIONAL PROCESSOR                                         provide new services. Current network processor tech-
                                                                    nology is ill equipped to adequately meet these demands.
In a typical system architecture, functions are partitioned         Current ASIC processors aren't flexible enough to sup-
into two types of processors. A general-purpose RISC                port a rapidly changing marketplace, while RISC and
processor can be used to develop and maintain the                   augmented RISC processors will not be able to scale to
Routing Information Base (RIB) – the RISC processor                 support the throughput rates required for complex fea-
calculates routes and handles OSPF, MPLS LDP, or                    tures at speeds of GbE, OC-48, and above, and require
RSVP packets and signaling. These are control functions             complex programming methods. Only Agere's "Wicked
where high processing rates are not required.                       Smart" approach provides network processors that com-
In contrast, the Agere Functional Processor is best ap-             bines the performance of ASICs with the flexibility and
plied to the data “fast path,” and thus helps network               feature support of RISC, exploited by a comprehensive
equipment providers to offer products capable of true               and simple development environment. This unique
wire-speed performance. In a typical system, the RISC               combination will allows network equipment manufactur-
processor will forward RIB information to a Forwarding              ers to quickly bring new products to market that can
Information Base (FIB) located in each of the line cards.           scale to support ever increasing bandwidth demands,
Using Agere high-performance FPP/RSP technology,                    while supporting complex feature sets for Quality of
these line cards are can enforce policies and forward               Service and SLA management.
packets at very high speeds. However, unlike ASICs,                 By exploiting the advantages of Agere's approach, manu-
Agere functional processors are programmable and can                facturers will be able to shorten time-to-market cycles,
flexibly accommodate product changes.                               create new products that scale to meet future perform-
                                                                    ance demands, and quickly add new features as market
Agere’s                                                             conditions warrant. Using Agere's network processors,
Functional Programming Language                                     equipment manufacturers will realize a tremendous com-
                                                                    petitive advantage over competitors using alternate ap-
In order to allow hardware manufacturers to quickly de-
                                                                    proaches.
velop and build solutions based on Agere's functional
processor, Agere provides a rich development environ-
ment called the "Functional Programming Language"
(FPL). This language is a true fourth-generation pro-               For more information, contact Agere at www.agere.com.
gramming language that is designed to be highly intui-
tive. Instructions are coded like a protocol definition
language, with interspersed action statements and the
ability to embed routing table information directly into
the protocol code.
Agere, Inc.                                        The Challenge for                                            Page 7
                                           Next Generation Network Processors
                                                 September 10, 1999

				
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Description: NGN is a "Next Generation Network" or the "New Generation Network" acronym. NGN softswitch core is able to provide voice, video, data and other multimedia integrated services, using open, standard architecture to provide rich next-generation network. Packet-based network to provide telecommunications services; use of multiple broadband QoS guaranteed capacity and transmission technology; its business-related functions independent of their transmission technology. NGN enables the user to free access to different service providers; NGN supports generalized mobility. It is a milestone in telecommunications history, marking the era of next-generation telecommunications networks.