# Lecture 10 More on Flip-flops by tvm12882

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```									                                                                                                              Points Addressed in this Lecture

• Introduction to Moore model and Mealy model state
diagrams
• State diagrams and state tables of flip-flops
• Timing parameters of flip-flops
Lecture 10: More on Flip-flops
Professor Peter Cheung
Department of EEE, Imperial College London

E1.2 Digital Electronics I                  10.1                          Nov 2007   E1.2 Digital Electronics I                 10.2                                             Nov 2007

State Diagrams                                                           State Diagram of RS Flip-Flop
S input        R input
• The circuit must be in
• There are two ways to draw state diagrams:                                              either state 1 or state 2.
– Moore model and Mealy model                                                                                                                       10
00                                            00
– we will look first at the Moore model using the Reset-Set (RS)                                                            01      1/0                        2/1        10
flip-flop as an example                                                                                                                           01

• A Moore model state diagram shows
– a circle for each of the various "states" a circuit can be in                  • In state 1                                                       State          Associated
• "states" refers to the logic levels around the circuit                         –    Q output = 0
Number         Q Output

– labels in the circles to show the state number and the associated                     –    an input of S=1, R=0 causes a transition to state 2
output for that state                                                                 –    any other input leaves the circuit in state 1
– an arrow for each possible transition between states                                  –    (an input of S=R=1 is not allowed for RS flip-flops)
– labels on the arrows to show the required conditions to transit                • In state 2
between states                                                                        – Q output = 1
– an input of S=0, R=1 causes a transition to state 1
– any other input leaves the circuit in state 2

E1.2 Digital Electronics I                  10.3                          Nov 2007   E1.2 Digital Electronics I                 10.4                                             Nov 2007
State Table of RS-Flip-Flop

• A state table is a tabular form of the state diagram                            • Example
– one row for each possible state
Present State               Next state
• Shows the next state which will be entered for all                                                                                       inputs: SR
possible combinations of inputs                                                                                               00         01     11    10
• The ordering of the inputs is same as for Karnaugh map                                                               1        1          1      X     2
2        2          1      X     2

• The circuits is in state 2; the inputs are S=1, R=0. What
is the next state?
– state 2

E1.2 Digital Electronics I                   10.5                      Nov 2007   E1.2 Digital Electronics I                        10.6                     Nov 2007

Assigned State Table of
Boolean Expression from Assigned State Table
RS-Flip-Flop
• Differs from a State Table by showing the associated                            • We continue the example of the RS flip-flop and call the
outputs not the state numbers                                                     "next output" Q+
• Example                                                                         • The assigned state table defines the logical relationship
between the inputs (S and R) and Q+
Present Output               Next output
– a Boolean relationship
inputs: SR
00           01    11     10              • Hence we can re-draw the assigned state table as a
0        0            0      X     1                 Karnaugh map
1        1            0      X     1

Q\SR       00   01          11     10
• The output of the circuits is 1; the inputs are S=1, R=0.
What is the next output?                                                                                         0       0     0          X      1

– 1                                                                                                         1       1     0          X      1

E1.2 Digital Electronics I                   10.7                      Nov 2007   E1.2 Digital Electronics I                        10.8                     Nov 2007
Q\SR          00          01         11         10                         Implementation from Characteristic Equations
0         0            0         X           1
1         1            0         X           1                        • The flip-flop can be implemented using gates
• It is common to re-write using NAND gates only
• The Boolean expression is then obtained by grouping
terms as usual
S
1
+                                                                                                                     &
Q
Q = QR + S

Q + = QS + R                                                              Q + = (QR ). S
&
R                           Q
• Such equations are called characteristic equations                                                               Q + = (QS ) R                        1

Asynchronous RS Flip-flop

E1.2 Digital Electronics I                            10.9                                    Nov 2007   E1.2 Digital Electronics I             10.10                            Nov 2007

JK State Implementation

• Moore Model State Diagram                                                                              • Characteristic Equation
10
11                                                                            Q + = J Q + KQ = J Q. KQ
00                                                              00
01            1/0                                    2/1        10
– when J=1, K=0 then Q+ = Q+Q = 1
01
11                                                     – when J=0, K=1 then Q+ = 0
– when J=1, K=1, then Q+ = Q (toggle)
• Assigned State Table

Present Output                         Next output
– Note that the JK is not normally implemented directly from this
equation
inputs: JK
– A master-slave configuration is used instead
00            01        11         10
0                  0            0         1          1
1                  1            0         0          1
E1.2 Digital Electronics I                            10.11                                   Nov 2007   E1.2 Digital Electronics I             10.12                            Nov 2007
D-type Implementation                                                                       Mealy Model State Diagrams

• Moore Model State Diagram                                                                         •    Similar principles to Moore model but different labelling
•    State circles are labelled only with state numbers
1
0           1/0                               2/1       1
•    Outputs are written next to inputs on the arrows
0                                         •    E.g. JK Flip-flop

Inputs J and K
• Assigned State Table                                         Characteristic Equation                                                                    Output

Present Output Next output                                                                                                                 10/1, 11/1
00/0                                                00/1
+                                                      1                          2       10/1
Q =D                                       01/0
0         1
01/0, 11/0
0                  0         1
1                  0         1
State Number

E1.2 Digital Electronics I                         10.13                                 Nov 2007   E1.2 Digital Electronics I                    10.14                           Nov 2007

Timing Parameters of Flip-flops
• For correct operation of flip-flops                                                             • Hold time of a flip-flop is always less than the
– data inputs must not change either just before or just after                               propagation delay between CLOCK and Q
clock pulses                                                                             • Rising edge of CLOCK causes the data at A to go to B
• If data changes near the clock the flip-flop might                                                and data at B to go to C in example below
enter a metastable state
– neither 0 nor 1
• The amount of time before and after the clock pulse
in which data transitions are not allowed are called:
A       1D            B   1D       C
– setup and hold times
– defined by the manufacturer
C1                C1
CLOCK
CLOCK
DATA

t            t
setup        hold
E1.2 Digital Electronics I                         10.15                                 Nov 2007   E1.2 Digital Electronics I                    10.16                           Nov 2007
• What data does C end up with?
– B doesn't change immediately because of the propagation delay
– The input to the second flip-flop is value of B just before the
CLOCK rising edge i.e. B->C; A->B
• Hence
– This circuit shifts the data one position to the right on each clock
pulse

E1.2 Digital Electronics I           10.17                                Nov 2007

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