Chapter 5 Field-Effect Transistors (FETs) by tvm12882

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									           Chapter 5
Field-Effect Transistors (FETs)




2010-9-27     SJTU   J. Chen      1
                                               2

Content

 Physical operation and current-voltage
  characteristics
 DC analysis
 Biasing in MOS amplifier circuit and basic
  configuration




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     Physical operation and
 current -voltage characteristics




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                                                                            4

Introduction to FET

    FET: Field Effect Transistor
    There are two types
          MOSFET: metal-oxide-semiconductor FET
          JFET: Junction FET
    MOSFET is also called the insulated-gate FET or
     IGFET.
          Quite small
          Simple manufacturing process
          Low power consumption
          Widely used in VLSI circuits(>800 million on a single IC chip)


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Device structure of MOSFET (n-type)

                                  Gate(G)
             Source(S)   Oxide                      Drain(D)
                         (SiO2)
                                            Metal



                   n+        Channel area              n+

                         p-type Semiconductor
                            Substrate (Body)
                                         Body(B)


   For normal operation, it is needed to create a
    conducting channel between Source and Drain

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Creating a channel for current flow
An n channel can be induced at
 the top of the substrate beneath
 the gate by applying a positive
 voltage to the gate
The channel is an inversion
 layer
The value of VGS at which a
 sufficient number of mobile
 electrons accumulate to form a
 conducting channel is called the
 threshold voltage (Vt)


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Device structure of MOSFET (n-type)

                                               L = 0.1 to 3 mm
                                               W = 0.2 to 100 mm
                                               Tox= 2 to 50 nm




             Cross-section view




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Classification of FET

    According to the type of the channel, FETs can
     be classified as
         MOSFET
                            •Enhancement type
               N channel
                            •Depletion type
                            •Enhancement type
               P channel
                            •Depletion type

         JFET
               P channel

               N channel


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Drain current under small voltage vDS
An NMOS transistor with vGS > Vt and with a small vDS
 applied.
    The channel depth is uniform and the device acts as a
     resistance.
The channel conductance is
 proportional to effective voltage,
 or excess gate voltage, (vGS – Vt) .
Drain current is proportional to
 (vGS – Vt) and vDS.



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Drain current under small voltage vDS




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Operation as vDS is increased

 The induced channel acquires a tapered shape.
 Channel resistance increases as vDS is increased.
 Drain current is controlled by both of the two voltages.




                              B


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Channel pinched off

   When VGD = Vt or VGS - VDS = Vt , the channel is
    pinched off
       Inversion layer disappeared at the drain point
       Drain current does not disappeared!




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Drain current under pinch off
• The electrons pass through the pinch off area at very
  high speed so as the current continuity holds, similar to
  the water flow at the Yangtze Gorges



       Pinched-off channel




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Drain current under pinch off
   Drain current is saturated and only controlled by
    the vGS




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Drain current controlled by vGS

 vGS creates thechannel.
 Increasing vGS will increase the conductance of
  the channel.
 At saturation region only the vGS controls the
  drain current.
 At subthreshold region, drain current has the
  exponential relationship with vGS



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p channel device

    Two reasons for readers to be
     familiar with p channel device
      Existence in discrete-circuit.
      More important is the
       utilization of complementary
       MOS or CMOS circuits.




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p channel device

   Structure of p channel device
      The substrate is n type and the inversion layer is p type.

      Carrier is hole.

      Threshold voltage is negative.

      All the voltages and currents are opposite to the ones of n
       channel device.
      Physical operation is similar to that of n channel device.




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Complementary MOS or CMOS




    The PMOS transistor is formed in n well.
    Another arrangement is also possible in which an n-type body is used and
     the n device is formed in a p well.
    CMOS is the most widely used of all the analog and digital IC circuits.


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Current-voltage characteristics

 Circuit symbol
 Output characteristic curves
 Channel length modulation
 Characteristics of p channel device
 Body effect
 Temperature effects and Breakdown Region




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Circuit symbol




   (a) Circuit symbol for the n-channel enhancement-type MOSFET.
   (b) Modified circuit symbol with an arrowhead on the source terminal to
       distinguish it from the drain and to indicate device polarity (i.e., n channel).
   (c) Simplified circuit symbol to be used when the source is connected to the
       body or when the effect of the body on device operation is unimportant.


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Output characteristic curves of NMOS




 (a) An n-channel enhancement-
     type MOSFET with vGS and vDS
     applied and with the normal
     directions of current flow
     indicated.
 (b) The iD–vDS characteristics for a
     device with k’n (W/L) = 1.0
     mA/V2.


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Output characteristic curves of NMOS

    • Three distinct region
              Cutoff region
              Triode region
              Saturation region
    • Characteristic equations
    • Circuit model

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Cutoff region


             • Biased voltage
                      vGS  Vt
             • The transistor is turned off.
                       iD  0
             • Operating in cutoff region as a switch.


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Triode region

   •     Biased voltage
                vGS  Vt
                vDS  vGS  Vt
   •     The channel depth changes from uniform to tapered
         shape.
   •     Drain current is controlled not only by vDS but also
         by vGS
                       W                    1   2
             iD  k n '     (vGS  Vt )vDS  vDS 
                       L                    2         process transcon-
                       W                                ductance parameter
                 kn '     (vGS  Vt )vDS
                       L

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Triode region

   • Assuming that the draint-source voltage is
     sufficiently small, the MOS operates as a linear
     resistance
                     vDS
             rDS                               1
                      iD                                  W
                           vGS VGS                  kn '   (VGS  Vt )
                                                          L
                      1
                                W
                           kn '   VOV
                                L




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Saturation region

    •        Biased voltage
                           vGS  Vt
                           vDS  vGS  Vt
    •        The channel is pinched off.
    •        Drain current is controlled only by vGS
                                  W
                        iD  k n ' ( vGS  Vt ) 2
                              1
                              2
                                  L

    •        Drain current is independent of vDS and behaves as
             an ideal current source.

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Saturation region

  The iD–vGS characteristic for
   an enhancement-type NMOS
   transistor in saturation
  Vt = 1 V, k’n W/L = 1.0
   mA/V2
  Square law of iD–vGS
   characteristic curve.




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Channel length modulation

   • Explanation for channel length modulation
          Pinched point moves to source terminal with the
           voltage vDS increased.
          Effective channel length reduced
          Channel resistance decreased
          Drain current increases with the voltage vDS
           increased.
   • Current drain is modified by the channel
     length modulation
                             W
                 iD  1 k n ' ( vGS  Vt )( 1 vDS )
                      2
                                          2
                                             +
                             L

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Channel length modulation




    The MOSFET parameter VA depends on the process technology and, for a
    given process, is proportional to the channel length L.


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Channel length modulation

    • MOS transistors don’t behave an ideal current
      source due to channel length modulation.
    • The output resistance is finite.
                             1
                   iD                            1     VA
             ro                                     
                   vDS                          I D   ID
                                  vGS  const.



    • The output resistance is inversely proportional to
      the drain current.


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Large-signal equivalent circuit model




     Large-signal equivalent circuit model of the n-channel
     MOSFET in saturation, incorporating the output resistance
     ro. The output resistance models the linear dependence of iD
     on vDS

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Characteristics of p channel device




       (a) Circuit symbol for the p-channel enhancement-type MOSFET.
       (b) Modified symbol with an arrowhead on the source lead.
       (c) Simplified circuit symbol for the case where the source is connected to the
           body.


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Characteristics of p channel device




 The MOSFET with voltages applied and the directions of
  current flow indicated.
 The relative levels of the terminal voltages of the
  enhancement-type PMOS transistor for operation in the triode
  region and in the saturation region.
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Characteristics of p channel device




      Large-signal equivalent circuit model of the p-channel
      MOSFET in saturation, incorporating the output resistance
      ro. The output resistance models the linear dependence of iD
      on vDS

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The body effect

   In discrete circuit usually there is no body effect due
    to the connection between body and source terminal.
   In IC circuit the substrate is connected to the most
    negative power supply for NMOS circuit in order to
    maintain the pn junction reversed biased.
   The body effect---the body voltage can control iD
        Widen the depletion layer
        Reduce the channel depth
        Threshold voltage is increased
        Drain current is reduced
   The body effect can cause the performance
    degradation.

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Temperature effects and breakdown region


    Drain current will decrease when the
     temperature increase.                W
                               iD  2 kn ' ( vGS  Vt ) 2
                                    1

    Breakdown
                                          L

          Avalanche  breakdown
          Punched-through

          Gate oxide breakdown




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MOS管注意事项

 MOS管栅-衬之间的电容很小,只要有少量的
  感应电荷就可产生很高的电压。
 由于RGS(DC)很大,感应电荷难于释放,感应电
  荷所产生的高压会使很薄的绝缘层击穿,造成
  管子损坏。
 因此,在存放、焊接和电路设计时要多加注意,
  应给栅-源之间提供直流通路,避免栅极悬空。



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MOS管注意事项

 MOS器件出厂时通常装在黑色的导电泡沫
  塑料袋中,切勿自行随便拿个塑料袋装。
  可用细铜线把各个引脚连接在一起,或用
  锡纸包装。
 取出的MOS器件不能在塑料板上滑动,应
  用金属盘来盛放待用器件。
 焊接用的电烙铁必须良好接地。
 在焊接前应把电路板的电源线与地线短接,
  待MOS器件焊接完成后再分开。

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MOS管注意事项

  MOS器件各引脚的焊接顺序是漏极、源极、
   栅极。拆机时顺序相反。
  电路板在装机之前,要用接地的线夹子去
   碰一下机器的各接线端子,再把电路板接
   上去。
  MOS场效应晶体管的栅极在允许条件下,
   最好接入保护二极管。在检修电路时应注
   意查证原有的保护二极管是否损坏。


2010-9-27   SJTU   J. Chen
• DC analysis
• Biasing in MOS amplifier circuit and basic
  configuration




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                                                            41

MOSFET amplifier: DC analysis
1.   Assuming device operates in saturation thus iD
     satisfies with iD~vGS equation.
2.   According to biasing method, write voltage loop
     equation.
3.   Combining above two equations and solve these
     equations.
4.   Usually we can get two value of vGS, only the one of
     two has physical meaning.



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DC analysis
5. Checking the      value of vDS
     i.    if vDS≥vGS-Vt, the assuming is correct.
     ii.   if vDS≤vGS-Vt, the assuming is not correct. We shall
           use triode region equation to solve the problem
           again.




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Examples of DC analysis


                    The NMOS transistor is
                    operating in the saturation
                    region due to
Vt  2V                           VGD  Vt




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Examples of DC analysis




      Assuming the MOSFET operate in the saturation region
      Checking the validity of the assumption
      If not to be valid, solve the problem again for triode region

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The MOSFET as an amplifier
    Basic structure of the
  common-source amplifier




 Graph determining the
 transfer characteristic
    of the amplifier

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The MOSFET as an amplifier and as a switch
                                           Transfer characteristic
                                            showing operation as an
                                            amplifier biased at point Q.
                                           Three segments:
                           vo                  XA---the cutoff region
                                Time
                                                segment
                                               AQB---the saturation
                                                region segment
                                               BC---the triode region
                                                segment


                                                 vI
                    vi

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Homework

 April     2, 2008:
      5.2;5.4;5.9;5.10;




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Biasing in MOS amplifier circuits
   Voltage biasing scheme
        Biasing by fixing voltage
         (constant VGS)
        Biasing with feedback
         resistor
   Current-source biasing
    scheme

    Disadvantage of fixing biasing
     Fixing biasing may result in large ID variability due to deviation
       in device performance
     Current becomes temperature dependent
      Unsuitable biasing method

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Biasing in MOS with feedback resistor




      Biasing using a resistance in the source lead can reduce the
       variability in ID
      Coupling of a signal source to the gate using a capacitor CC1

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Biasing in MOS with current-source




Biasing the MOSFET using a       Implementing a constant-current
  constant-current source I        source using a current mirror


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Small-signal operation and models

    The ac       characteristic
            Definition of transconductance
            Definition of output resistance
            Definition of voltage gain
    Small-signal       model
            Hybrid π model
            T model
            Modeling the body effect



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The conceptual circuit

                  Conceptual circuit utilized to study
                   the operation of the MOSFET as a
                   small-signal amplifier.
                  Small signal condition
                     v gs  2(VGS  Vt )




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The small-signal models




Without the channel-length                  With the channel-length
    modulation effect                       modulation the effect by
     iD                       W
                                         including an output resistance
gm                      k n ' VOV
     vGS                      L                   vDS                VA
             vGS VGS                         ro                    
                                                   iD    iD  I D
                                                                       ID
—transconductance


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The small-signal models




   The T model of the MOSFET          An alternative representation
   augmented with the drain-to-              of the T model
   source resistance ro


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Modeling the body effect




        Small-signal equivalent-circuit model of a MOSFET in
        which the source is not connected to the body.



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Single-stage MOS amplifier

            Characteristic parameters
            Three configurations
                Common-source configuration
                Common-drain configuration
                Common-gate configuration




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Definitions




                                             vi
      Input resistance with no load    Ri 
                                   vi        ii        RL  
      Input resistance Rin 
                                   ii
                                          v
      Open-circuit voltage gain     Avo  o
                                             vi   RL  
                           vo
      Voltage gain   Av 
                           vi

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Definitions
                                            io
    Short-circuit current gain       Ais 
                                            ii   RL  0
                          i
    Current gain    Ai  o
                          ii
                                                            io
    Short-circuit transconductance gain           Gm 
                                                            vi    RL  0
                                           v0
  Open-circuit overall voltage gain Gvo 
                                           vsig
                               v                          RL 
  Overall voltage gain  Gv  0
                               vsig
                                vx
    Output resistance Rout 
                                ix   v sig  0




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Relationships

   Voltage divided coefficient
              vi      Rin                       Rin          RL
                                      Gv             Avo
             vsig Rin  Rsig                Rin  Rsig     RL  Ro
                        RL                      Ri
             Av  Avo                  Gvo            Avo
                      RL  Ro                Ri  Rsig
                                                   RL
             Avo  Gm Ro               Gv  Gvo
                                                RL  Rout
   Hence the appropriate configuration should be
    chosen according to the signal source and load
    properties, such as source resistance, load resistance,
    etc
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Basic structure of the circuit



                                     Basic structure of the circuit
                                     used to realize single-stage
                                     discrete-circuit MOS
                                     amplifier configurations.




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The common-source amplifier
The simplest common-source
 amplifier biased with constant-
 current source.
CC1 And CC2 are coupling
 capacitors.
CS is the bypass capacitor.




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Equivalent circuit of the CS amplifier




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Equivalent circuit of the CS amplifier




             Small-signal analysis performed directly on the amplifier circuit
             with the MOSFET model implicitly utilized.
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Characteristics of CS amplifier
   Input resistance              Rin  RG

   Voltage gain                  Av   g m (ro // RD // RL )
                                              RG
   Overall voltage gain Gv                        g m ( RD // RL // ro )
                                           RG  Rsig
   Output resistance             Rout  ro // RD

                Summary of CS amplifier
                    Very high input resistance
                    Moderately high voltage gain
                    Relatively high output resistance
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The CS amplifier with a source resistance




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    Small-signal equivalent circuit with ro neglected
   Voltage gain
              g m ( RD // RL )
    Av  
                1  g m RS
   Overall voltage gain
                RG    g m ( RD // RL )
    Gv  
             RG  Rsig 1  g m RS




                                                             RS takes the effect of
                                                              negative feedback
                                                             Gain is reduction by
                                                              (1+gmRS)
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The Common-Gate amplifier

                                 Biasing with constant
                                  current source I
                                 Input signal vsig is
                                  applied to the source
                                 Output is taken at the
                                  drain
                                 Gate is signal grounded
                                 CC1 and CC2 are coupling
                                  capacitors




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The CG amplifier




                                A small-signal equivalent
                                 circuit
                                T model is used in
                                 preference to the π model
                                Ro is neglecting

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The CG amplifier fed with a current-signal input
    Voltage gain
       Av  g m ( RD // RL )

    Overall voltage gain
            g m ( RD // RL )
       Gv 
             1  g m Rsig




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Summary of CG amplifier

 Noninverting amplifier
 Low input resistance
 Relatively high output resistance
 Current follower
 Superior high-frequency performance




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The common-drain or source-follower amplifier




  Biasing with current source
  Input signal is applied to gate, output signal is taken at the source


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The CD or source-follower amplifier



                              Small-signal equivalent-
                               circuit model
                              T model makes analysis
                               simpler
                              Drain is signal grounded

                                Overall voltage gain
                                             RG        ro // RL
                                     Gv                           1
                                          RG  Rsig r // R  1
                                                     o     L
                                                                gm
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Circuit for determining the output resistance




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Summary of CD or source-follow amplifier

 Very high input resistance
 Voltage gain is less than but close to unity
 Relatively low output resistance
 Voltage buffer amplifier
 Power amplifier




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Summary and comparisons

   The CS amplifier is the best suited for obtaining the
    bulk of gain required in an amplifier.
   Including resistance RS in the source lead of CS
    amplifier provides a number of improvements in its
    performance.
   The low input resistance of CG amplifier makes it useful
    only in specific application. It has excellent high-
    frequency response. It can be used as a current buffer.
   Source follower finds application as a voltage buffer and
    as the output stage in a multistage amplifier.


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The internal capacitance and high-frequency model

    Internal capacitances
        The gate capacitive effect
                Triode region
                Saturation region
                Cutoff region
                Overlap capacitance
        The junction capacitances
                Source-body depletion-layer capacitance
                drain-body depletion-layer capacitance
    High-frequency model

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The gate capacitive effect
   MOSFET operates at triode region
             C gs  C gd  1 WLC ox
                           2

   MOSFET operates at saturation region
             C gs  2 WLCox
                    3
             
             C gd  0
             
   MOSFET operates at cutoff region
             C gs  C gd  0
             
             
             C gb  WLCox
             




 2010-9-27                            SJTU   J. Chen
                                                                     78

Overlap capacitance
    Overlap capacitance results from the fact that the source and
     drain diffusions extend slightly under the gate oxide.
    The expression for overlap capacitance Cov  WL ov Cox
    Typical value Lov  0.05  0.1L
    This additional
     component should be
     added to Cgs and Cgd in
     all preceding formulas




    2010-9-27                 SJTU   J. Chen
                                                 79

The junction capacitances

•   Source-body depletion-layer capacitance
                       C sb 0
             C sb 
                          V
                      1+ SB
                           Vo
•   drain-body depletion-layer capacitance
                       Cdb 0
             Cdb 
                         V
                      1+ DB
                          Vo




 2010-9-27                      SJTU   J. Chen
                                 80

High-frequency model




 2010-9-27      SJTU   J. Chen
                                                                                     81

High-frequency model

                                                    The equivalent circuit for the
                                                    case in which the source is
                                                    connected to the substrate
                                                    (body)




 The equivalent circuit model with
 Cdb neglected (to simplify analysis)




 2010-9-27                         SJTU   J. Chen
                                                82

The MOSFET unity-gain frequency

   Current gain
             Io        gm
                
             I i s (C gs  C gd )

   Unity-gain frequency
                        gm
             fT 
                  2 (C gs  C gd )




 2010-9-27                    SJTU    J. Chen
                                                        83

The depletion-type MOSFET
Physical structure
     The structure of depletion-type MOSFET is
      similar to that of enhancement-type MOSFET with
      one important difference: the depletion-type
      MOSFET has a physically implanted channel
     There is no need to
      induce a channel
     The depletion MOSFET
      can be operated at both
      enhancement mode and
      depletion mode

 2010-9-27              SJTU   J. Chen
                                                                            84
Circuit symbol for the n-channel depletion-MOS




  Circuit symbol for the n-          Simplified circuit symbol applicable
  channel depletion-type             for the case the substrate (B) is
  MOSFET                             connected to the source (S).




 2010-9-27                    SJTU     J. Chen
                                                                               85

Characteristic curves




Expression of characteristic equation
               W
     iD  k n ' ( vGS  Vt ) 2
              1
              2
               L
Drain current with vGS  0
                    W 2                            the iD–vGS characteristic
     I DSS    k n ' Vt
              1
              2
                    L                                    in saturation

 2010-9-27                       SJTU    J. Chen
                                                                            86

The iD–vGS characteristic in saturation




   Sketches of the iD–vGS characteristics for MOSFETs of enhancement and
    depletion types
   The characteristic curves intersect the vGS axis at Vt.


 2010-9-27                          SJTU   J. Chen
                                    87

The output characteristic curves




 2010-9-27         SJTU   J. Chen
                                                                  88

The junction FET
                                  D
                                                  Depletion
                                                  layer




                           N-channel
             G                                                D
                 P+                          P+
                                                         G

                         n-type
                      Semiconductor                           S


                                 S
 2010-9-27                 SJTU        J. Chen
                                                                                  89

Physical operation under vDS=0

          D                      D                                 D

P+                   P+   P+                          P+   P+                P+
G                         G                                G




                 S                      S                              S

      UGS = 0                  UGS < 0                          UGS = UGS(off)
     2010-9-27                   SJTU       J. Chen
                                                     90
The effect of UDS on ID for UGS(off) <UGS < 0




                                                动画
 2010-9-27               SJTU   J. Chen
Summary of semiconductor devices




2010-9-27    SJTU   J. Chen   91
                                                        92




 Diode, BJT and FET are nonlinear devices
  made of semiconductor, mostly silicon
 Diode
     A diode allows current to flow in forward direction
      and hence can perform functions such as
      rectification, demodulation/detection, switch etc.
     The reverse current may become dramatically
      large at breakdown, such phenomena can be used
      as voltage regulator

2010-9-27               SJTU   J. Chen
                                                                     93




   Bipolar Junction Transistor
       A BJT has three terminals: base, emitter and collector
       The collector current is controlled by voltage/ current on
        the base-emitter junction and is almost independent on
        collector voltage.
       It can perform functions such as amplification and switch,
        etc.
       A BJT should be properly biased for normal operation
       There are three basic configurations, each has different
        performance (input/output resistance, gain, high frequency
        response, etc)

2010-9-27                    SJTU   J. Chen
                                                            94




   Field Effect Transistor
     A FET has three terminals: gate, source and drain
     The drain current is controlled by gate voltage and
      is almost independent on drain voltage.
     It can perform functions such as amplification,
      logic calculation and switch, etc.
     A FET should be properly biased for normal
      operation
     There are three basic configurations, each has
      different performance (input/output resistance,
      gain, high frequency response, etc)

2010-9-27               SJTU   J. Chen
                                                    95




 As the microelectronics develops, more and
  more functions are fulfilled by IC chips
 The discrete devices and circuits, however, are
  still very important not only for practical
  applications, but also for better understanding
  and design of LSICs
 Quantitative calculation is sometimes
  complicated but not difficult
 As long as you know the parameter definitions
  clearly, results can be derived KCL, KVL, etc

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                                                96

Homework

 April     6, 2010:
    5.25;5.40;5.47;5.63;               5.116




2010-9-27              SJTU   J. Chen

								
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