TimeCycle Fetch Decode Execute Write back

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Birla Institute of Technology & Science, Pilani
Distance Learning Programmes Division
First Semester 2008-2009
Comprehensive Examination (EC-2 Regular)

Course No.                  : IS ZC351
Course Title                : COMPUTER ORGANIZATION & ARCHITECTURE
Nature of Exam              : Open Book
Weightage                   : 60%                             No. of Pages     =2
Duration                    : 3 Hours                         No. of Questions = 8
Date of Exam                : 28/09/2008 (FN)
Note:
1.    Please follow all the Instructions to Candidates given on the cover page of the answer book.
2.    All parts of a question should be answered consecutively. Each answer should start from a fresh page.
3.    Leave about one inch margin space on all four sides of the answersheet.
4.    Mobile phones and computers of any kind should not be used inside the examination hall.

Q.1      Consider the following sequence of instructions, where the syntax consists of an
opcode followed by the destination register followed by one or two source
registers:

2             AND               R7,    R5, 3
4             SRL               R7,    R0, 8
5             OR                R2,    R4, R7
6             SUB               R5,    R3, R4

Create the table of four-stage pipeline implementation for the execution of the
above instructions for the following:
(a)    Scalar pipeline allows out-of-order execution
(b)    Scalar pipeline but no out-of-order execution
(c)    List all the anti-dependencies in the given instruction set. Rewrite the above
code by using register-renaming technique to eliminate these dependencies.

Assume that all pipeline stages take one cycle except for the execute stage. For
simple integer arithmetic and logical instructions, the execute stage takes one
cycle, but for a LOAD from memory, five cycles are required in the execute stage.

A sample table is given below

Time/Cycle Fetch            Decode Execute Write back
0
1
2
3
---
[5 + 5 + 5 = 15]
IS ZC351 (EC-2 REGULAR)              FIRST SEMESTER 2008-2009                   PAGE 2

Q.2   What are the limitations to designing a super scalar machine to increase instruction
level parallelism? Explain any five in detail.                                  [10]

3.1. What are the two basic approaches used to minimize register memory
operations on RISC machines. Explain briefly.
3.2. What is the disadvantage of write back and write through cache write
policies?
3.3. What points should be considered at first for designing RISC
characteristics.
3.4. Discuss the different characteristics of RISC and compare RISC with CISC.
[4 + 2 + 2 + 4 =12]

Q.4   Consider a three way set associative write through cache with an 8-byte block size,
128 sets, and random replacement. Assume a 32-bit address. What is the size of
the cache (in bytes)? How many total bits are there in the cache (data and tags)?
[2 + 2 = 4]

Q.5   Consider a hypothetical 32-bit microprocessor having 32-bit instructions
composed of two fields. The first byte contains the opcode and the remainder the
immediate operand or an operand address.
5.1. What is the maximum directly addressable memory capacity (in bytes).
5.2. How many bits are needed for the PC, IR, MBR and MAR registers?
5.3. What is the maximum memory address space that the processor can access
directly if it is connected to a 16-bit memory?      [2 + 4 + 2 = 8]

Q.6   Convert   the    IEEE    single-precision    floating   point               number
10000010001100000000000000000000 into a decimal number.                        [4]

Q.7   Express -2-126 in IEEE single-precision floating point format.                  [4]

Q.8   Define the following:
PC, IR, MAR, MBR, Sign and Overflow.                                            [3]

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