# MULTIPLICATION AND DIVISION ALGORITHMS

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```					MULTIPLICATION AND DIVISION
ALGORITHMS

Instructor: Prof. Ten Eyck
Course: Computer Architecture
(CMSC 415)

Presented by:
Manpreet Bhullar
Computer Architecture Project   & Matt Hattersley
Binary Multiplication

147                          10010011   Multiplicand
* 85                       * 01010101   Multiplier
10010011
00000000
10010011
00000000
10010011
00000000
10010011
00000000
12495        011000011001111 Product

Computer Architecture Project
Multiply Algorithm Version 1
Multiplier0 = 1               1. Test      Multiplier0 = 0
Multiplier0

1a. Add multiplicand to product &
place the result in Product register

2. Shift the M’cand register left 1 bit

3. Shift the M’plier register right 1 bit

64th     No: < 64 repetitions
repetition?
Yes: 64 repetitions
Done

Computer Architecture Project
Multiplication Hardware 1

Shift_left
32-bit multiplicand
64 bits

16-bit multiplier Shift_right
32-bit ALU
16 bits
lsb
Write
32-bit product                                  Control
32 bits

Computer Architecture Project
Multiplication Hardware

   Product: initialized to all 0’s
   Control: decides when to shift the Multiplier
and Multiplicand registers and when to write
new values to Product register
   At the end, the multiplier is out of the product
register and the product contains the result

Computer Architecture Project
For Version 1:

Step-by-step transition in the
registers during the multiplication
process 1

Computer Architecture Project

 -instead of shifting multiplicand left, shift product right
 -adder can be shortened to length of the multiplier &
multiplicand(8 bits in our example)
 -place multiplier in right half of the product
register(multiplier will disappear as product is shifted
right
 -add multiplicand to left half of product

Computer Architecture Project
Multiply Algorithm Final
Version
Product = 1                     1. Test     Product = 0
Product00

1a. Add multiplicand to the left half of product &
place the result in the left half of Product register

2. Shift the Product register right 1 bit.

64th     No: < 64 repetitions
repetition?
Yes: 64 repetitions
Done

Computer Architecture Project
For FinalVersion :

Step-by-step transition in the
registers during the multiplication
process (Final)

Computer Architecture Project
Multiplication Hardware(Final)

Shift_left
multiplicand
16 bits

16-bit ALU

Write
product                                      Control Test
32 bits
Shift_right

Computer Architecture Project
Multiply in MIPS
 Can    multiply variable by any constant using MIPS sll and add instructions:
i' = i * 10;   /* assume i: \$s0 */

sll \$t0, \$s0, 3     # i * 23
sll \$t0, \$s0, 1     # i * 21

 MIPS    multiply instructions: mult, multu

 mult  \$t0, \$t1
–   puts 64-bit product in pair of new registers hi, lo; copy to \$n by mfhi,
mflo
–   32-bit integer result in register lo
Computer Architecture Project
Multiplying Signed numbers
Main difficulty arises when signed numbers are involved.
Naive approach: convert both operands to positive numbers,
multiply, then calculate separately the sign of the
product and convert if necessary.

A better approach: Booth’s Algorithm.
Booth’s idea: if during the scan of the multiplier, we observe a
sequence of 1’s, we can replace it first by subtracting the
multiplicand
of the sequence.
after seeing the last 1Computer Architecture Project
For Example:
0110 x 0011 (6x3) This can be done by (8- 2) x3 as well, or (1000 - 0010) x
0011 (using 8 bit words)
At start, product = 00000000, looking at each bit of the multiplier 0110, from
right to left:
0: product unchanged: 00000000 ,
shift multiplicand left: 00110
1: start of a sequence:
subtract multiplicand from product: 00000000 - 00110 = 11111010 ,
shift multiplicand left: 001100
1: middle of sequence, product unchanged: 11111010,
shift multiplicand left: 0011000
0: end of sequence:
add multiplicand to product: 11111010 + 0011000 = 00010010 = 18
shift multiplicand left: 00110000

Computer Architecture Project
Booth’s Algorithm

Scan the multiplier from right to left, observing, at each step,
both the current bit and the previous bit:
1. Depending on (current, previous) bits:
00 : Middle of a string of 0’s: do no arithmetic operation.
10 : Beginning of a string of 1’s: subtract multiplicand.
11 : Middle of a string of 1’s: do no arithmetic operation.
01 : End of a string of 1’s: add multiplicand.
2. Shift multiplicand to the left.
Computer Architecture Project
Integer Division
0001 1001            quotient (25)
(10)   0000 1010 divided into 1111 1010           dividend (250)
-1010
1011
-1010
10
101
1010
-1010
0 remainder

Computer Architecture Project
Start: Place Dividend in Remainder
Division
Algorithm                         1. Subtract the Divisor register from the
Remainder register, and place the result
1                                 in the Remainder register.

Remainder  0                Test           Remainder < 0
Remainder

2a. Shift the           2b. Restore the original value by adding the
Quotient register       Divisor register to the Remainder register, &
to the left setting     place the sum in the Remainder register. Also
the new rightmost       shift the Quotient register to the left, setting
bit to 1.              the new least significant bit to 0.

3. Shift the Divisor register right 1 bit.

n+1                No: < n+1 repetitions
repetition?
Yes: n+1 repetitions (n = 8 here)
Done
Computer Architecture Project
Division Hardware

Shift Right
Divisor

16 bits
Quotient     Shift Left
16-bit ALU
8 bits

Write
Remainder                                    Control
16 bits

Computer Architecture Project
Integer Division

– ALU,   Divisor, and Remainder registers: 16 bit;
– Quotient register: 8 bits;
– 8 bit divisor starts in left ½ of Divisor reg. and it is
shifted right 1 on each step
– Remainder register initialized with dividend

Computer Architecture Project
For Version 1:

Step-by-step transition in registors
during division process1

Computer Architecture Project
Start: Place Dividend in Remainder
Division                      1. Shift the Remainder register left 1 bit
Algorithm
2. Subtract the Divisor register from the
(Final)                   Remainder register, and place the result
in the Remainder register.

Remainder  0             Test                Remainder < 0
Remainder

3b. Restore the original value by adding the
Divisor register to the left half of Remainder register, &
3a. Shift the          place the sum in the left half of Remainder register. Also
Remainder register     shift the Remainder register to the left, setting
to the left setting    the new rightmost bit to 0.
the new rightmost
bit to 1.

n                No: < n repetitions
repetition?
Yes: n repetitions (n = 8 here)
Done. Shift left half of Remainder right 1 bit
Computer Architecture Project
Division Hardware (Final)

Divisor

8 bits

8-bit ALU
Shift Right
Write
Remainder                              Control Test
16 bits                Shift Left

Computer Architecture Project
For Final Version:

Step-by-step transition in registers
during division process (Final)

Computer Architecture Project
Mult/Div Hardware

Divisor/multiplicand

8 bits
alu_control
Carry-          8-bit ALU       Shift_left, shift_right
out of
Write
Top half                                         Control
16 bits                Result/lsb

msb
Computer Architecture Project
Computer Architecture Project

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