Interconnect Programs Challenges Accelerating the Next Technology Revolution Tokyo

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Interconnect Programs Challenges Accelerating the Next Technology Revolution Tokyo Powered By Docstoc
					Interconnect Programs & Challenges

“Accelerating the Next Technology Revolution”
Tokyo March 15, 2006




Sitaram Arkalgud PhD
Director - Interconnect
SEMATECH
Austin, Texas
Contents
 •   Roadmap
 •   Challenge in Interconnect
 •   Low k Development
 •   Cu Metallization
 •   Advanced Interconnects
 •   Summary




                           2
Interconnect Roadmap




         3
SEMATECH Roadmap
(based on ITRS 2005)

 Half Pitch            65          45        32         22         16
 ITRS                 2007       2010       2013       2016       2019
 SEMATECH             2006       2009       2012       2015       2018
 Early dev            2004       2005-      2007-      2010-      2013-
 tools/Materials                 2007       2010       2013       2016

 DRAM                  65          45        32         22         16
 Flash                 57          40        28         20         14
 MPU                   68          45        32         23         16
 • SEMATECH roadmap target is 1 year before ITRS
 • R&D work (i.e. early materials and tool development) would start 4-5
 years ahead of ITRS roadmap.


                                    4
     Interconnect Roadmap
                                        2005      2006      2007       2008     2009       2010     2011      2012      2013      2014       2015     2016      2017      2018
(ITRS 2005 MPU)                                             hp65                           hp45                         hp32                          hp22
Low K Dielectric
Bulk dielectric constant (k)            < 2.7      < 2.7     < 2.4     < 2.4    < 2.2      < 2.2     < 2.2    < 2.0      < 2.0     < 2.0    < 1.8      < 1.8     < 1.8    < 1.6
Effective dielectric constant (Keff)   3.1 - 3.4 3.1 - 3.4 2.7 - 3.0 2.7 - 3.0 2.5 - 2.8 2.5 - 2.8 2.5 - 2.8 2.1 - 2.4 2.1 - 2.4 2.1 - 2.4 1.9 - 2.2 1.9 - 2.2 1.9 - 2.2 1.6 - 1.9




Cu Metallization
M1 wiring pitch (nm)                    180       156       136       118       104         90       80        72        64       56          50       44       40        36
Effective resistivity (μohm-cm)         3.15      3.29      3.47      3.67      3.9        4.08      4.3      4.63      4.83      5.2        5.58     6.01     6.33       6.7




3D
Number of 3D Layers
TSV count                                                            No official, industry wide roadmap exists
Post Bond Misalignment




   Technology                                                      Low k/Cu                                                             3D                               FC
   Transition


                                                                                       5
         Challenges in Interconnect
Cu Metallization:
  Cu Metallization:                                              Low kkdielectric:
                                                                   Low dielectric:
- -Resistivity
    Resistivity                                                  - -kk < 2.2 (2009)
                                                                     bulk < 2.2 (2009)
                                                                      bulk
        - -Scattering effects
            Scattering effects                                   - -Kbulk < 2.0 (2012)
                                                                     Kbulk < 2.0 (2012)
        - -LER
            LER                                                  - -Keff = 2.5 to 2.8 (2009)
                                                                     Keff = 2.5 to 2.8 (2009)
        - -Barrier Thickness
            Barrier Thickness                                    - -Keff = 2.1 to 2.4 (2012)
                                                                     Keff = 2.1 to 2.4 (2012)
        - -CD controll
            CD controll                                          - -Porosity
                                                                     Porosity
- -Barrier step coverage
    Barrier step coverage                                        - -Mechanical properties
                                                                     Mechanical properties
- -Seed layer step coverage
    Seed layer step coverage                                     - -Reliability
                                                                     Reliability
- -Fill characteristics
    Fill characteristics                                         - -Etch, ash, CMP
                                                                     Etch, ash, CMP
- -Ultra fine line reliability
    Ultra fine line reliability                                  - -Pore sealing
                                                                     Pore sealing




                                  Low kkbarriers/caps:
                                    Low barriers/caps:
                                  - -lower kkthan SiN, SiCN
                                      lower than SiN, SiCN
                                  - -Keff = 2.5 to 2.8 (2009)
                                      Keff = 2.5 to 2.8 (2009)
                                  - -Keff = 2.1 to 2.4 (2012)
                                      Keff = 2.1 to 2.4 (2012)
                                  - -Mechanical properties
                                      Mechanical properties
                                  - -Reliability
                                      Reliability
                                  - -Metal pitch
                                      Metal pitch
                                            6
Interconnect at SEMATECH
• Interconnect has a long history of catalyzing industry
adoption of new technologies
    • CMP
    • Cu technology; Cu in IC Fabs, Electroplating
    • Low-k
    • 300mm
• Fully integrated approach and results vetted by
member company consensus

• Evaluate all new technologies based on
   • Performance indicators
   • Cost calculators


                            7
Interconnect Capability
 •   State of the Art 300mm BEOL
 •   Low k Dielectric Etch
     –   TEL sccm & DRM
 •   Low k Dielectric Ash
     –   Mattson eHighland & ICPHT chambers
 •   Spin On Dielectric Track (TEL)
 •   ULK CVD Dielectric Tool
     –   Novellus kbulk=2.3 (and 2.1 in the future)
 •   UV Cure Tool (Novellus)



                                8
Low k Dielectric Development




             9
Areas of Investigation (45 and 32nm nodes)

 •   Porous low k dielectric screening
     –   Electrical and mechanical properties
 •   Unit process development
     –   Etch, ash, CMP, cleans
     –   Pore sealing
 • Lower k dielectric barriers/cap materials
 • Two level metal integration
 • Dielectric reliability
 • Airgap structures


                            10
6 Phases of ISMT Low-k Material Assessment
                         I             II              III                 IV                  V             VI
                      Material     Blanket           1LM                  1LM                 2LM        Reliability
 Phase
                     Properties     Films          Screening            Dvlpmnt             Dvlpmnt          &
                                                                                                         Packaging

                                                                                          Module
                                       J105
                                       J105                                               Module
                                                                                       Integration
     Involvement
      (arb. units)




                                                                                        Integration


                                      Increasing input from             CMP, Etch & Metals


                                                                                                              Gate (V-VI)
                                                                                                              1. M2 etest in spec
                                                                                                              2. 1k via chain yields
                                                       Time                                                   ~100%

                              Gate (II-III)                   Gate (III-IV)
 Gate (I-II)                                                                                   Gate (IV-V)
                              1. 2-LVL stack anneal           1. X-SEMs of completed
 1. κ<2.2
    κ<2.2                                                        1LM Module
                                                                                               1. M1 etest in spec
    (path to 2.0)             2. CMP adhesion test                                             2. Process modules in spec
                              3. Blanket film polish          2. Rev.0 module process
 2. Thermal                                                                                    3. All tools available
                                 rate                            recipe(s)
    stability                                                                                  4. BTS data ok
                              4. Blanket film RGA             3. Adhesion issues
 3. Adhesion                                                                                   5. DD etch verified
                              5. Etched film RGA              4. Moscap data
 4. 300mm (2003)                                                                               6. Multistack adhesion ok
                                                              5. Mechanical strength
                                                                                               7. Integration plan written
                                                              6. Etch & CMP selectivities



                                                                 11
                                                                  7
Materials Evaluation Database-2005
  MSQ based                                                        Etchstop, cap
 and MSQ like           Organic                 CVD systems           and HM
   systems              systems                                        layers
  JSR LKD 5109        Honeywell GX3-P          Trikon Orion 2.2      CVD SiC
  Nanoglass 1.9       Dow P-SiLK Y             Trikon Orion 1.9      CVD SiCN
  CCIC NCS 2.2        Sumitomo Vap 1.9         Trikon Orion 1.9      JSR FF02
  R&H LK2000 v7                                                      JSR AD00
                                               DSI Far
  R&H LK2000 v8                                                      R&H HM 2800
                                               Air Products DEMS
  JSR LKD 5530
                                               Nvls ULK              R&H VL
  JSR LKD 5525
                                               ASM ELK               CCIC MFL

                                                                     Nvls low-k ESL

      Recent Materials                                               ASM low-K ESL


         Material          Type


  Rohm&Haas              Lowk/HM
                                              Program Started
  SolidFirst
  Novellus ULK             Low k              in 1993
  ASM ULK/ELK              Low k
  Air Products DEMS        Low k               ~500 Materials
  CCiC MFL               Lowk/ES
  JSR 5525 / 5530          Low k               Screened
  U Toronto                Low k
  Urbana Champain          Low k
                                               ~10 Integrated
                                         12
Solid First™ ILD Process
 A late porogen removal integration approach removes the porogen post-
 CMP
 Therefore, etch/ash/metallization/CMP processing is on a ‘dense’ non-
 porous film (consisting of a matrix and porogen system)
 Expected advantages of this approach are to provide an integrated porous
 ULK that
  ⇒   Achieves ITRS 45 nm node keff target of < 2.6
  ⇒   Minimizes process-induced dielectric damage
  ⇒   Does not require a pore-sealing liner or densification to block ALD precursor
      penetration
  ⇒   May enable thinner continuous metal barriers
                                                                                                 porogen

CMP stop

  Low-k

CMP stop
                       SiCN                 CMP then
  Low-k                                      UV cure
                       SiC
             SiO2                           @ 400°C                                    SiO2
           Substrate                                                                 Substrate
                        Engbrecht et al., AMC 2005; Collaboration with Rohm & Haas
                                                      13
keff Development Status at SEMATECH
        2LM dual damascene integration of 300 nm pitch comb
        Extracted M2 keff is 2.51 with adjustment for expected M3 ULK level
        (target keff for 45 nm node is 2.5)

                           3.00
        Air                                        Predicted
        SiN                2.75                    Extracted
                                                                     Air
                   kkeff
                    eff




        SiO SiCN           2.50                                            SiCN
                                                                     M3
 keff                                                                              keff
layer   M2                 2.25                                      M2           layer
        M1                                                           M1
        SiC                                                          SiC
        SiO                                                          SiO
                           2.00
        Si                                                           Si
                                    M2 with      M2 modeled
                                  passivation    with M3 ULK


                                         14
      Comparison of Zirkon ILD to Porous-SOD
                  MSQ (k ~ 2.3)
     Integrated Zirkon ILD has comparable M2 BTS to a
     porous-spin-on-dielectric methylsilsesquioxane
     reference (k ~ 2.3)
                                   100%
                                              Zirkon
                                   80%
                  Percent failed



                                              MSQ baseline
                                   60%

                                   40%

                                   20%

                                    0%
                                      0.001   0.01     0.1    1   10   100
                                                     TTF (hrs)

Wafer-level BTS (300°C, N2 ambient, 32 V) results for passivated 300 nm
pitch M2 structure for either Zirkon ILD or porous-MSQ reference baseline.
                                                         15
Summary
   A dual damascene integration using Zirkon ILD
   films achieved a keff of 2.5

   The integration has demonstrated:
       excellent via chain yields
       effective ALD precursor blocking
       low damage processing resulting in low keff
       reliability that is comparable to a porous-MSQ
       reference baseline
   However, the VL2100v1 hardmask correlated to
   lower BTS TTF and is a reliability concern


                            16
   Cleans Modeling                                                                       Wetting Theoretical capillary pressures
                                                                                                                                                                                                     300




                                 dis
                                                                                                                                                                                                     250




                                    so
         we




                                                           dr
          ett




                                    lvi
                                                                                                                                                                                                     200




                                                             yin
           ti


                                                                                                                                              Wetting Challenges Increase
              in




                                        n




                                                               ng
                                         g




                                                                 g
                 g
                 g


                                                                                                                                                                                                     150




                                                                                                                                                                                                            pressure [atm]
                                                                                                                                                                                                     100
                                                                                          required pressure for removal
                                                                                                                                                                                                     50


                                                                                                                                                                                                     0
                                                             Removability of       260    240    220       200    180     160     140         120        100          80      60      40    20   0
       Contact angle             Solubility                  Cleans Chemistry                                                                                                                        -50
                                               Transport
                                                                                          required pressure for insertion                                                  Hole size [nm]
                                               mechanisms
                                                                                                                                                                                                     -100
                                         Damaging
                                                    Viscosity of
Surface        Free surface
                                                    liquid                  Cracking
tension of     energy of solid
liquid                                                       Surface    Thermal                                                   0.00
                                                                                                                                              1.00




                                                                                                                      ter
                                                             tension of properties of




                                                                                                                   me
                                                                        liquid                                                                                                  Solubility




                                                                                                                                                              po
                                                             liquid




                                                                                                                 ar a




                                                                                                                                                                l
                                                                                                                                                                lar
                Material Treatment                                                                                        0.25
                                                                                                                                                         0.75




                                                                                                             np




                                                                                                                                                                      Ha
                                                                                                                                                                         ns
                                                                                                            e
                                                                                                         ns




                                                                                                                                                                            e
                                                                                                                                                                            e
                                                                                                                 0.50




                                                                                                                                                                             n
                                                                                                                                                                             np
                                                                                                       Ha
                                                                                                                                                     8                0.50




                                                                                                                                                                               ar a
      • Obtaining fundamental understanding of the



                                                                                                    i ng




                                                                                                                                                                                ra
                                                                                                                                                         16




                                                                                                                                                                                   me
                                                                                                                                                                                   me
                                                                                                                                                              3



                                                                                                i dg
      cleaning mechanisms – wetting, solubility, and                                                    0.75                      12       19
                                                                                                                                                13
                                                                                                                                                                       9
                                                                                                                                                                  5            0.25




                                                                                                                                                                                      t
                                                                                                                                                                                      te
                                                                                                                          1

                                                                                             br
      drying                                                                                                                                             6




                                                                                                                                                                                       r
                                                                                           H-                                    20                 10
      • Building up database of material, process (ash                                                                                 2
                                                                                                                                                             17   15 7
      and etch chemistries) and solvent interactions                                            1.00                                                4               18 14 110.00
                                                                                                 0.00              0.25                0.50                   0.75       1.00
      • Intent is to provide a predictive model for
                                                                                                                 dispers Hansen parameter
      extendability of wet processing (cleans, plating,
      etc)
                                                                           17
Cu Metallization




       18
Areas of Investigation (45 and 32nm nodes)

 • Extension of PVD barriers
 • Introduction of ALD barriers
     –   Barrier precursor penetration & pore sealing
 •   Direct plating
 •   Cu seed technology
 •   Cu fill technology
 •   Ultra fine line reliability
 •   Patterning ultra fine lines


                            19
Electromigration of Ultra Fine Lines
  99
  98
  95
  90
  80
                                                                                     • Little impact of decreasing
  70
  60                                                                                 linewidth on MTF (180nm to 60nm)
  50
  40
  30
  20                                     0.060 μm, t =8.7hrs, σ=0.190
                                                                                     • Low preclean dependance
                                                    50

  10                                     0.110 μm, t =9.0hrs, σ=0.243

   5
                                                    50

                                         0.185 μm, t =9.2hrs, σ=0.262
                                                    50
                                                                                     • MTF improvement with increased
   2
   1                                                                                 (350C) anneal temperature
       1                            10                                   100
                                 Time (hrs)

  99                                                                                 99
  98        t 50 = 39 hrs                                                            98
  95        σ = 0.691                                    t50 = 38 hrs                95
            (5063001-17)                                                                                Anneal tem p. 350 C
  90                                                     σ = 0.511                   90                 Anneal tem p. 150 C
  80                                                     (5063001-12)
                                                                                     80
  70                                                                                 70
  60                                                                                 60
  50                                                                                 50
  40                                                                                 40
  30                                                                                 30       t50 = 38 hrs
                                                                                                                                t50 = 55 hrs
  20       t50 = 43 hrs                                                              20       σ = 0.511
  10       σ = 0.504                                Barrier 1st, 50/50
                                                                                     10       (5063001-12)                      σ = 0.471
           (5063001-05)                             Barrier 1st, 70/70                                                          (5063001-21)
   5                                                Pre clean 1st, 150                5
   2                                                                                  2
   1                                                                                  1
       1                    10                100                        1000             1                  10                 100            1000
                                 Time (hrs)                                                                        Time (hrs)




                                                                                20
Pore Sealing Metrology
 TEM-EELS scan to monitor pore sealing
 (a) TEM of pore sealed sample (b) EELS of pore sealed sample (c) EELS of unsealed sample
                          Cu       Ta   Low k               Cu      Ta     Low k
                                                                                                                                          Carbon Depletion
      (a)                   (b)                                                                            (c)
            Low-K
      Cu
             1
                 50
        Carbon K
        Copper
        Nitrogen K
        Oxygen K                                                                                       0           10         20          30       40        50
                        0         10   20        30                   40               50         60
        Silicon                             Position (nm)
                                                                                                                               Position (nm)




 Cyclic voltametry to monitor pore sealing
                                                                  Cyclic Voltametry Testing (0.125um/ 0.125um comb
                                                                                      structures)

                                                           0.5

                                                           0.3
                                            Current (nA)




                                                                                                                        No pore sealing
                                                           0.1

                                                           -0.1                                                         SEMATECH pore sealing
                                                                                                                        process
                                                           -0.3

                                                           -0.5
                                                               -0.8             -0.3          0.2            0.7
                                                                                        Voltage



                                                                           21
Patterning Ultra Fine Lines
 •        Critical for determining the impact of linewidths on line
          resistivity, barrier properties, and reliability.
 •        Imprint Technology – first dual damascene structures
          with 60nm line/space on 300mm wafers
                                                      Isolated          Dense
                                  60nm 1:5 L/S              60m Dense
 0.2 µm



                  60nm    50 nm




 •        E beam patterning of 30nm lines
          –  Write time reduced to <
          1 hour. Further reduction to
          ~ 10min possible.
          - Etch development is the
          next step

                                                 22
Advanced Interconnects




          23
                                 keff - ITRS 2005
                          Historical
                    4.5   performance, keff
                                        eff

                     4
                    3.5
      k Effective



                                                          ITRS hp65
                     3
                    2.5                       ITRS hp45

                                                   ITRS hp32
                     2
                    1.5
                     1
                     1990 1995 2000 2005 2010 2015 2020

Dielectric scaling will probably not match ITRS 2005’s predictions
                                              24
Cu Resistivity Trend
                                                           Effective Cu Resistivity vs Node (2005 ITRS)

                                                8.00                   Contributors:
                                                                         High resistivity barriers
                                                7.50
                                                                         Barrier volume effect
                                                7.00                     Grain boundary, surface and
         Effective Resistivity (micro-ohm-cm)




                                                6.50                       interface scattering effects
                                                6.00                   Impact:
                                                5.50
                                                                         Performance
                                                                         Process control (for Design)
                                                5.00
                                                                         Reliability
                                                4.50

                                                4.00                                                       NomCu
                                                3.50                                                       MinCu
                                                                                                           MaxCu
                                                3.00

                                                2.50

                                                2.00
                                                       0   10     20     30     40        50   60    70   80       90

                                                                                Node (nm)




KA Monnig; SEMATECH; SEMATECH-Novellus Workshop on Cu Metallization 2005
                                                                                     25
Materials Solutions to the Interconnect
‘RC’ Problem Are Drawing to a Close
                  Future Connectivity
1. Evolutions Of ‘Conventional Interconnects’
   Cu and Low-k, Airbridges, Stacked and/or 3D-IC

                Future Connectivity

          TOO
2. Different Signal Transmission (Non TEM wires)
   RF on Chip, Guided Terahertz, Optical on Chip, Plasmons




       FUTURISTIC
3. “Non-Classical” or Nano-structured Material
   •   Nanotubes (Ballistic transport, Spintronics)
   •   Self Assembly (Ballistic transport, Spintronics, Reduced
       Patterning Cost)


                              26
Air Gaps: Comparison of refilled CVD Low K and PECVD SiO2 (SiH4/N2O)
                                                        2     4  2

                                                                              RC90 (GGE125/90 x GA2_90/110)

                                                  1.20E-05                                   Pre etch                                                                                Post refill
                                                                                                                                                                                     SiO2              Low K
                                                  1.00E-05

                                                                                                                                                                                     12 nm 12 nm 25 nm




                                        s (sec)
                                                  8.00E-06
             Pre etch                                                                                                                                                                                                       Med




                                  RC delayc
                                                                                                                                                                                                                            UQL




                                         e
                                                  6.00E-06
                                                                                                                                                    Post etch                                                               LQL
                                                  4.00E-06


                                                  2.00E-06
             Post etch
                                                  0.00E+00




                                                                                                                                                                                                       110c


                                                                                                                                                                                                              110c


                                                                                                                                                                                                                     110c
                                                                                                                     110e e t h




                                                                                                                                                                                       110e f t h


                                                                                                                                                                                                       4037


                                                                                                                                                                                                              4037


                                                                                                                                                                                                                     4037
                                                                  4 0 3 7 w3b f


                                                                                  4 0 3 7 w45b f


                                                                                                   4 0 3 7 w67b f




                                                                                                                                     4 0 3 7 w3at


                                                                                                                                                     4 0 3 7 w45at


                                                                                                                                                                     4 0 3 7 w67at
                                                                   110c f e


                                                                                              e


                                                                                                               e




                                                                                                                                      110c f f


                                                                                                                                                                 f


                                                                                                                                                                                 f
            Silox or




                                                                                                                    4 0 3 7 b f ec




                                                                                                                                                                                      4 0 3 7 at ec
            CVD Low K




                                                                                                                                                      110c f


                                                                                                                                                                      110c f
                                                                                   110c f


                                                                                                    110c f
                                                                                                                          R90/110 x C125/90
            Post refill                                                                                                   0 SiCN    12 SiCN 25 SiCN
                                                         No refill                                                         2.40E-06
                                                         SiO2                                                                        3.85E-06
                                                         CVD Low K                                                                   4.36E-06 5.02E-06
• Poorer gap fill with SiO2 has
larger void fraction and lowest
RC delay                                               SiH4/N2O oxide                                                                                                                                 CVD Low K
• Lower k refill material has
better gap, with lower void
fraction and higher RC delay


                                                             27
3D Interconnects
•   Pros
    – Keeps wires short, impact beyond Cu/Low K on parasitics (less
      emphasis on new materials)
    – Permits heterogeneous integration
        •   Memory on Logic
        •   CMOS wi; Analog, MEMS, Optical, RF, Compound Semi
    – Permits smaller footprint
    – Permits power savings
    – Uses conventional Si process technology
    – Eases introduction of future technologies
        •   On chip optical, MEMS, Bio …

•   Cons
    – Some technical challenges (materials, thermal, design, test)
    – Very few “common” approaches/standardization
    – No manufacturing infrastructure



                                     28
3D Approaches
 1. Chip Stack Packaging
       a. Ball Bond
       b. Wire Bonds
       c. Folded Tapes
 2. Die Stacking
       a. ‘Printed Wiring’ on Stack Side
       b. Big Vias
 3. Monolithic 3D
       a. Wafer Based
 3D Integration: Trends and Opportunities- An Overview;
 Simon Thomas, Proceedings of the Advanced
 Metallization Conference 2002, pp 3-13,
                              29
What Aspect of 3D?
Wafer Scale ‘Monolithic Processing’
     Very Similar Tools & Processes to Current SOC
                        Align &
                         Stack


                         Bond


                        Pattern,
                         Etch &
                        Fill Vias

                      Polish/Thin
                         Back

                        Repeat
                       Sequence


                          30
         Performance: 3D vs. Conventional
             4.5
                  Low-k Scaling
                                 4
                                3.5
                  k Effective


                                                                                      1           N
                                 3                                                            2
                                2.5                                                               3 4
                                 2                                                                      56
                                       Historical                                  Potential impact,
                                1.5
                                       performance, keff
                                                     eff                                 3D*
                                 1
                                 1990 1995 2000 2005 2010 2015 2020

                    - *3D RC delay impact converted to an effective dielectric constant;
                    - Assumption: n = 2 in 2008, n = 3 in 2011, n = 4 in 2014, etc.
                    - Assumption: Scaling of Cu lines/low-k ceases in 2005
S. Vitkavage (SEMATECH) – 3D Architectures for Semiconductor Integration and Packaging 2005
                                                                    31
 The Cost of 3D Interconnects
        Chip Stack                   3D Interconnects                     2D SOC
     Lowe r T e ch/ V a lue           Lowe r T e ch/ V a lue
                                                                  H ighe st T e ch/ H igh Cost
           Adde d                           Adde d
  D ie by D ie P roce ssing      D ie or W a fe r P roce ssing    W a fe r Le ve l P roce ssing
                                                                        H e te roge ne ous
 S upports H e te roge ne ous S upports H e te roge ne ous
                                                                      Inte gra tion = E xtra
  Inte gra tion with N o N e w Inte gra tion - R e la tive ly
                                                                      Ma sking Le ve ls, IC
 Inte gra tion or IC P roce ss   Low T e ch Additions
                                                                   P roce sse s, Inte gra tion
                                                                     La rge st Footprint @
      S ma ll Footprint                 S ma ll Footprint
                                                                       H ighe st Cost/ in2
       D e sign R e use         D e sign R e use Optimize d       D e sign must be ‘S hrunk’
                                     N e w S i whe re V a lue
      Ma ture S i R e use                                           N o Ma ture S i R e use
                                              Adde d
       Lowe st T T M                   Ca n be Low T T M              Longe st T T M
      H ighe r powe r                    Lowe r powe r                 Lowe r powe r
       consumption                       consumption                   consumption
    Optimum te ch node               Optimum te ch node            Aggre ssive te ch node
  More       Medium
                          Low cost                              Performance
expensive     Cost
                   Best compromise between performance & cost?
                   A good, generic but flexible cost model is essential
                                               32
Cost Impacts, Opportunities, and Target
Areas for Improvement
•   Die-on-wafer process flows and Cost Resource
    Model results
•   Die based cost calculator
•   Input fields:                             Initial Target Wafer Information
                                                                                           Product Estimation Cost Model
                                                                                                        Initial Donor Wafer Information
                                                    Diameter of target wafer (mm)      200
                                                                                      200                     Diameter of donor wafer (mm)       200
                                                                                                                                               200
         •   Die Size (number of die)                          Cost of target wafer $3,500.00
                                                         Length of target die (mm)      9
                                                                                                                      Cost of donor wafer ($) $4,700.00
                                                                                                                    Length of donor die (mm)      6

         •   Parent Wafer Cost                             Width of target die (mm)
                                                 Percentage of sites with KGD (%)
                                              Number of die possible in target wafer
                                                                                        7
                                                                                        55
                                                                                       244
                                                                                                                     Width of donor die (mm)
                                                                                                           Percentage of sites with KGD (%)
                                                                                                        Number of die possible in donor wafer
                                                                                                                                                  5
                                                                                                                                                 91
                                                                                                                                                 878

         •   Host and Donor wafer yield              Bonded Wafer Information
                                                 Number of thru-hole vias required              4000     Target Die Yield        Donor Die Yield
    –   Output:                                             Via exclusion area (um2)
                                              Additional via die area required (mm2)
                                                                                                 20
                                                                                                0.08
                                                                                                          Medium Volume             High Volume

                                               Number of processing steps required               3
         •   Post yield die cost                Results with Current Die Area                          Results with Optimized Die Area
                                                           Area of target die (mm2)  63.000                         Area of target die (mm2) 46.540

IMPACT: Ability to                              Required length of donor die (mm)
                                                 Required width of donor die (mm)
                                              Number of die possible in donor wafer
                                                                                      6.007
                                                                                      5.007
                                                                                       875
                                                                                                                    Area of donor die (mm2) 46.540
                                                                                                          Approximate yield for each wafer
                                                                                                       Number of die possible in target wafer
                                                                                                                                                64
                                                                                                                                                388

compare 2D SOC vs. 3D                           Number of target die after bonding     219
                                                         Integration cost per wafer $300.00
                                                        Integration cost per device   $1.37
                                                                                                         Number of target die after bonding     349
                                                                                                                  Integration cost per wafer $300.00
                                                                                                                 Integration cost per device   $0.86

costs for a specific die                                           Total wafer cost $8,500.00
                                                              Total cost per device  $22.72
                                                                                                                        Total cost per wafer $8,500.00
                                                                                                                       Total cost per device $23.00


size, wafer level cost,                    Areas shaded in this color are user defined values
                                           Areas shaded in this color are calculated values



and yield
                                      33
Summary




   34
WE ARE THE INTERCONNECT EVALUATION
ENGINE FOR OUR MEMBER COMPANIES

In 2005…..
 Demonstrated Keff of 2.5 for 45nm Node With Minimal
 Low-k Damage
 Integrating CVD Low-k (K~2.3) and UV Cure Films &
 Tools
  Ultra Fine Line (<60nm) Cu Metallization Reliability and
 Extendability Determined
 Demonstrated First Viable Pore Sealing Solution,
 Scalable to <45nm Node
 Developed First Principles Model Based Cleans
 Roadmap Identifying Potential Roadblocks
 3D IC Program started, cost model complete

                            35