Computer Architecture Lecture 4

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					Lecture 4: Computer Architecture


      FAST- National University of
    Computer and Emerging Sciences

     Programming for Engineers (1)
       Computer Organization and
         Architecture (Overview)
                       SHARIQ BASHIR
                        Lecture No. 4
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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

 Octal Number System
 • Octal Number System
   – Base = 8 or ‘o’ or ‘Oct’
   – 8 symbols: { 0, 1, 2, 3, 4, 5, 6, 7}
 • Octal to Decimal
    (an-1an-2…a1a0)8 = (an-1 x 8n-1 + an-2 x 8n-2 + …+ a1 x 81 + a0 x 80 )10
    Example: (127)8 = (1 x 82 + 2 x 81 + 7 x 80 )10 = (64 + 16 + 7)10 = (87)10
 • Decimal to Octal
   Repeated division by 8 (similar in principle to generating binary codes)

     Example: (213)10 = (? )8

             Divide-by -   Quotient   Remainde    Octal digit
                  8                      r
                 213 / 8        26           5    Lower digit = 5   Stop, since quotient = 0
                  26 / 8         3           2   Second digit =2    Hence, (213)10 = (325)8
                   3/8           0           3     Third digit =3
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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

 • Octal to Binary
     – Expand each octal digit to 3 binary bits.
         Example:     (725)8 = (111 | 010 | 101)2




 • Binary to Octal
     – Combine every 3 bits into one octal digit
         Example:     (110 | 010 | 011)2 = (623)8




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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

VON NEUMANN ARCHITECTURE
 • The structure and organization of virtually all
   modern computers are based on a single
   theoretical model of computer design called the
   Von Neumann architecture.
 • The Von Neumann architecture is a model for
   designing and building computers that is based on
   the following three characteristics.
     – Four major subsystems of computer.
     – Stored program concept.
     – Sequential execution.

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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

VON NEUMANN ARCHITECTURE
 1. A computer constructed from four major
    subsystems called memory, input/output, the
    arithmetic/logic unit (ALU), and the control unit.
 2. The stored program concept, in which the
    instructions to be executed by the computer are
    represented as binary values and stored in
    memory.
 3. The sequential execution of instructions. One
    instruction at a time is fetched from memory to
    the control unit, where it is decoded and
    executed.
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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture




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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

 Main Memory
 Memory Contents
 • The bits that make up a computer’s memory, store
   characters, numbers and program instructions in binary
   form.

 Addressing Memory
 • A typical memory contains well over a Megabyte of
   memory.
 • Each Information in memory is assigned a unique number
   (integer) called address.
 • The information is then accessed using it assigned
   address.

 • * A single byte is equal to 8 bits.
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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

 Memory and Cache
 • Information stored and fetched from memory subsystem.
 • Random Access Memory (RAM) maps addresses to memory
   locations.
 • Cache memory keeps values currently in use in faster
   memory to speed access times.
 • RAM (Random Access Memory)
    – Memory made of addressable ―cells‖
    – Current standard cell size is 8 bits (note byte is also 8 bits)
    – All memory cells accessed in equal time
    – Memory address
        • Unsigned binary number N long
        • Address space is then 2N cells
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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture




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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

 Memory and Cache (continued)
 • Parts of the memory subsystem
    – Fetch/store controller
        • Fetch: retrieve a value from memory
        • Store: store a value into memory

    – Memory address register (MAR)
    – Memory data register (MDR)



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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

 Memory and Cache (continued)
 • Fetch operation
    – The address of the desired memory cell is moved into
      the MAR.
    – Fetch/store controller signals a ―fetch,‖ accessing the
      memory cell.
    – The value at the MAR’s location flows into the MDR.

 • Store operation
    – The address of the cell where the value should go is
      placed in the MAR.
    – The new value is placed in the MDR.
    – Fetch/store controller signals a ―store,‖ copying the
      MDR’s value into the desired cell.

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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

 Memory and Cache (continued)

   • Memory register

       – Very fast memory location

       – Given a name, not an address

       – Serves some special purpose

       – Modern computers have dozens or hundreds
         of registers
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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture




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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

 Cache Memory
 • Memory access is much slower than processing time
 • Faster memory is too expensive to use for all
   memory cells
 • Locality principle
    – Once a value is used, it is likely to be used again
 • Small size, fast memory just for values currently in
   use speeds computing time.



  Cache Memory


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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

 Input/Output and Mass Storage
 • Communication with outside world and external data
   storage.
    – Human interfaces: monitor, keyboard, mouse
    – Archival storage: not dependent on constant power
 • External devices vary tremendously from each other.

 • Volatile storage
    – Information disappears when the power is turned off
    – Example: RAM
 • Nonvolatile storage
    – Information does not disappear when the power is turned
      off.
    – Example: mass storage devices such as disks and tapes.

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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

 Input/Output and Mass Storage
 (continued)
 • Direct access storage devices
    – Data stored on a spinning disk
    – Disk divided into concentric rings (sectors)
    – Read/write head moves from one ring to another while
      disk spins
    – Access time depends on:
        • Time to move head to correct sector
        • Time for sector to spin to data location


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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture




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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

 Input/Output and Mass Storage
 (continued)
 • I/O controller
    – Intermediary between central processor and I/O
      devices.
    – Processor sends request and data, then goes on
      with its work.
    – I/O controller interrupts processor when request
      is complete.



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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture




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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

 Machine Language Instructions
 • Can be decoded and executed by control unit.
 • Parts of instructions
    – Operation code (op code)
        • Unique unsigned-integer code assigned to each
          machine language operation.
    – Address field(s)
        • Memory addresses of the values on which operation
          will work.


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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

 Machine Language Instructions
 (continued)
 • Operations of machine language

    – Data transfer
        • Move values to and from memory.

    – Arithmetic/logic
        • Perform some operations that produce numeric values.

    – Compares
        • Compares values of two address unit, and check greater, less
          than, equal or unequal condition.
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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

 The Arithmetic/Logic (ALU) Unit
 • Actual computations are performed
 • Primitive operation circuits
    – Arithmetic (ADD, etc.)
    – Comparison (CE, etc.)
    – Logic (AND, etc.)
 • Multiplexer selects desired output.
 • ALU process
    – Values for operations copied into ALU’s input register locations.
    – All circuits compute results for those inputs.
    – Multiplexer selects the one desired result from all values.
    – Result value copied to desired result register.

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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture




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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

 The Control Unit
 • Manages stored program execution

 • Task
     – Fetch from memory the next instruction to be
       executed

     – Decode it: determine what is to be done

     – Execute it: issue appropriate command to ALU,
       memory, and I/O controllers.

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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

 Control Unit Registers And Circuits
 • Parts of control unit
    – Links to other subsystems, it uses two special
      registers:
        • Program Counter (PC)
             – Stores the memory address of the next
               instruction to be executed
        • Instruction Register (IR)
             – Stores the code for the current instruction.

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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture




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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

  Putting All the Pieces Together—the Von
           Neumann Architecture

   • Subsystems connected by a bus

       – Bus: wires that permit data transfer among
         them

   • Computer repeats fetch-decode-execute cycle
     indefinitely.


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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture




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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture

 The Future: Non-Von Neumann
 Architectures

• Physical limitations on speed of Von Neumann
  computers.

• Non-Von Neumann architectures explored to bypass
  these limitations.

• Parallel computing architectures can provide
  improvements: multiple operations occur at the
  same time.

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       FAST, National University of Computer and Emerging Sciences, Islamabad
Lecture 4: Computer Architecture




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       FAST, National University of Computer and Emerging Sciences, Islamabad

				
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