# Reconfigurable Computing - Type conversions and the standard

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```					Reconfigurable Computing -
Type conversions and the standard libraries

John Morris
Chung-Ang University
The University of Auckland

‘Iolanthe’ at 13 knots on Cockburn Sound, Western Australia
Arithmetic in a programming language
   VHDL is like a general purpose programming language!
   You should be able to write things like
‬   c = a + b; c = a – b;
‬   IF a = b THEN … END IF;
‬   IF a < b THEN … END IF;
‬    and even ..
‬    C = a * b;
‬    D = a / b;
‬   without having to implement adders, subtracters, comparators, … explicitly!
   There is a standard library
‬    std_logic_arith
which defines operators: +, -, ABS, *, <, <=, >, >=, =, /=, SHL, SHR
   So you can write
‬   c = a + b;          cnt = cnt – 1; …
if you get the types right!!
   VHDL is strongly typed, so this can sometimes be painful!!
 The advantage is that, when you do get it to compile, it‟s more likely
to generate a correct circuit!
std_logic_arith
…                       The semicolons should be at the end of each line!
This error brought to you by
;library IEEE
Microsoft and the PowerPoint team!
;use IEEE.std_logic_1164.ALL

The library is a VHDL PACKAGE
PACKAGE std_logic_arith is
(as most are)
;type UNSIGNED is array (NATURAL range <>) of STD_LOGIC     Note that we have three new types here:
;type SIGNED is array (NATURAL range <>) of STD_LOGIC        UNSIGNED, SIGNED and SMALL_INT
;subtype SMALL_INT is INTEGER range 0 to 1

;function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED        … and MANY definitions of “+”!!!
;function "+"(L: SIGNED; R: SIGNED) return SIGNED
;function "+"(L: UNSIGNED; R: SIGNED) return SIGNED          These are necessary because of the
;function "+"(L: SIGNED; R: UNSIGNED) return SIGNED       strong typing – but they allow you to write
;function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED             a variety of expressions!
;function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED
;function "+"(L: SIGNED; R: INTEGER) return SIGNED          U, v, w: unsigned( 0 TO n);
;function "+"(L: INTEGER; R: SIGNED) return SIGNED          s, r, t: signed( 0 TO n);
;function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED   i, j, k: integer;
;function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED
;function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED
;function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED
std_logic_arith
…                       The semicolons should be at the end of each line!
This error brought to you by
;library IEEE
Microsoft and the PowerPoint team!
;use IEEE.std_logic_1164.ALL

The library is a VHDL PACKAGE
PACKAGE std_logic_arith is
(as most are)
;type UNSIGNED is array (NATURAL range <>) of STD_LOGIC   u, v, w: unsigned( 0 TO n);
;type SIGNED is array (NATURAL range <>) of STD_LOGIC     s, r, t: signed( 0 TO n);
;subtype SMALL_INT is INTEGER range 0 to 1                i, j, k: integer;

;function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED      u   <=   v   +   w;
;function "+"(L: SIGNED; R: SIGNED) return SIGNED            s   <=   r   +   t;
;function "+"(L: UNSIGNED; R: SIGNED) return SIGNED          s   <=   u   +   r;
;function "+"(L: SIGNED; R: UNSIGNED) return SIGNED          S   <=   r   +   u;
;function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED       u   <=   v   +   j;
;function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED       u   <=   j   +   v;
;function "+"(L: SIGNED; R: INTEGER) return SIGNED           s   <=   r   +   j;
;function "+"(L: INTEGER; R: SIGNED) return SIGNED
…
;function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED
;function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED
;function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED
;function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED
std_logic_arith
 To get things into the right type, you need to use conversion
functions
 These (+more!) appear in std_logic_arith

function CONV_INTEGER(ARG: UNSIGNED) return INTEGER ;
;function CONV_INTEGER(ARG: SIGNED) return INTEGER
;function CONV_INTEGER(ARG: STD_ULOGIC) return INTEGER

;function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED
;function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED
;function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED
;function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED

;function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED
;function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED
;function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED
;function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED

function function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER ) return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; size: integer ) return std_logic_vector;
General Type Conversion
 When the types are compatible, you can cast a type like this:
 For example, signed and std_logic_vector are essentially the
same,
so this works:

a, b : std_logic_vector;
s: signed;
s <= signed( a );
s <= signed(a) + signed(b);
Typical FPGA Architecture
 Logic blocks embedded in a „sea‟
of connection
resources
 CLB = logic block
IOB = I/O buffer
PSM = programmable
switch matrix
 Interconnections critical
 Transmission gates on paths       Aside:
This is a ‘universal’ problem -
 Flexibility
not restricted to FPGAs!
 Connect any LB to any other
Applies to
but                              • custom VLSI,
 Much slower than              • ASICs,
connections within a logic    • systems,
block                         • parallel processors
 Much slower than long lines   Small transistors
on an ASIC                      high speed
 high density
 long, wide datapaths
Logic Blocks
 Combination of
 And-or array
or
Look-Up-Table (LUT)
 Flip-flops
 Multiplexors
 General aim
 Arbitrary boolean
function of several
variables
 Storage
 All modern FPGAs have
„fast carry logic‟
 High speed lines connecting
LBs directly
 Very fast ripple carry adders
 The simplest and most well known adder

an-1 bn-1   an-2 bn-2               a 1 b1      a 0 b0
FA          FA                     FA          FA
cout cin    cout cin               cout cin    cout cin

sn-1        sn-2                     s1         s0
carry
out
 Time to complete
 n x propagation delay( FA: (a or b)  carry )
 We can do better than this - using one of many known better structures
but
 Small
 Regular
 Fits easily into a 2-D layout!   Very important in packing circuitry   into
fixed 2-D layout of an FPGA!
 Ripple carry adder performance is limited by propagation of carries

an-1bn-1      an-2bn-2                 a 3 b3      a 2 b2      a 1 b1       a 0 b0
FA            FA                      FA          FA          FA           FA
cout cin      cout cin                cout cin    cout cin    cout cin     cout cin
sn-1          sn-2                     s3           s2          s1           s0
carry
out LB                                      LB                       LB

A 2-bit adder fits in a Xilinx CLB          But these signals would need to
(enough logic for 5 inputs and              be carried by the general
routing resources (slow!)
2 outputs)
(In fact, you can’t fit a 2-bit adder with
carry out in a CLB
because there aren’t enough outputs!

The fast carry logic provides special (low R) lines for
carry-in and carry-out fast adder with 2 bits/CLB
‘Fast Carry’ Logic
 Critical delay
 Transmission of carry out from one logic block to the next
 Solution (most modern FPGAs)
 „Fast carry‟ logic
 Special paths between logic blocks used specifically for carry out
 Very fast ripple carry adders!
 Carry select
 Uses ripple carry blocks - so can use fast carry logic
 Should be faster for wide datapaths?
 Uses large amounts of logic and multiple logic blocks
 Hard to make it faster for small adders!
0         a4-7       b4-7

cin      a0-3             b0-3                                              cout7
n-bit

sum04-7
cout3
n-bit
cout7
n-bit
sum0-3
sum14-7
„Standard‟
n-bit ripple carry                         0      1                 0       1
n = any suitable value
Here we build                                  carry
sum4-7
from 4-bit blocks
Carry Select Adder                                            These two blocks
„speculate‟
0       a4-7       b4-7 the value of cout3
on

cin      a0-3        b0-3                               n-bit
cout7

sum04-7
cout3
n-bit
cout7
n-bit
sum0-3
sum14-7
the 4 low order bits                            0      1                    0     1
One assumes it will
be 0
After 4*tpd it will                      the other assumes 1
produce a carry out             sum4-7                  carry
After 4*tpd we will have:
a4-7         b4-7
0        • sum0-3 (final sum bits)
• cout3
cin      a0-3        b0-3                                                  cout
(from low order block) 7
n-bit
• sum04-7
• cout07
(from block assuming 0 cin)
sum0
cout3                 • sum14-7 4-7
n-bit                                   • cout17
Ripple Carry Adder                    1          (from block assuming 1 cin)
b 4-7

cout7
n-bit
sum0-3
sum14-7
the 4 low order bits                            0     1                     0        1

After 4*tpd it will
produce a carry out             sum4-7                      carry
0       a4-7       b4-7

cin      a0-3        b0-3                         n-bit
cout 7
Cout3 selects correct
sum4-7 and carry out
sum04-7
cout3
n-bit
cout7
n-bit
sum0-3
sum14-7
0      1                  0       1

All 8 bits + carry are available
after
4*tpd(FA) + tpd(multiplexor)                 sum4-7                    carry
 This scheme can be generalized to any number of bits
 Select a suitable block size (eg 4, 8)
 Replicate all blocks except the first
 One with cin = 0
 One with cin = 1
 Use final cout from preceding block to select correct set of outputs for
current block

```
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