# Voltage Transfer Characteristic for TTL

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```					                 Voltage Transfer Characteristic for TTL
VCC = 5 V
*    Summary of transfer characteristic
   When the input is low,
R3 =
0.13 K                 The current iR goes out the E of Q1
iR
 So Q2 and Q3 get no base current and are off
 So the output is high
   When the input increases,
 Some of iR gets directed into the B of Q2, so
+                                                                             Q2 gets some base current and comes on in
v_
i
active mode
 C current of Q2 increases, so IR drop across R1
increases and output voltage drops (B to C)
 As Q2 comes on, it provides base current to
Q3 and Q3 come on in active mode (C).
Q1 in saturation, Q2 and Q3 off                        When the input increases further,
vo                     Q2 comes on                                      More of iR gets directed into the C of Q1, so
A B                    Q3 comes on,                              Q2 gets more base current and moves into the
VOH =3.7 V                II           Q2 heads towards saturation               saturation mode (C to D)
I             C III
2.7 V                                Q3 reaches saturation,              Q2 provides more base current to Q3 and then
Q2 already in saturation             Q3 moves into saturation mode (D).
Q1 comes out of saturation
D                                         Further increases in the input direct all of iR into
VOL=                                         IV         E
the C of Q1, so Q2 gets even more base current and
0.1 V
0  0.5V 1.2V 1.4V                        3.7 V                   moves deeper into the saturation mode (D to E).
vi              Similarly, Q3 moves deeper into saturation.
VIL      VIH
ECE 352 Winter 2007                                         Bipolar Digital Pt. 4                                1
Voltage Transfer Characteristic for TTL
VCC = 5 V
*    Noise Margins
   Noise Margin for low state NML = VIL -VOL
iR                                                       VOL = low output voltage for typical high
input voltage = 0.1 V
 VIL= maximum input voltage recognized
as a low input = 0.5 V
+                                                                             NML = VIL-VOL =0.5 V - 0.1 V = 0.4 V
v_
i                                                          vo
   Noise Margin for high state NMH = VOH -VIH
 VOH = high output voltage for typical low
input voltage = 3.7 V
 VIH= minimum input voltage recognized
as a high input = 1.4 V
vo
A       B                                                        NMH = VOH -VIH = 3.7 V - 1.4V = 2.3 V
VOH =3.7 V                   II
I             C III
2.7 V                                   IV                            Noise margins are very unequal for this
technology.
NML                  D         NMH    E
VOL=
0.1 V
0  0.5V 1.2V 1.4V                        3.7 V   vi
VIL      VIH
ECE 352 Winter 2007                                         Bipolar Digital Pt. 4                           2
Comparison of Simplified TTL and TTL
VCC = 5V         VCC = 5V
RC =
1.6K
R=4K
+
vo

*    Noise Margin (Low state)
*    Noise Margin (Low state)
 NML = VOL - VIL = 0.6V - 0.1 V = 0.5 V
 NML = VOL - VIL = 0.5V - 0.1 V = 0.4 V
*    Noise Margin (High state)
*    Noise Margin (High state)
 NMH = VOH - VIH = 5 V - 0.7 V = 4.3 V
 NMH = VOH - VIH = 3.7 V – 1.4 V = 2.3 V

vo                                                                  vo
A B
A       B                                                     3.7 V         II
VCC = 5V                                                                            I         C III   IV
I       II III                                            2.7 V

NMH                                                   NML           D    NMH
0.2V         NML C              D                               VOL=                                     E
0.1V                                                            0.1 V
vi                               0 0.5V 1.2V 1.4V             3.7 V    vi
0.6 V 0.7V            5V                                      VOL= V       VIH
IL
ECE 352 Winter 2007                         Bipolar Digital Pt. 4    0.1 V                                3
Voltage Transfer Characteristic for TTL
VCC = 5 V                         *    What is the function of Q4?
 Q4 is weakly on but producing little current
when the output is low.
iR
 This helps to minimize power
dissipation since Q3 is on and in
saturation so ready to conduct current.
 Q4 is weakly on when the output is high.
+
v_
i                                                         vo                  This is because the following gate has
a reverse biased E junction for Q1 and
so draws almost no current.
 The reason Q4 is included in the circuit is to
provide a large current to ensure a fast
transition time when the output is going
vo                                                                    from low to high so tPLH is small.
A       B                                                    At all other times we want Q4 off (or only
VOH =3.7 V                   II                                               weakly on) to minimize power dissipation.
I             C III
2.7 V                                                                A simple resistor in place of Q4 gives a
very long rise time ~ 100’s nsec, as we saw
D                                       for the RTL inverter, so the use of Q4 and
VOL=                                            IV    E
the diode D is an improvement.
0.1 V
0  0.5V 1.2V 1.4V                       3.7 V    vi
VIL      VIH
ECE 352 Winter 2007                                         Bipolar Digital Pt. 4                           4
Transistor - Transistor Logic (TTL)
Fan – Out Capability
*  What is the ability (fan-out) of the TTL
VCC = 5 V       logic to drive simultaneously a number of
subsequent inverters?
R3 =                    iRi * Fan-out = NMax = maximum number of
0.13 K                  = 1 mA subsequent inverters that can be
simultaneously driven (connected to the
output).
p       * For the output high, i.e. vo = 3.7 V, the
n               output is connected to a reverse biased E
iC3                                      junction for Q1 for each subsequent
iE1 =1 mA
+                                  inverter, so current load is very small.
+
_ VCE3             +
vo           * However, for output low, i.e. vo = 0.1 V
_                  E junction of each Q1 forward biased, so
sat                                       VCC  VBE1  VCE 3, sat 5V  0.7V  0.1V
iE1                                             1.0 mA
R                     4K
Recall, we found when the output was low                                     So this adds to the collector current of Q3
iB 3  2.4 mA                                                           so iC3 = N iE1 = N (1.0 mA)
For   10, then the maximum for iC 3 is                               Fan-out limit = maximum value of N
iC 3Max   iB 3  10(2.4 mA)  24 mA                                  In saturation, iC3 < β iB3
   In active, iC3 = β iB3
i        24mA
N max    C 3Max         24       Fan-out limt                      So limit is when Q3 comes out of saturation
i E1   1.0mA
into active mode and iC3 = β iB3.
ECE 352 Winter 2007                                   Bipolar Digital Pt. 4                                                 5
TTL Propagation Delay
Output going high
vo
iC4
iB4                                     VOH=
iR                                               3.7V
Goes
on                                 1.9V
iE4               iCap
Goes
Goes                     off                  +
low                                     Goes vo        C          VCE,sat
high                      = 0.1 V
Goes                                        tPLH       t
off

*   Output going high
 Input goes low
 Transistors Q2 and Q3 turn off (cutoff) due to low input to gate.
 Large charging current flows through Q4 to charge up C.
 Q4 called pull-up transistor
 Charging time is small ~ 1 nsec
 tPLH is the time it takes the output to rise from
VOL = VCE,sat = 0.1 V to 1/2(VOH + VOL) = ½(3.7+0.1) V = 1.9 V
ECE 352 Winter 2007                    Bipolar Digital Pt. 4                    6
TTL Propagation Delay
Output going high

vo                           *   Charging current for capacitor is emitter
iC4                                                  current of Q4.
iB4                                                               At outset, vo= VCE,sat = 0.1 V,
VOH=
3.7V                                 so iB4 and VCE4 are initially large
1.9V                                   5V  1.6 K iB 4  VBE 4  VD  v0
iE4                                                              5V  0.7V  0.7V  vo 3.6V  0.1V 3.5V
iCap       VOH=                               iB 4                                            2.1 mA
0.1V                                                1.6 K            1.6 K     1.6 K
t                  Charging current iCap ≈ iE4 is large
vo             C           tPLH                              since for  = 10
iCap  iE 4  (   1)iB 4  11(2.1 mA )  23 mA
iC4
      As vo rises, iB4 decreases, so iE4 = iCap
Goes                       decreases, but Q4 stays in active mode.
high                      At vo = 1.9V
R                                           5V  1.6 K iB 4  VBE 4  VD  v0

S                                                                   5V  0.7V  0.7V  1.9V 1.7V
iB 4                                   1.1 mA
1.6 K           1.6 K
  So iE4 = iC has decreased to
iC  iE 4  (   1)iB 4  11(1.1 mA )  12 mA
P                               So capacitor charging current is not
vCE4
constant and calculation of tPLH is
more difficult.
ECE 352 Winter 2007                               Bipolar Digital Pt. 4                                              7
TTL Propagation Delay
Output going high
vo                          *      Approximating the charging current for
iC4                                                 capacitor as a constant (average value),
iB4
VOH=
3.7V                                        iCap  iE 4  (12 mA  23 mA ) / 2  18 mA

*      We can calculate the propagation delay
iE4                                                 tPLH using
iCap       VOH=
0.2V
dvo
t          iCap  C        iE 4
vo          C          tPLH                                 dt
Assuming a constant charging current, then

vo t   VOL  E 4 t  0.1V  E 4 t
i              i
iC4
C              C
Goes              t PLH  time for output to rise from VOL  0.1V to vo  1.9V
high                               iE 4
1.9V  0.1V          t PLH
C
R                                          1.9V  0.1V       1.8V
t PLH    C
                C

S                                                              iE 4           iE 4
So Q4 provides a large
charging current to reduce the
rise time for the output going
For C  10 pF we          get           high.

P                                                      1.8V          1.8V
vCE4                    t PLH  C          10 pF       1.0 n sec
iE 4         18mA
ECE 352 Winter 2007                           Bipolar Digital Pt. 4                                                     8
TTL Propagation Delay
Output going low

vo
iR1
iR                                                   VOH = 3.7V

Goes
iB2                off
Goes                   iCap                    1.9V
on
Goes                            iB3    iC3         +
Goes vo                        VCE,sat
C
high                                         low                            = 0.1 V
Goes                                            tPHL       t
on
*    Output going low
 Input goes high
 Transistors Q2 and Q3 turn on (first in active then saturation)
as iR is redirected from the input into the base of Q2
 Q4 is turned off as VB4 = VCC – iR1 R1 decreases since iR1≈ iC2.
 Large discharge current flows through Q3
 Q3 called pull-down transistor
 Discharge time is small ~ 1 nsec
 tPHL is time it takes the output to fall from VOH = 3.7 V to
1/2(VOH + VOL) = ½(3.7+0.1) V = 1.9 V
ECE 352 Winter 2007                     Bipolar Digital Pt. 4                         9
TTL Propagation Delay
Output going low
VCC=5V
vo
iR
VOH = 3.7V
off
iB2              iE4=0                  1.9V
iCap
on                  +          VCE,sat
Goes                                                                                                            t
iC3        vo        = 0.1 V    tPHL
high
on                                      dvo
iCap  C   iC
iB3                                             dt
Assuming a constant discharge current, then

vo t   VOH 
iC           i
iC3                                                                             t  3.7V  C t
C             C
t PHL    time for output to fall from VOH  3.7V to vo  1.9V
iC
1.9V  3.7V         t PHL
C
 3.7V  1.9V         1.8V
t PHL  C 
                  C

     iC               iC
S             R                    What current to use for the transistor?
iB 3  2.4 mA for Q3 intially in active and   10,
iC 3  iB 3  10(2.4 mA)  24 mA
P                                  so for C  10 pF we get
vCE3
1.8V       1.8V
ECE 352 Winter 2007                      Bipolar Digital Pt. 4 t PHL  C      10 pF       0.75 n sec 10
iC        24mA
Power Dissipation for Transistor - Transistor Logic (TTL)
*For input high and output low.
VCC = 5 V  Q2 and Q3 are in SATURATION.
VBC1  VBE 2  VBE3  0.8 V
iR1
VB1  3(0.8 V )  2.4 V and
iC4=0    R3 =
iR                    0.13 K                                   VCC  VB1 5 V  2.4 V
iR                           0.65 mA
R1         4K

   Since Q2 is in saturation mode,
VB1 VC2                                                  iC2 < β iB2 but VCE2 = 0.2 V and
io         p
n
+                       sat                                     VC 2  VBE3  VCE 2  0.8 V  0.2 V  1.0 V
vi =
low
3.7V
_                                                                      VCC  VC 2 5 V  1 V
iR1                      2.5 mA
sat                                      R1         1.6K
   Q4 is weakly on, iC4 ≈ 0.
   Power dissipation
PL  VCC (iR  iR1 )
 5V (0.65mA  2.5mA)
 15.8mW
ECE 352 Winter 2007                    Bipolar Digital Pt. 4                                       11
Power Dissipation for Transistor - Transistor Logic (TTL)
*      For input low and output high.
 Q2 and Q3 are off, iC2 ≈ 0, iC3 ≈ 0.
VCC = 5 V
 Q4 is weakly on, iC4 ≈ 0.
iR1=0         iC4=0                                      iR1 ≈ 0.
R3 =                              Q1 is on so VBE1 = 0.7 V
iR                          0.13 K
VB1  VBE1  VCE , sat  0.2V  0.7 V  0.9 V
VCC  VB1 5 V  0.9 V
iR                          1.0 mA
VB1                                                                          R1         4K
io ≈ 0       p
n
+                            off                                                 Power dissipation
Low =0.2V                                                  high
_                                                                             PH  VCC (iR )  5V (1.0mA )  5.0mW
off                                Average Power Dissipation

P  1/ 2( PL  PH )  1/ 2(15 .8  5)  10 .4mW
    Power Delay Product

(1.0  0.75n sec)
DP  PtP  (10.4mW )                        9 pJ
2

ECE 352 Winter 2007                             Bipolar Digital Pt. 4                                          12
TTL vs. Simplified TTL

vo
vi                                vo
vi

*    Logic levels and noise margins
*   Logic levels and noise margins                                        Noise Margin for Low State
    Noise Margin for Low State                                           NML = VIL – VO = 0.6 V - 0.1 V = 0.5V
 NML = VIL – VO = 0.5 V - 0.1 V = 0.4 V                     Noise Margin for High State
    Noise Margin for High State                                          NMH = VOH - VIH = 5 V - 0.7 V = 4.3 V
 NMH = VOH - VIH = 3.7 V – 1.4 V = 2.3 V                    Unequal noise margins for high and low states.
    Unequal noise margins for high and low states.
*    Propagation delays
*   Propagation delays                                                   Output going low                t PHL  0.55 n sec
   Output going low     t PHL  0.75 n sec                         Output going high               t PLH  16 n sec
   Output going high        t PLH  1 n sec                                                            t P  8.3 n sec
   Propagation delay
   Propagation delay       t P  0.9 n sec

*   Power – Delay Product                                       *    Power – Delay Product
DP  t P P  0.9 n sec10 .4mW   9 pJ                             DP  t P P  8.3 n sec12 .3mW   102 pJ

ECE 352 Winter 2007                              Bipolar Digital Pt. 4                                                   13
TTL Summary
 Fast switching times, ~ 1 nsec.
 Low power-delay product (~ 10 pJ)
 Good fan-out capability

 Static power dissipation, higher
than CMOS
 Complexity – four transistors
 Time delay due to saturating
transistors.
 Small noise margin for low state,
e.g. 0.4 V.

ECE 352 Winter 2007     Bipolar Digital Pt. 4                        14
Comparison of Digital Logic Families

vo

vi

*    J. Millman and A. Grabel, Microelectronics, McGraw Hill, p. 261 (1987).
ECE 352 Winter 2007                 Bipolar Digital Pt. 4                         15
TTL Gates

ECE 352 Winter 2007    Bipolar Digital Pt. 4   16
Schottky TTL Gates

*   Schottky diode clamp prevents
transistors from going deep into
saturation.
*   Reduces transistor switching time.
*   Reduces propagation delay, e.g. from
~ few nsec to < 1 nsec.
*   Power-delay product is not reduced
due to lower resistances used.
*   Low power version of Schottky TTL
has DP ~ 4 pJ.

ECE 352 Winter 2007                    Bipolar Digital Pt. 4   17
Comparison of Digital Logic Families

Power delay product
= a constant

ECE 352 Winter 2007        Bipolar Digital Pt. 4                 18
Comparison of Digital Logic Families

ECE 352 Winter 2007        Bipolar Digital Pt. 4    19
Emitter-Coupled Logic (ECL)

*   Sub nsec propagation delay
(fastest of bipolar technologies).
*   40 mW/gate power dissipation
(high).
*   Power delay product = 30 pJ.
*   Noise margins nearly equal, ~ 0.15 V
*   High fan-out capability.

ECE 352 Winter 2007         Bipolar Digital Pt. 4                                 20
BiCMOS

Basic Inverter        Advanced Inverter                     Two input NAND Gate

ECE 352 Winter 2007                 Bipolar Digital Pt. 4                     21
Comparison of Digital Logic Families

ECE 352 Winter 2007        Bipolar Digital Pt. 4    22

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