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Radio Frequency Digital-to-Analog Converter

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					Oversampled Pipeline A/D Converters with Mismatch Shaping

Personnel: Ayman Shabra (Hae-Seung Lee)
Sponsors: Center for Integrated Circuits & Systems (CICS)
Keyword: ic

In recent years, delta-sigma modulators and pipeline converters have been considered as
possible realizations of analog-to-digital converters for wide-band signals. In comparing
these converters, we recognize a few important attributes. Due to the wide bandwidth of
the input signal and limited circuit speed, delta-sigma converters afford only low
oversampling ratios, which makes high-resolution conversion extremely difficult. The
low oversampling ratio generally nullifies the primary advantage of delta-sigma
 converters; the tolerance to component mismatches. In this regard, remaining potential
advantages of delta-sigma converters over pipeline converters now only include ease of
anti-alias filtering and low quantization noise. It must be noted that the ease of anti-
aliasing is not inherent to delta-sigma modulation. Rather, it is associated with
 oversampling. Therefore, pipeline converters can experience the same benefit of easy
anti-aliasing by simply operating the converter at higher sampling rate than the Nyquist
rate, i.e., oversampling. As for quantization noise in pipeline converters, the quantization
noise can be made smaller by adding more stages at the end of the pipeline. Since the
 last stages of the pipeline do not contribute much thermal noise, they can be made
extremely small and low power. Therefore, the quantization noise itself can be made
arbitrarily small with negligible increase of area and power. Certainly, doing so will not
improve the accuracy or thermal noise. However, it is no different in delta-sigma
converters with low oversampling ratio.

Based on the above observation, we can conclude that delta-sigma converters do not
possess any fundamental advantage over pipeline converters for wide-band applications
that necessitate low oversampling ratios. At this low oversampling ratio many delta-
sigma converters are incapable of providing good enough performance. While there are a
few examples of delta sigma converters with a low oversampling ratio[1,2], we believe
that a more efficient approach would be to oversample a standard pipeline converter,
 and shape the distortion due to mismatch out of the signal band, where it will be
removed by a subsequent digital filter[3]. Since no attempt is made to shape the
quantization noise, there are none of the concerns associated with delta-sigma converters
with a low oversampling ratio.

A test chip was fabricated in a 0.35um CMOS process to demonstrate a number of
mismatch shaping concepts. A 77dB SFDR and 67dB SNDR is achieved at an
 oversampling ratio of 4 and a sampling rate of 60Msample/s. Mismatch shaping
improves the converter SFDR by 12dB's and SFDR by 5dB's.


[1] T. L. Brooks, D. W. Robertson, D. F. Kelly, A .Del Muro, and S. W. Harston, "A 16b SD Pipeline ADC with 2.5
MHz output Data-Rate," Digest of Technical Papers, 1997 ISSCC, pp. 208-209, San Francisco, Feb. 1997.
[2] E. T. King, A. Eshraghi, I. Galton and T. Fiez, "A Nyquist-Rate Delta-Sigma A/D Converter," IEEE Journal of
Solid-State Circuits, vol. 33, no. 1, January, 1998.
[3] A. Shabra, H.-S. Lee. L. Hernandez, "Oversampled pipeline A/D Converters with Mismatch Shaping," Electronic
Letters, vol. 34, no. 6, 19 March 1998, p508-9.
Mixed-Signal Design in Deeply Scaled CMOS Technology


Low Power Reconfigurable Analog-to-Digital Converter

Personnel: Kush Gulati (Hae-Seung Lee)
Sponsors: Center for Integrated Circuits & Systems(CICS)
keyword: ic


There are applications which require Analog to Digital Converters (ADC) that can
digitize signals at a wide range of bandwidth at varying resolution with adaptive power
consumption. Clearly, a conventional ADC with fixed topology and parameters cannot
accomplish this task efficiently. An alternate approach is to employ an array of ADCs,
each customized to work at narrow ranges of resolution and input bandwidth – such a
system would occupy a prohibitively large area to achieve optimal power consumption at
fine granularity over bandwidth and resolution. A single ADC with reconfigurable
parameters and reconfigurable topology would be able to achieve the above goal. Prior
reconfigurable ADCs, however, achieve very limited reconfigurability. The proposed
ADC is designed to provide a significantly larger reconfigurability space. Its target
resolution ranges from 6 to 16 bits and signal bandwidth from 0 to10MHz.
The concept of this ADC stems from the observation that certain ADC architectures such
as the pipeline, cyclic and sigma-delta ADC topologies are composed of the same basic
components such as opamps, comparators, switches and capacitors. The sole difference
between them, from a network perspective, is the interconnection between these devices.
Thus, a converter composed of these basic building blocks in conjunction with a
configurable switch matrix, can be made to construct these different topologies and work
at different resolutions and bandwidths.
The reconfigurable ADC consists of several basic building blocks as shown in Figure 1.
A user defined 'resolution word' that determines the resolution of the ADC is supplied to
the main reconfiguration logic that then determines the global structure of the ADC and
the state of each block. The PLL shown in the figure uses the frequency information in
the clock and the resolution information from the main reconfiguration logic to determine
the appropriate bias current of the opamps.
The ADC was fabricated in a TSMC 0.6m DPTM CMOS process and occupies a total
die area of 10.5x7.6mm2 (Figure 2). The reconfigurable ADC intrinsically requires an
area only slightly larger than a 12-bit ADC, however, the prototype layout is optimized
not for area but for testability. The resolution of the ADC can be varied from 6 - 15 bits
while bias current can be varied over a range of about 3 orders of magnitude
corresponding to a sampling rate range of 20KHz-20MHz. Table 1 provides a summary
of representative measured results.
            Process                0.6m CMOS, DPTM
            Die Area                 10.5mm x 7.6mm
        Power Supply               2.7V-4.6V
   Parameter Reconfiguring       12 clock cycles
            Time
            Sigma-Delta 15 bit Mode (3.3V)
           Resolution                      15 bits
             Fclock                       10MHz
               Fin                       3.13KHz
                                   (1.5V p-p differential)
              OSR                          1024
             Power                         8.8mW
              HD2                         111.8dB
              HD3                         96.21dB
                Pipeline 12 bit Mode (3.3V)
           Resolution                      11 bits
             Fclock                      2.62MHz
               Fin                        1MHz
                                    (1V p-p differential)
             Power                       24.6mW
              DNL                      < +/- 0.55LSB
              INL                      < +/- 0.82LSB




Table 1. Measured results at two performance points.
Fig. 1. ADC architecture
Fig. 2. ADC micro-photograph.
Mixed-Signal Design in Deeply Scaled CMOS Technology

Personnel: John Fiorenza (H.-S. Lee and C. G. Sodini)
Sponsors: Center for Integrated Circuits and Systems, MARCO
keyword: ic

         There are tremendous challenges in implementing mixed-signal systems on a
single substrate in deeply scaled CMOS technologies primarily due to the negative
impact of the technology on analog circuits. Nearly every aspect of scaling except speed
goes against analog circuits. Lower power supply voltage severely restricts the signal
range, requiring substantially lower circuit noise in order to keep the signal-to-noise ratio.
Small geometry transistors exhibit far less voltage gain and greater threshold voltage
mismatches than their predecessors. Attempts to overcome device gain limitations with
conventional techniques such as cascode and regulated cascode aggravates already slim
signal swing. The use of long-channel devices for higher gain inevitably compromises the
circuit speed.

        In order to overcome the challenges, we are exploring innovative circuit
techniques that avoid shortcomings of deeply scaled technologies, and actually exploit
them in mixed signal systems. As the first step we have been investigating circuit
techniques that overcome the device gain limitations without penalizing the signal swing
or circuit speed. An innovative approach that we have developed employs two signal
paths: the main path and the prediction path. The prediction path processes the signal ½
clock phase earlier than the main path at a reduced accuracy. The information obtained
from the prediction phase is used to in the main path in order to compensate for the finite
device gain, incomplete settling and other non-idealities. The two-path approach can be
applied to many different classes of analog circuits including data converters, filters,
instrumentation amplifiers, and many others. As the initial proof-of-concept, we designed
a MOS sample-and-hold amplifier in a standard 0.18  digital CMOS process. The
simulation predicts the accuracy corresponding to 100dB amplifier gain with no
cascading. The chip design will be submitted for fabrication in April.


A CMOS-Compatible Compact Display

Personnel: Andrew Chen (A.I. Akinwande and H.S. Lee)
Sponsorship: 3M, MARCO
keyword: ic

The proliferation of portable electronic systems has created demand for high-resolution
displays which are compact and highly energy-efficient. We have designed and built a
proof-of-concept for a display that meets these design constraints. Our display uses a
standard digital CMOS integrated circuit to produce a low-brightness image, and an
image intensifier to increase brightness to a visible level. Since a only very low light level
needs to be generated from the CMOS chip the power efficiency is primarily determined
by the intensifier which typically exhibit high efficiency. Moreover, exploiting high level
of integration achieved by the CMOS IC, low power techniques such as pixel memory
and data compression can be implemented further lowring the system power
consumption. A display using our design should produce a daylight-visible image using
approximately half a watt of power.

Silicon devices can convert electrical energy into light, although their efficiency is very
low. We use silicon light-emitting diodes to produce a very faint image which is
optically coupled into an image intensifier. The image intensifier is a compact vacuum
device that uses cathodoluminescence to increase the brightness of an image. It is
comonly found in night vision scopes and scientific equipment. Cathodoluminescence,
using a phosphor to convert electrons to photons, is an established technology used in
cathode-ray tubes. Cathodoluminescent devices have high conversion efficiency (40
lumens/watt), high reliability, and can achieve very high output brightness (projection
televisions).

Our first research objective was to produce a laboratory demonstration of the system, and
to quantify its performance. An integrated circuit with light-emitting arrays was
fabricated in a commercial 0.18um CMOS logic process. Each array measured 16x32
pixels and included a wordline decoder. Each pixel contained a 1-bit digital memory
along with light emitter and driver circuits. We used the p+/nwell junction as a light-
emitting structure. Power conversion efficiency was approximately 10-6 (W/W), and we
observed a broad emission spectrum peaking at 700nm. A test system consisting of the
integrated circuit, microscope optics, and image intensifier has been constructed. Sample
images were recorded, as shown below. Grayscaling was demonstrated at 32-levels,
limited by the speed of the speed of the microcontroller.




                                                       top left: image from test system captured with
                                                       CCD camera, top right: 32-level grayscale
                                                       demonstration, bottom left: circuit board
                                                      including IC in 0.18um CMOS process.

In the near future, we will investigate circuit designs to support the integration of light
emitters onto CMOS integrated circuits. Memory can be added to the display to
eliminate the need for refreshing, thus reducing switching power. Analog, or digital
multiple bits-per- pixel memories are being investigated. In addition, row parallel current
level addressing is being investigated. This addressing allows analog and digital
calibration for precise brightness control of each pixel. High-level computation can be
integrated on-chip to perform image processing, or data compression/decompression, or
intelligent power management. High-resolution displays require large input data
bandwidth, for example computer monitors typically require over 2GHz bandwidth and
interface circuits dissipate high power. For example, The Silicon Image Sil 161B digital
video interface receiver dissipates 800 mW. Interface circuits using compression and/or
circuit techniques such as low-swing signaling can reduce the interface power
dramatically, lowering the overall system power.

We will also be investigating a RF wireless link between the display and the host. For
high resolution displays, even with on-chip data compression, the I/O data rate will still
be very high. For this reason, the traditional narrow-band wireless link is not a suitable
technology. We propose ultra-wideband data communication technology for host-to-
display data communication. This technology can potentially be extended to chip-to-chip
and back plane data communication as well. The ultra-wideband communication, which
has been in limited use for medium-to-long range (~mile), low-data rate communication,
employs a train of impulses rather than a single frequency RF carrier. The impulse train
has a very wide frequency spectrum, typically DC- GHz range. Since the energy is spread
in such a wide frequency range, there is negligible interference with traditional
narrowband RF systems. Unlike narrowband transceivers, highly frequency selective
circuits are unnecessary facilitating the integration of the entire transceiver. Also, the
effect of the multipath can be mitigated, and even exploited by measuring the arrival time
and the phase of the multipath signals. For this reason, the untra-wideband technology is
more suitable for short-range, fixed environment communication than the application that
has been in use. The host-to-display, chip-to-chip, and backplane communication can
benefit from the ultra-wideband communication because they are typically short-range,
fixed environment communication. The short-range nature of the host-to-display, chip-to-
chip, and backplane communication could provide a reasonable signal-to-noise ratio,
which, combined with ultra-wideband would provide potentially very high data rate
required in such data communication. Also, the host-to-display wireless link has an added
possibility of broadcasting to multiple displays.



Radio Frequency Digital-to-Analog Converter

Personnel: Susan Dacy (H.-S. Lee)
Sponsorship: Lucent Fellowship, ABB, and Center for Integrated Circuits & Systems
(CICS)
keyword: ic

Dynamic performance of high speed, high resolution, DACs is limited by distortion at
the data switching instants. Inter-Symbol Interference (ISI), imperfect timing
synchronization and clock jitter are all culprits. A DAC output current controlled by an
oscillating waveform is proposed to mitigate the effects of the switching distortion. The
oscillating waveform should be a multiple (k*fs) of the sampling frequency (fs), where
k>1. The waveforms can be aligned so that the data switching occurs at the zero
crossings of the oscillating current output. This makes the DAC insensitive to switch
dynamics and jitter. The architecture has the additional benefit of mixing the DAC
impulse response energy to a higher frequency. Instead of the conventional sinx/x DAC
impulse response roll-off, there is a large high frequency lobe near the control
oscillating waveform frequency (k*fs). An image of a low intermediate frequency (IF)
input signal can therefore be output directly at a high IF or radio frequency (RF) for
transmit communications applications.

A narrowband sigma-delta DAC with eight unit elements was chosen to implement the
RF DAC. A sigma-delta architecture allows the current source transistors to be smaller
 since mismatch shaping is employed. Smaller current source transistors have a lower
drain capacitance, allowing large high frequency output impedance to be achieved
without an extra cascode transistor. Elimination of the cascode reduces transistor
headroom requirements and allows the DAC to be built with a 1.8V supply.

The RF DAC is currently being designed in 0.18um, 1.8V CMOS technology. Target
specifications are a 17.5MHz conversion bandwidth centered around 942.5MHz with
60dB SNR and 80dB SFDR.



Analog Base-band Processor for Wireless Gigabit LAN

Personnel: M. Spaeth (H.-S. Lee)
Sponsorship: SRC
keyword: ic


        The base-band analog processor performs necessary signal processing on the 150
MHz base-band signal in the transmit and receive signal paths for a wide-band wireless
local area network. The individual channel characteristics depend on the RF signal fade
and interference. Broadcasting to multiple appliances requires channel equalization at the
receiver. In the receive (Rx) section, the wide-band amplifier amplifies the received
signal from the RF transceiver network and is followed by a equalization filter. The
amplitude of the signal following the channel equalization filter can very greatly,
depending on the channel conditions, so a programmable gain amplifier is needed to
better match the signal amplitude to the dynamic range of the subsequent analog-to-
digital converter. The demodulation of the carrier is then carried out in the digital
domain by a DSP.

       There are tremendous technical challenges in the development of the base-band
analog processor. The analog circuits in both the transmit and receive sections of the
processor must handle 150MHz of signal bandwidth with high signal-to-noise ratio.
These analog circuits include the wide-band amplifier (WBA), the programmable gain
amplifier (PGA), the anti-alias filter, the channel equalization filter, the D/A converter in
the Tx section, and the A/D converter in the Rx section. In order to digitize the wide 150
MHz signal band, the A/D converter must have an effective sampling rate of at least 300
MHz, and preferably above 600 MHz to ease the anti-alias and digital filtering
requirements. The preliminary estimate of the A/D converter resolution needed to handle
the wide dynamic range of the received signal is 12 bits. At present, such high
performance is beyond the capability of monolithic silicon integrated circuits.
Additionally, any harmonic and intermodulation distortion in the signal path produces
spurious signals in other sub-bands, so the WBA, the PGA, the anti-alias and channel
equalization filters and the A/D converter must exhibit very high spurious-free dynamic
range (SFDR) in addition to wide bandwidth. In the Tx section, the D/A converter and
reconstruction filter must posses similar performance levels. In order to address these
technical challenges, we propose to investigate innovative techniques for the base-band
analog processor.

This work focuses on the implementation of the extremely high speed, high resolution,
and wide-bandwidth A/D converter in the Rx section. To achieve high speed operation,
some degree of parallelism is often employed. In a parallel time-interleaved converter,
any mismatch in the gain, offset, or timing of the constituent channels results in
undesirable harmonics in the output spectrum, related to the sampling rate of the
individual channels. Therefore, the present time interleaving typically employs a small
degree of parallelism, so that the harmonics either out of the signal band of interest, or
below the quantization noise floor. Our approach is to use large-scale parallelism (64 or
128 channels) in a time-interleaved pipeline A/D converter. Back-end digital calibration
is applied to account for static gain, offset, and timing mismatch errors between channels,
so that the resulting calibrated output has sufficiently low spurious harmonics.

    Measurement and calibration techniques for gain and offset errors are performed using
standard calibration techniques. By digitizing a fast ramp using one converter as a fixed
timing reference for the remaining converters, the relative timing skew between channels
can be discerned. The calculated timing offsets are then used to re-time the output data
stream using polynomial interpolation in the DSP in the back-end. Thus all of of the
calibration is performed using simple algebraic operations with minimal latency. To
allow all of the calibration operations to be performed in the background, a small fraction
of the available channels are systematically pulled out for calibration, while a novel
token-passing control scheme selects which of the 'active' converters will sample the
incoming signal.

   Figure 1 shows a top-level block diagram of the proposed A/D converter. 129
identical pipeline A/D channels are organized into 16 banks of 8 converters, with one
additional converter used only as a skew timing reference. In this scheme 2 banks are
pulled out at a time for calibration, so the remaining 112 converters operate at about 5.5
MHz to achieve the desired 600MHz aggregate sampling rate. 14 bit pipelines are used
to generate 12 bit digitally error-corrected outputs. The converter bank that is actively
digitizing the input signal receive the output of the front-end anti-aliasing filter. The
converter banks that are under calibration may digitize DC values for gain and offset
measurements or the fast ramp for timing skew measurements. The converter has two
sets out outputs so that digitized signal samples and calibration data may be output
simultaneously. The back-end DSP averages the calibration data, and generates the
algebraic coefficients needed to correct the gain, offset, and timing mismatch errors.

(see attached file topblock.ps)


Substrate Noise Charaterization Shaping in Mixed-Signal Systems

Personnel: M. S. Peng (H.-S. Lee)
Sponsorship: Center for Integrated Circuits & Systems (CICS), MARCO
keyword: ic

The basic demands of power, speed, and cost drive the ever tighter integration of all
circuits in a system onto a single chip, or the so-called System on a Chip (SoC). This
necessitates the integration of analog circuits with digital circuits. However, in this
integration, the acute problem of substrate noise coupling arises. The noisy digital circuits
inject noise into the common substrate, which can severely affect sensitive
analog circuits. Improperly accounted for, this noise can degrade performance drastically,
and in some cases destroy functionality.

Up to now, most efforts in addressing this problem have been to ensure that analog
circuits are robust enough to withstand the digital noise. These techniques include
physical separation, differential architectures, and simulation. Hardly any effort has been
placed on reducing the substrate noise itself.

With this in mind, the focus of this research is to investigate the characteristics of the
substrate noise as well as ways to cancel the injected substrate noise. We have
implemented a test chip that includes a digital circuit as substrate noise generator and a
delta-sigma A/D converter that samples the substrate noise. The digital circuit is operated
in such way that it injects periodic noise waveform on the substrate. The delta-sigma
converter is used as an accurate on-chip sampling scope to map the substrate noise as a
function of time. The sampling edge of the delta-sigma A/D converter is moved relative
to the digital clock edge. Fig. 1 shows an example of measured substrate noise using this
technique.
                       Inv:0-
                       Inv:1-
                         >1
                         >0


               Fig. 1 Measured substrate noise with an on-chip sampling scope.



        In order to reduce the effect of the substrate noise, we propose to cancel and shape
the noise in bands of interest with a feedback loop. This type of noise shaping is well
suited for oversampling and bandpass type applications.

The substrate noise shaping loop is based on a delta-sigma modulator loop with the
substrate noise treated as quantization noise. The feedback D/A is replaced by an array
of noise-injecting inverters. This has the advantage of simplicity and low power.

Furthermore, the addition of an independent substrate noise shaping loop to the system
will require little effort and little loss of performance. The analog and digital circuits can
be designed as if there was no substrate noise shaping loop.

As proof of concept, a prototype chip has been designed that integrates the substrate
noise loop with a 16-bit delta-sigma A/D converter and a complex digital encryption
engine onto the same substrate. The chip runs at 2.5V and has been fabricated in
0.25um CMOS technology.

The chip is currently being tested and characterized. Preliminary measurements show
noise cancellation in desired bands of interest. Fig. 2 and Fig. 3 show the substrate noise
spectra before and after noise shaping. The substrate noise shaping reduces the overall
substrate noise by 15 dB in 0-45kHz frequency band.
       Magnitude (dB)




                             Frequency (kHz)
                        Fig. 2. Substrate Spec. w/out SN Shaping
Magnitude (dB)




                             Frequency (kHz)
                         Fig. 3. Substrate Spec. w/ SN Shaping
Superconducting Bandpass Delta-Sigma A/D Converter

Personnel: J. F. Bulzacchelli (H.-S. Lee and M. B. Ketchen -- IBM)
Sponsorship: Center for Integrated Circuits and Systems
keyword: ic

The direct digitization of RF signals in the GHz range is a challenging application for any
circuit technology. Traditionally, flash A/D converters have been used to digitize signal
frequencies above 1 GHz, but their resolution and linearity are inadequate for most radio
systems, which must handle signals with a large dynamic range. Semiconductor bandpass
delta-sigma modulators are used to digitize IF signals with high resolution, but their
performance at microwave frequencies is limited by the speed of
semiconductor comparators and the low Q of integrated inductors.

In this program, we present the design and testing of a superconducting bandpass delta-
sigma modulator for direct A/D conversion of GHz RF signals. The schematic of the
circuit is shown in Fig. (ref. no. 1). The input signal is capacitively coupled to one end of
a superconducting microstrip transmission line, which serves as a high quality resonator
(loaded Q > 5000). The current flowing out of the other end of the microstrip line
is quantized by a clocked comparator comprising two Josephson junctions. If the current
is above threshold, the lower junction switches and produces a quantized voltage pulse
known as a single flux quantum (SFQ) pulse. If the current is below threshold, the upper
junction switches instead. The pattern of voltage pulses generated across the lower
Josephson junction represents the digital output code of the delta-sigma modulator.
These voltage pulses also inject current back into the microstrip line, providing the
necessary "feedback" signal to the resonator. At the quarter-wave resonance of
the microstrip line (about 2 GHz in our design), the resonator shunts the lower junction
with a very low impedance, the "feedback" current to the resonator is maximized, and
the quantization noise is minimized. Because of the high speed of Josephson junctions
and the simplicity of the modulator circuit, the maximum sampling rate exceeds 40 GHz.

While such a high sampling rate improves the performance of the delta-sigma modulator,
the challenges of high speed testing in a cryogenic environment are formidable. Even in
the best cryogenic sample holders, the long cables used to connect the superconducting
chip to room-temperature electronics have significant losses at frequencies above 10
GHz. Experimentally, we found two solutions for clocking the circuit at high
frequencies. In the first approach (detailed in previous reports), we employ an
optoelectronic clocking technique, in which picosecond optical pulses at a 20.6 GHz
repetition rate are delivered (via optical fiber) to an on-chip photodetector, the current
pulses from which drive a Josephson clock amplifier. In the second approach, the
modulator is triggered by an on-chip clock source. An increase in bias current turns
the Josephson clock amplifier into an oscillator tunable between 20 and 45 GHz. We
found that surprisingly good frequency stability could be achieved with the on-chip clock
source with careful adjustment of dc bias currents.

Since the modulator output data rate exceeds the capacity of the interface to room-
temperature test equipment, on-chip processing of the data is used to reduce the
bandwidth requirements for readout. As explained in the 1998 MTL report, two
segments of the modulator's bit stream are captured with a pair of 128-bit shift registers.
The number of clock cycles skipped between acquiring the two segments is set by an on-
chip programmable counter (from 0 to over 8000). Cross-correlation of the two captured
segments is used to provide estimates of the autocorrelation function R[n] of the
modulator output, from n=0 up to a large value, such as n=8000. Fourier transformation
of R[n] then yields a power spectrum with frequency resolution comparable to an 8K FFT
of the original bit stream.

Fig. (ref. no. 2) shows the block diagram of the modulator test chip. As mentioned
above, the bandpass modulator can be clocked either externally by a 20.6 GHz optical
source or internally by an on-chip Josephson oscillator. A 1:4 demultiplexer converts the
single-bit output of the modulator to 4-bit words at one-fourth the sampling rate. This
allows most of the test chip, including the programmable counter and the shift register
memory banks, to operate at a reduced clock rate with larger timing margins. Because of
the 1:4 demultiplexing, 128-bit memory banks A and B are organized as 4 parallel rows
of 32-bit long shift registers. As just discussed, the number of clock cycles skipped
between loading the A and B memory banks is set by a programmable counter, which is
programmed by external control currents. Once the shift registers have been loaded, a
readout controller unloads the stored bits and transfers them to "high-voltage" drivers,
which amplify the output signals up to about 2 mV, which is large enough to be detected
by room-temperature electronics. The test chip employs over 4000 Josephson junctions
and represents one of the most complex circuits ever designed in this technology.

The test chip was fabricated at HYPRES, Inc. While the chip has been used with the 20.6
GHz optical clock, higher oversampling ratios and SNRs are attained with the on-
chip clock source operating near 40 GHz. In the initial experiments, the programmable
counter on the test chip was programmed so that the shift registers captured 256
consecutive bits from the modulator, so that 256-point FFTs could be calculated. The
output spectra of the modulator at a sampling rate of 42.6 GHz are plotted in Fig. (ref. no.
3). The width (about 500 MHz) of the input tone at 1.7 GHz reflects the low frequency
resolution of the 256-point FFTs. The full-scale (FS) input sensitivity is -17.4 dBm (30
mV rms). Quantization noise is suppressed at 2.23 GHz and at higher frequencies
corresponding to higher-order microstrip modes. The SNR (49 dB over a 20.8 MHz
bandwidth) is limited by the frequency resolution of the measurements but still exceeds
the SNRs of semiconductor modulators with comparable center frequencies. Other
measurements, based on the correlation technique discussed above, show that the in-band
noise over a 19.6 MHz bandwidth is -57 dBFS. The center frequency and sampling rate
of the experimental modulator are the highest reported to date for a bandpass delta-sigma
modulator in any technology.

(See attached file: mtl02fg1.ps)(See attached file: mtl02fg2.ps)(See
attached file: mtl02fg3.ps)
A CMOS Bandgap Current and Voltage References

Personnel: Matthew C. Guyton (H.-S. Lee)
Sponsorship: Center for Integrated Circuits and Systems
keyword: ic

Most analog circuits require reference voltages and currents that do not vary with power
supply voltages and temperature. Bandgap voltage references with an output voltage
around 1.2 volts have been popular for this purpose. However, producing non-integer
multiples of bandgap voltage requires an operational amplifier increasing the complexity
and power consumption. Bandgap current references also require an operational amplfier.

The focus of this research is to develop simple and low power bandgap current and
voltage references. We have developed a novel bandgap core circuit that produces a
bandgap referenced output current directly without an operational amplifier. This simple
circuit can even be operated as a 2-terminal bandgap current source. The same core
circuit can also be used to generate arbitrary non-integer multiples of bandgap voltage.

A prototype 2-terminal band-gap current source has been designed and fabricated
employing only 4 MOS transistors and 2 parasitic PNP transistors in a standard 0.35
CMOS technology. We are presently evaluating the first silicon.


Hae-Seung Lee, Professor,
Department of Electrical Engineering
and Computer Science (EECS)

Graduate Students
John Bulzacchelli, Research Assistant, EECS
Andrew, Chen, Research Assistant, EECS
Susan Dacy, EECS
John Fiorenza, Research Assistant, EECS
Kush Gulati, Research Assistant, EECS
Matthew Guyton, Research Assistant, EECS
John D. Morris, EECS
Mark Peng, Research Assistant, EECS
Todd Sepke, Research Assistant, EECS
Ayman Shabra, Research Assistant, EECS
Mark Spaeth, Research Assistant, EECS


Publications
     1.   K. Gulati and H.-S. Lee, "Low Power Reconfigurable Analog-to-Digital Converter " Digest of
          Technical Papers, 2001 International Solid-State Circuits Conference, Feb. 2001, San Francisco,
          CA
     2.     J. F. Bulzacchelli, H.-S. Lee, J. A. Misewich, and M. B. Ketchen, ``Analog-to-Digital Converter
            Testing Method Based on Segmented Correlations,'' IEEE Transactions on Applied
            Superconductivity, Vol. 11, pp. 275-279, March 2001.


     3.     Shabra, A. and H.-S. Lee, “A 12-bit Mismatch-Shaped Pipeline A/D Converter,” in Digest of
            Tech. Papers, 2001 Symposium on VLSI Circuits, July 2001, pp. 211-214.

     4.     K. Gulati and H.-S. Lee, "Low Power Reconfigurable Analog-to-Digital Converter ", IEEE J.
            Solid-State Circuits, vol. 36, pp 1900-1911, Dec. 2001.

     5.     J. F. Bulzacchelli, H.-S. Lee, J. A. Misewich, and M. B. Ketchen, "Superconducting Bandpass Delta-
            Sigma Modulator with 2.23 GHz Center Frequency and 42.6 GHz Sampling Rate," Digest of Technical
            Papers, 2002 International Solid-State Circuits Conference, pp. 188-189, Feb. 2002, San Francisco, CA.


     6.     Shabra, A. and H.-S. Lee, “Oversampled Pipeline A/D Converters with Mismatch Shaping,”
            accepted to IEEE J. Solid-State Circuits.



Student Theses, Ph.D.

          Gulati, Kush, "A Low-Power Reconfigurable CMOS A/D Converter," May 2001.
          Shabra, Ayman, "Mismatch Shaping in Pipeline A/D Converters," May 2001.


Student Theses, M. Eng.


          Morris, Jonh D., "Improving Toggle Rate in a Rail-to-Rail Comparator Output Stage," May 2001

Hae-Seung Lee's Research Interest: Analog and mixed signal integrated circuit design with the
emphasis on data converters, amplifiers, and communication circuits.

				
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