Herschel PACS - IBDR SIGNAL PROCESSING UNIT - SPU - by wio18411

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									PACS IBDR                                             27/28 Feb 2002




                          Herschel PACS - IBDR

                   SIGNAL PROCESSING UNIT
                                 - SPU -

            HW Unit, Start-up SW and Low-level SW Drivers



                    José M. Herreros
         INSTITUTO DE ASTROFÍSICA DE CANARIAS
                         - IAC -


Herschel PACS SPU - IAC                                           1
PACS IBDR                                           27/28 Feb 2002


                           CONTENTS

            1.   Electrical Design Evolution
            2.   Budgets.
            3.   Box Outlines and Block Diagrams.
            4.   Software
            5.   Model Philosophy.
            6.   CRISA Status Report.
            7.   Critical / Problem Areas.
            8.   Schedule.



Herschel PACS SPU - IAC                                         2
PACS IBDR                                           27/28 Feb 2002


             ELECTRICAL DESIGN EVOLUTION

• CPU BOARD:

     – Program and Data Memory sizes increase due to:
        • PACS data reduction/compression requirements
        • UTMC memories instead of WhiteElectronics

     – PSC ASIC Design consolidation (TEMIC manufacturer)

• DC/DC CONVERTER:

     – Removal of external synchronization



Herschel PACS SPU - IAC                                         3
  PACS IBDR                                                                       27/28 Feb 2002


                    New MEMORY ORGANIZATION
                                         LFI-REBA                  LFI-REBA           PACS-SPU
          Feature
                                           DPU                       SPU               SWL-LWL
Program ROM Size                        32 KW x 48                32 KW x 48          32 KW x 48
Program RAM Size                        128 KW x 48              128 KW x 48         256 KW x 48
                                        512 KW x 48              512 KW x 48         512 KW x 48
EEPROM Size                             256 KW x 48            Not implemented       256 KW x 48
Data RAM Size                           128 KW x 32              128 KW x 32         128 KW x 32
                                        512 KW x 32              512 KW x 32         512 KW x 32
Expansion Data RAM Size               Not implemented            512 KW x 32         512 KW x 32
Interface to MIL BUS             Included in Auxiliary Board    Not implemented     Not implemented
OBT timer                                  PMPSC               PMPSC (Not used)    PMPSC (Not used)
                                                                                   DMPSC (Not used)
Watchdog timer                            DMPSC                     DMPSC           Not implemented
Interface to DAU             -   End of Acquisition Interrupt  Not implemented      Not implemented
                             -   Internal analog acquisitions
                             -   1Hz Interrupt
                             -   OBT Clock Sync status
                             -   1Hz signal control
Interface to DAE             -   DAE Power Status input       - DAE Data ready      Not implemented
                             -   DAE reset SMCS1 output         Interrupt
                             -   DAE reset SMCS2 output
Interface to SPU             -   Reset to SPU                 - Reset from SPU      Not implemented

   Herschel PACS SPU - IAC                                                                     4
PACS IBDR                                                   27/28 Feb 2002


                          SPU UNIT BUDGETS


                                     IIDR               IBDR
                                  (01-03-01)         (27-02-02)


    DIMENSIONS (mm)
    (LENGTH X DEPTH X HEIGHT)   242 X 183 X 102    238 X 205 X 97
    (WITHOUT AND WITH FEET)     242 X 213 X 102    270 X 215 X 97


    POWER (W)                         20           30,29 (AVERAGE)
                                (20% CONTINGENCY     35,04 (PEAK)
                                    INCLUDED)



    MASS (KG)                        5,546              3,757
                                (20% CONTINGENCY   (10% CONTINGENCY
                                    INCLUDED)          INCLUDED)




Herschel PACS SPU - IAC                                                 5
PACS IBDR                                   27/28 Feb 2002


                     PACS SPU BOX OUTLINE

  LFI-REBA




Herschel PACS SPU - IAC                 PACS-SPU        6
   PACS IBDR                                                                                   27/28 Feb 2002


                 SPU FUNCTIONAL BLOCK DIAGRAM
                            SPU
                                                                 The CPU board is designed to include as maximum:
                           SPU-SWL
                                                                  One DSP working at 18 MHz
                                                                  One 32 KW x 48 Boot PROM bank
                 IEEE
SPU_SWL_LVDS_1
                 1355
                                        DSP
                                               SPU_SWL JTAG
                                       21020

                 IEEE
                                                                  Three EDAC protected SRAM memory banks:
SPU_SWL_LVDS_2
                 1355
                                                                       512 KW x 48 for Program RAM
                                       MEM

SPU_SWL_LVDS_3
                 IEEE
                 1355
                                                                       512 KW x 32 for Data RAM
                                                                       512 KW x 32 for expansion of Data RAM
                                                                  One EDAC protected up to 256 KW x 48
                           SPU-LWL                                   EEPROM memory bank.
SPU_LWL_LVDS_1
                 IEEE
                 1355
                                                                  Three IEEE1355 DS links including one
                                        DSP
                                       21020
                                               SPU_LWL JTAG          common 8KWx32 Dual Port RAM buffer
SPU_LWL_LVDS_2
                 IEEE
                 1355
                                                                  Two PSC ASICs including:
                                       MEM                             Watchdog, OBT and 32 bit GP Timers.
                                                                       EDAC logic and Interrupt management.
                 IEEE
SPU_LWL_LVDS_3
                 1355


                                                                       Programmable Address decoding and
                                                                          Wait State generator.
                             DAU                                  One Auxiliary Board Interface, including:
   ANALOG HK
     DATA
                  INTERN
                    ACQ
                                                                       One redundant interface to the MIL-STD-
                                                                          1553 bus including one 8KWx16 Dual Port
                                                                          RAM buffer.
                             DC/DC
                                               S/C PRIMARY PWR
                                                                  One Mother Board Interface
                           CONVERTER


                             PSU
                                                                 Each CPU board executes its own specific Start
                                                                     Up and Application Software.

     Herschel PACS SPU - IAC                                                                                    7
PACS IBDR                                     27/28 Feb 2002


                          CPU BLOCK DIAGRAM




Herschel PACS SPU - IAC                                   8
PACS IBDR                                            27/28 Feb 2002


                    DC/DC CHARACTERISTICS

• Input Voltage Operation from 26 to 32 Volts
• Use of a SMART Converter
  (Buck / Push-Pull with conductance Control)
• Buck Switching Frequency Operating around 130kHz
• Outputs Voltages as follow :
   – +5 Volts
   – +/- 15 Volts




Herschel PACS SPU - IAC                                          9
PACS IBDR                                                                                                     27/28 Feb 2002


                                            DC/DC BLOCK DIAGRAM
            F001 : INPUT FILTER                                                                            F006 : OUTPUT STAGE
                                                   F005 : BUCK STAGE             F006 : PUSH-PU LL STAGE
        Co mmon & Diff erential M ode




                        GND




                                                                                                                                 GND




                               F003 : APS          F004 : CONTROL STAGE
                                                  Buck Co nduct an ce Cont rol
                                                      Push-Pu ll Cont rol

                           GND


                                                                   GND




                                                  F002 : PROTECTION & RESET
                                                    Over-Volt age Prot ect ion
                                                    Under-Voltage Prot ect ion




                                                                   GND




Herschel PACS SPU - IAC                                                                                                                10
PACS IBDR                                      HERSCHEL-PACS-SPU                                 27/28
                                                                                   DAU BLOCK DIAGRAM                    Feb 2002

                                                 TH_SPU_SWLa
                                                TH_SPU_SWLb
                                                 TH_SPU_LWLa
                                                 TH_SPU_LWLb



                                                                                    ANALOG TELEM ETRY




                          EXTERNAL CONNECTOR
                                                 TH_PSUa                              CONDITIONING
                                                                                     THERMISTOR




                                                                                                                             INTERNAL CONNECTOR
                                                 TH_PSUb




                                                 VCC_CUR_HK_P




                                                                         CURRENT
                                                                         SENSING
                                                                                       VCC CURRENT
                                                                                    CONDITIONING CIRCUIT
                                                 VCC_CUR_HK_N



        DAU                                                      VCC



       BLOCK                                     VCC_VOLT_HK



      DIAGRAM
                                                                                      VCC VOLTAGE
                                                                                   CONDITIONING CIRCUIT


                                                                                                      +15V   +15V_AUX
                                                                 DGND


                                                                                                             AGND


                                                 15VP_CUR_HK_P                                               VCC




                                                                         CURRENT
                                                                         SENSING
                                                                                                             DGND
                                                                                       +15V CURRENT
                                                                                    CONDITIONING CIRCUIT
                                                 15VP_CUR_HK_N




                                                                 +15V




                                                 15VP_VOLT_HK
                                                                                      +15V VOLTAGE
                                                                                   CONDITIONING CIRCUIT



                                                                       AGND




Herschel PACS SPU - IAC                                                                                                        11
PACS IBDR                 27/28 Feb 2002




          ASIC
         BLOCK
        DIAGRAM




Herschel PACS SPU - IAC              12
 PACS IBDR                                                    27/28 Feb 2002


     START-UP SW AND LOW-LEVEL SW DRIVERS
                                       •   Both SWL-SPU and LWL-SPU
                                           contain their own separate but
                                           identical PROM SW activated
                                           simultaneously during the
                 Responses                 switch-on of the SPU or under a
                                           SW reset.
SPU_SUSW
                             DPU_ASW   •   The Start-Up SW will perform
                                           the necessary functions to boot
                 Commands                  the unit at power up, perform a
                                           health self-test and start the
                                           Application SW giving it the
               CONTEXT DIAGRAM             control.
                                       •   The Low-Level SW drivers is a
                                           set of primitives (source/object
                                           code) to be compiled/linked
                                           with the different application
                                           software package.

   Herschel PACS SPU - IAC                                               13
                                               SPU Start up SW
PACS IBDR                                                                               27/28 Feb 2002
                      Hardware Reset                         Power up init




                                                       Reset source discrimination




    PACS SPU
  START-UP SW                                                Hardware tests



 ARCHITECTURE                             Warm Reset




                                                       Configuration for command loop
                                                                  execution




                                   Uses                        Command loop




                                                          Control transfer to APSW




                     LLSW_DRV




Herschel PACS SPU - IAC                                                                            14
                                                                  Application SW
PACS IBDR                                                                27/28 Feb 2002


                        SPU MODEL PHILOSOPHY



                                     LFI-REBA   PACS-SPU
             MODEL                                                 NOTES
                                    -NUMBER-    -NUMBER-
  ENGINEERING MODEL (EM)                 1         1     COMMERCIAL COMPONENTES

  AVIONICS MODEL (AVM)                      1      1     COMMERCIAL COMPONENTES

  QUALIFICATION MODEL (QM)                  1      0     MILITARY COMPONENTS

  FLIGHT MODEL (PFM)                        2      2     HI-REL COMPONENTS

  FLIGHT SPARE (FS)                     (x)        (x)   HI-REL COMPONENTS


  Note (x): Only one board for each type.




Herschel PACS SPU - IAC                                                             15
PACS IBDR                                                         27/28 Feb 2002

MODEL                                   BUILT STANDARD
               NON REDUNDANT UNIT (SINGLE BOX)
               ELECTRICAL AND FUNCTIONAL REPRESENTATIVE OF THE FLIGHT MODEL
               NON REPRESENTATIVE IN FIT AND FORM OF THE FLIGHT MODEL
               COMMERCIAL HYBRID DC/DC CONVERTER
 EM
               PROCESSOR SUPPORT CHIP (PSC) IN FPGA
               COMMERCIAL GRADE COMPONENTS
               SOFTWARE FLIGHT STANDARD (VERSION 1)
               NON DELIVERABLE MODEL
               NON REDUNDANT UNIT (SINGLE BOX)
               ELECTRICAL AND FUNCTIONAL REPRESENTATIVE OF THE FLIGHT MODEL
               NON REPRESENTATIVE IN FIT AND FORM OF THE FLIGHT MODEL
               FLIGHT DC/DC CONVERTER DESIGN
 AVM           PROCESSOR SUPPORT CHIP (PSC) IN FPGA
               COMMERCIAL GRADE COMPONENTS
               SOFTWARE FLIGHT STANDARD (VERSION 1)
               EMC CONDUCTIVE EMISSIONS TEST
               TO SUPPORT INSTRUMENT AND SYSTEM LEVEL TEST
               FULL REDUNDANT (TWO IDENTICAL BOXES)
               FULL FLIGHT STANDARD
               PROCESSOR SUPPORT CHIP (PSC) IN ASIC
 FM
               HI-REL GRADE COMPONENTS
               UNITS (NOM + RED) TO BE SUBMITTED TO ACCEPTANCE LEVEL TESTS
                   VIBRATION, THERMAL/VAC AND EMC

Herschel PACS SPU - IAC                                                         16
PACS IBDR                                           27/28 Feb 2002


                 CRISA STATUS REPORT (1/4)

1. Contract / Commercial / Management
•  Phase 1 - conditioned final milestone - achieved on W51
•  Phase 2 - 2nd progress Milestone - took place on W51.
•  Phase 3 ITT not set.
2. HW & System Engineering
•  System engineering activity: Production of revised system
   documents for the system BDR (HW/SW ICD).
• Design engineering activity: DC/DC Electrical design
   consolidated. PCB design finished.
3. SW Engineering
• Integration under way. Little adaptations being implemented in
   parallel with the tests.

Herschel PACS SPU - IAC                                        17
PACS IBDR                                                 27/28 Feb 2002


                 CRISA STATUS REPORT (2/4)

4. ASIC Development
• ASIC tests and integration fully completed in representative
   FPGA. Now working in the ‘coberture’ (failure simulations) as
   part of the industrial file for procurement. This activity resulting
   more complex than expected will be finished beginning W10.
   The complete dossier is expected to be ready by end March
   2002.
5. Physical & Verification Engineering
• None.
6. Unit Tester Engineering
• Unit tester HW & SW (1st) in work area.
• Complementary ‘test set’ ready in work area.

Herschel PACS SPU - IAC                                              18
PACS IBDR                                         27/28 Feb 2002


                 CRISA STATUS REPORT (3/4)

7. Procurement & Parts Engineering
• DC/DC CV PCB for AvMs ordered week #8.
• Last steps of the Procurement for AvM going on compatible
   with schedule. No critical conflict still envisaged.
• Changes to DCL (coming from DC/DC design) to be reported on
   February 22nd 2002 to TLG and IAC.
8. MAI Activities
• New CPUs set under MAI, about 60% achieved. No conflict
   envisaged up to now in plant to fulfil delivery dates. Two
   boards already waiting to be tested.
• 1st DAU and AUX ready for tests.


Herschel PACS SPU - IAC                                      19
PACS IBDR                                               27/28 Feb 2002


                 CRISA STATUS REPORT (4/4)

9. Tests activities
• 1st CPU under HW Characterisation. Timing problems detected
    outside the CPU, concretely within the NAIS test board (an
    auxiliary I/F board with the logic analyser used in test). Once
    confirmed this fact, tests have been normally resumed. They
    are satisfactorily running at good rhythm by now.
• SW (version 1) integration under way. Last steps performed
    consisting on the successful initiation of the 1355 / SCMS tests.
10. EMs / AvMs Delivery Schedule - no margin included -
• EM SPU ready for delivery:               15/03/02
• EM REBA ready for delivery:              04/04/02
• AvM SPU ready for delivery:              16/04/02
• AvM SPU ready for delivery:              04/04/02

Herschel PACS SPU - IAC                                            20
PACS IBDR                                            27/28 Feb 2002


                 CRITICAL / PROBLEM AREAS

• Financing for PACS-SPU and LFI-REBA Qualification stage:
  Confirmed un-officially.

• Funds expected for end of December not received.
  Negotiations in progress.

• ITT for Phase III: Qualification and QM
  Not started pending of receiving funds.

• Request for financing Phase IV: Flight Models
  To be made before 15 of March.

Herschel PACS SPU - IAC                                         21

								
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