# An Introduction to IBIS Models and Signal Integrity Simulation by wio18411

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```									    An Introduction to
IBIS Models
and
Signal Integrity Simulation

Shahana Tanveer
Northrop Grumman
April 13, 2004
What is SI?

Peak voltage: ~3V

GND
1.7V
Maximum
undershoot: 1.7V
MFG Abmax is -.5V

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Common Signal Integrity Problems

Common Signal Integrity (SI) problems include:
 Undershoot/overshoot
 Ringing
 Crosstalk
 Power/ground plane noise, ground bounce

It is important to lay out the PWB to eliminate possible SI problems.

Things to consider:
    Termination Schemes
    Layer Stack up
    Trace width/spacing/length/impedance
    Bypassing

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Modification: Harness Came in Too Long

Board Dimensions 3" x 5"   4
Solving SI problems - Simulation

 SI simulation is becoming more common with
the availability of quality tools that fit
seamlessly with the PWB layout flow.
 SI simulation becomes more important with
faster operational speeds and higher density
requirements.

A line is electrically long when:
Propagation delay, tp > Rise Time, tr/4,
Where tp = Length, L/ velocity, v

Assuming v = 1.4 x 108 m/s
When tr = 2.5 ns, L = 8.75 cm
But when tr = 1 ns, L = 1.05 cm

So as edge rates are getting faster and faster with
the newer technologies, it is becoming more
important to consider transmission line effects,
termination and possible signal integrity problems
in the PWB design.
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Simulation Models: SPICE

SPICE….
 SPICE simulations model a circuit at transistor level, thus SPICE models
contain detailed information about the circuit and process parameters which is
regarded as proprietary and IC vendors are reluctant to provide..
 Not all SPICE simulators are fully compatible.
 Although SPICE simulation accuracy is typically very good, a significant
limitation with this type of modeling is simulation speed.
 SPICE has various simulator options that control accuracy, convergence and
the algorithm type, and any options that are not consistent might give rise to
poor correlation in simulation results across different simulators.

IBIS, is an alternative to SPICE simulation.

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Simulation Models: IBIS
IBIS: Input/Output Buffer Information Specification from the
Electronics Industry Alliance
 IBIS behavioral data is taken from actual devices.
 IBIS models tend to simulate much faster than SPICE models.
 IBIS Modeling provides a simple table-based buffer model for
semiconductor devices.
   IBIS models can be used to characterize I/V output curves, rising/falling
transition waveforms, and package parasitic information of the device.
   IBIS models are intended to provide nonproprietary information about
I/O buffers and are more easily available from different IC vendors
   Non-convergence is eliminated in IBIS simulation.
   Virtually all EDA vendors presently support IBIS models, and ease of
use of these IBIS simulators is generally very good.
   IBIS models for most devices are freely available over the Internet
making it easy to simulate several different manufacturers’ devices on
the same board.

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Elements of an IBIS Model

[2]

[3]
[4]

[5]
[1]

8
Elements of an IBIS Model
Element 1: Pull-down
 Describes the I/V characteristics during pull-down.
 Data for minimum and maximum current for given
voltages.
 Data is taken for -Vcc to 2Vcc as that allows a
behavioral model for signal reflections caused by
improper termination and overshoot and undershoot
situations when the protection diodes are forward
biased.
Element 2: Pull-up                                         Element [1]
 Describes the pull-up state of the buffer when the
output drives high.
 Data is entered using the formula Vtable =
Vcc – Voutput
 The minimum and maximum values are determined
by the minimum and maximum operating
temperatures, supply voltages and process variations.
 Combining the highest current values with the fastest
ramp time and minimum package characteristics, a
fast model can be derived. A slow model can be          Element [2]
derived by combining the lowest current with the
slowest ramp time and maximum package                                 9
characteristics.
Elements of an IBIS Model
Element 3: GND and Power Clamps
 Describes the ground and power clamp diodes.
 The GND clamp curve is derived from the
ground relative data gathered while the buffer
is in the high-impedance state and illustrates
the region where the ground clamp diode is
active. The range is from -Vcc to Vcc.
 The power clamp curve is derived from the
Vcc relative data gathered while the buffer is
in a high impedance state and shows the
region where the power clamp diode is active.
This measurement ranges from Vcc to 2Vcc.

Element [3]

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Elements of an IBIS Model
Element 4: Ramp
 Describes the ramp time for the pull-up and pull-
down devices. Ensures proper AC operation of the
model.
 The min and max columns represent the minimum
and maximum slew rates for the buffers.                 Element [4]
 The values represent the intrinsic values of the
transistors with all package parasitics and external
loads removed.

Element 5: Package
 Adds the component and package parasitics.
 C_comp is the capacitance of the die itself,
excluding the package capacitance.
 Package characteristic resistance, inductance and
capacitance are added by R_pkg, L_pkg, and
C_pkg, respectively.                                   Element [5]

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Putting it all together – the IBIS File

A standard IBIS model file consists of three sections:
 Header Info–this section contains basic information about the
IBIS file and what data it provides.
 Component, Package, and Pin Info –this section contains all
information regarding the targeted device package, pin lists, pin
operating conditions, and pin-to-buffer mapping.
 V-I Behavioral Model–this section contains all data to recreate I-
V curves as well as V-t transition waveforms, which describe the
switching properties of the particular buffer.

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Putting it all together

Header

Component

Model I-V Data

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Caution!
Not all models can be trusted out of the box!
|***********************************************************************
| RTSX-S IBIS Model (RT54SX32S and RT54SX72S)
|***********************************************************************
[IBIS ver]   3.2
[File name]   rtsxs.ibs
[File Rev]   1.1
[Date]      March 1, 2004
[Disclaimer] All V/I data was verified for accuracy against bench measurements. The measurements were done
on typical production parts. 3.3V PCI model has not been verified against silicon measurements.
Please check Actel IBIS page for updates at http://www.actel.com/

|******************************************************************************
| IBIS file 6325q83f.ibs created by Jason Lew
|******************************************************************************
[IBIS ver] 2.1
[File name] 6325q83f.ibs
[File Rev] 2.x
[Date]      April 9, 2003
[Source]     From Lab mesurement at Quicklogic.
[Disclaimer] This information is for modeling purposes only, and is not guaranteed.

Be aware of what you are using!
Make certain that models come from trusted sources and are verified
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Setting up the Simulation
 Import CAD data into Simulation tool (translation
is seamless if using the simulator tool supported
Layout tool). This incorporates trace routing, via,
power plane information into simulation.
 Set up simulation environment with different
parameters (as shown below).

Link models
to devices

Generate Stimulus

Define Board Construction

Specify Noise Rules
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Viewing Results

Various Result options:

Simulation Waveforms

Violation Reports

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Simulation Examples

Example 1: Actel AX driving Xilinx input       Simulation helped choose termination
 1V overshoot and undershoot                 value, topology
 Use simulation to test different IO
buffers for optimum buffer selection
that meets both timing and SI
AX High Slew Driver
requirements.
Violates Device Abs Max

AX Slow Slew Driver          AX Fast Slew Driver with 45 Ohm
Cannot meet device timing       Termination: Cleans Signal

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Simulation Examples

Question: How would RTSX-S                 Use RTSX-S Buffer model with same
behave in this environment?               routing
 Simulate both High Slew and Slow Slew
RTSX-S
SX-S High or Slow slew: Same
SX-S with 45 Ohm Termination:
rising edge, slower only on falling edge
Cleans Signal

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Simulation Examples

Example 2: RTSX-S on multi driver signal (other end Xilinx Virtex)

Overshoot and undershoot violates Abmax
Use Simulation to try different Termination
schemes:
- Series termination at RTSX-S
- RC termination at Xilinx

Unterminated RTSX-S driver

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Simulation Examples

With 45 Ohm at RTSX-S – overshoot and undershoots removed

45 Ohm at RTSX-S, RTSX-S driving   45 Ohm at RTSX-S, Xilinx driving (12S
driver)

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Simulation Examples
RC termination at Xilinx:
12S driver
 Reduces overshoot and undershoot
 But reveals problems with the
Xilinx driver

RC termination, RTSX driving       RC termination, Xilinx driving

16F Driver

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Advanced Simulation

 Include true power/ground characteristics instead of assuming ideal
planes
 Simulate the effects of Simultaneously Switching Outputs, identify
possible false logic switching
 Optimize decoupling strategies
 Determine worst case power/ground voltage fluctuations

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References

 High Speed Digital Design by Howard W. Johnson and Martin
Graham.
   http://www.eigroup.org/ibis/
   www.actel.com
   www.mentor.com/icx
   www.sigrity.com

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