ADF4193 Low Phase Noise, Fast Settling PLL Frequency Synthesizer by zrl90908

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									          ADF4193

Low Phase Noise, Fast Settling
 PLL Frequency Synthesizer




                                 1
                      BASED ON

     A 10ms Fast Switching PLL
    Synthesizer for a GSM/EDGE
            Base-Station

                            By
            Mike Keaveney, Patrick Walsh,
           Mike Tuthill, Colin Lyden, Bill Hunt

ISSCC 2004 / SESSION 10 / CELLULAR SYSTEMS AND BUILDING BLOCKS / 10.6


                                                                        2
FUNCTIONAL BLOCK DIAGRAM




                           3
No connection here



                     50Ω




                     52Ω




                           4
                   FEATURES
•   New fast settling fractional-N PLL architecture
•   Single PLL replaces ping-pong synthesizers
•   0.5 degree RMS phase error at 2 GHz RF output
•   Digitally programmable output phase
•   RF input range up to 3.5 GHz
•   3-wire serial interface
•   On-chip low noise differential amplifier
•   Phase noise figure of merit –216 dBc/Hz
•   Loop filter design possible using ADI SimPLL
APPLICATIONS
• GSM/EDGE base stations
• PHS base stations
• Instrumentation and test equipment
                                                      5
   Background – GSM Base-station
     Synthesizer Requirements
               30ms          547ms

     Tx @ f1                 Tx @ f2              Tx @ f3


PA o/p power

                  ~10ms for Tx Synth. to switch

• Switch frequency in 10ms     => Wide PLL BW

• Low Phase Noise during Data Burst
• Low Spurious during Data Burst
                                       } => Narrow PLL BW
                                                            6
                Phase Noise & Lock Time Simulations
                            Phase Noise
                              (dBc/Hz)
                                          -100


                                          -140                                                  320kHz BW:
                                                                                                Lock Time: 6.3ms
                                                       1kHz               1MHz
Frequency
            (MHz)




                     1880                                    40kHz Loop BW:          1880
                                                             Lock Time: 120ms
                     1805                                                            1805

                       50                                                              50
Phase
            (Deg.)




                       0                                            N=1880/104         0
                                                                0.8*75M/(2pN)=528k
                      -50                                                             -50
                            0         50         100   150        No cycle slip if          0      5    10     15

                                     50 ms/div.                 BW>0.8*Fstep/2pN                   5 ms/div.
                                                                 [Cicero JSSC’00]                                   7
                 8x Bandwidth Switching
             KV ICP .F(s)                Charge Pump
 Loop Gain                               Cell Array,
               2p .N                      ICP<63..0>         KV
                                Fref
                                                        CZ    s   Fout
                      64x ICP          PFD
36dB
                                                  CP     R/8
 0dB
                                                         7R/8
        1x ICP
-135o                                        N

-180o
                 f0    8f0             Wide BW: 64x ICP & R/8
                                       Narrow BW: 1x ICP & R
    [Ref: Crowley ‘78]
                                                                    8
             PLL Static Phase Error
                Matched                 Mismatched
      Fref
     Fdiv
     UP
   DOWN
               +ICP          Dt  ICP                  t  DICP
 Charge
 Balance:      -ICP
                      t                           Dt

              At Balance:   Dt  ICP = t  DICP

       5º @ 1.85GHz  7.5ps ( 0.065º @ 26MHz)

With t = 3ns, for Dt < 7.5ps, requires ICP mismatch < 0.25%
   Conventional Charge Pump PLL
                                           ICP<63..0>
                                          UP
 ICP Envelope                         PFD DN


   0        64x          1x
                                           N

Output Phase (simulation)
                                               64x → 1x ICP
200°/                                          mismatch D = 10%
 div.                                               Df = 200°

        0                              Ideal
                  Time (5ms / div.)                               10
    Differential Charge Pump Concept
                                     • Better Up/Down
         mp1            mp2            Matching
Vbias1
                Vtune
                                       – Same Type Devices
UPp                            DNp     – Symmetric Layout

                + –
         CPO+           CPO–       • Charge Injection is
                                     Common Mode to
DNn                            UPn
                                     Vtune
Vbias2
         mn1            mn2
                                     • Requires
                                       – Low Noise Diff-amp
                                       – CMFB                 11
Charge Pump Cell with Chopped Outputs
                                 5V
 Vbias1   mp1                                          mp2

                      UPp1   DNp2     UPp2      DNp1


    ~2V                   CPO+          CPOB–                ~2V

                     DNn1    UPn2     DNn2   UPn1

 Vbias2
          mn1                                          mn2



                  Fref
                f1 , f2
           UP1,DN1
           UP2,DN2                                                 12
  Chopped Up/Down Signal Paths from PFD
            f1
Fref
                           UP1, DN2
                 D Q
       f2
                  RB

                       t
                  RB
       f2        D Q
Fdiv                       DN1, UP2
            f1                    f1   f2

                           Fref
                           Fdiv
       Chopped Output Charge
                                            13
                         Diff-Amp

 CPO –                                   500     500
                                                         Vout
     1000
             0.5                                 –
                                                 +

                     1000                                Vref
CPO +                        0.5         500      500

                   5mA             5mA
                                                       Phase Noise
                                               -100
• PLL suppresses DC errors & 1/f noise.
• Want zero IIN mismatch  MOS i/p’s           -130

• Noise > 40kHz → FM sidebands                             40kHz
        < 7nV/Hz required @ Vout
                                                                     14
     Common Mode Feedback Loop
                              200mA          +
                                             –
UP               ~2V
                                             +
     DN                                      –




                                   UPp
                                            +         CPO+
                                   DNp
                                       Charge
              UP                   UPn Pump
                                            _          CPO–
          PFD DN                   DNn


• Pulse Stretch circuit
   → Fast leading edge, current controlled trailing edge
   → Control current mirrored to both up and down pulses.
     CMFB Pulse Stretch Signals
             UP
             DN   } from PFD
            UPp
            DNp   } to PMOS switches
            UPn
            DNn
                  } to NMOS switches
Phase info         Differential CP output
from PFD
remains intact
                   Common Mode output


                                            16
            Proposed Fast Locking PLL
                             External
                                                          R3/7
Fref   f1               +
             D                2C2       2C1
                    Charge                       +                    Fout
       f2           Pump
                                  R2/16
                                                –
                    <64:1>        7R2/16                  R3
                                                                 C3
       f2     D         –
                                  2C2   2C1

       f1                         R2/16
                                                          External
        Fast Lock                 7R2/16

        Control
                                              ÷ N / N+1
 Open R2 & R3           Mod-130
 switches when            SD
 ICP is @ 1x
       ICP Reduction with SD Compensation
      16
ICP
(mA)
       0
                                                                  2     MUX
                                                                       1
  Fref                                                  +   Z-1        0
  X2
                  17                      18                           X2
                       Time (µs)
                          1
                                  3
                                      3
           FRAC
                  +           
                                               1              SD Out
                   –
                    +                             +

                                               X2
                              130
                    Measured: Phase Lock Time
                              75 MHz jump from 1880 to 1805 MHz
                  25


                  15
Phase (Degrees)




                   5


                   -5


                  -15


                  -25
                        -10   10    30    50      70       90   110   130   150

                          Start                Time (ms)
                                                                                  19
                    Chopping Off vs. Chopping On
                    40
                                            Chopping Off
  Phase (Degrees)



                    20


                     0

                                Wide           Narrow
                    -20
                                BW              BW

                    -40
                          -10    10    30        50        70   90
                                        Time (ms)
Measured:
 ~1% ICP mismatch change  20° phase step w/o chopping
         Measured: Output Phase Noise


                                    DCS-1800 Tx LO Mask
dBc/Hz




           RMS Phase Error (SSB) = 0.25°




    Fout = 1860MHz, Fref = 26MHz, Chopping @ Fref/2
               External VCO (Vari-L 1843T)                21
Measured: Spur Side-Band Levels
                Fout = 1872.4 MHz (N = 72 2/130)

        0

       -20        Integer Boundary Spurs:
                  -75dBc @ Df = +/- 400kHz
       -40
dBc




       -60                          Chopping:
                                    <-95dBc @ Df = 13MHz
       -80

      -100
         1872           1877                 1882          1887
                           Frequency (MHz)

 Chopping @ Fref/2, (with 2% measured ICP mismatch)
                                                                  22
                   Die Photo
   N                                       Diff-Amp

Lock
Detect        Serial                         Loop
            Interface              Charge
   R                                        Filter
                                   Pump      Switches
                                    Array
    PFD
                        Timers &
                                             CMFB
                         Control


  SD
Modulator                                     BGR


                                                       23
         Performance Summary
Lock Time                      10 ms
RMS Phase Error                0.25 deg.
Idd: Charge Pump (5V)          33 mA
      Diff-amp (5V)            30 mA
      Remainder of chip (3V)   20 mA
Fractional Spurs (worse case at -75 dBc @ 400kHz
integer boundaries):            -85 dBc @ 600kHz
Spur due to Chopping @ Fref/2: < -95 dBc @ 13MHz
Reference Spur:                 < -95 dBc @ 26MHz
Chip Size                       2.29 x 2.32 mm
Technology                     0.35m BiCMOS w/ 5V options
Package                        5x5mm 32 lead LFCSP
                                                        24
                 Summary
• Static Phase Error due to Up to Down Mismatch
  in the PFD and Charge Pump blocks can be
  eliminated using a chopping scheme.

• Loop Gain Changes during BW switching can be
  digitally compensated for in the SD Modulator.

• A PLL based synthesizer can jump over the full
  TX band in <10ms and still meet the phase noise
  and spurious requirements for a GSM and
  EDGE base-station.
                                                    25

								
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