Analytical Bound for Unwanted Clock Skew due to Wire-Width Variation by via28446

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									Analytical Bound for Unwanted
Clock Skew due to Wire-Width
            Variation
     Anand Rajaram, Bing Lu †, Wei Guo ‡,
          Rabi Mahapatra, Jiang Hu

             Texas A&M University
           † Cadence Design System
           ‡ Instiut Français Pétrole.


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Presentation Outline
 Introduction
 Previous works
 Problem formulation
 Skew bound via wire shaping analysis
 Experimental results
 Conclusion



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Major Concern for Clock Network
     Skew - delay difference between sinks
      in clock tree
                          D1


             Clock                 Skew =D1- D2
             Driver


                          D2

       Process variations cause unwanted skew

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   Process Variation
               Etching
                errors               Spot
Gate length                         defects
      tox
                     Junction
                     depth      T             W
                                      S
                    Mask
Gate width       misalignment   H

                                Ground plane




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Interconnect Variation
   Significantly affects delay and skew
       May cause up to 25% clock skew variations   ( Y. Liu,
        et al., DAC 2000 )

   Needs to be estimated during clock network
    design and in post design analysis
   Difficult to be modeled – distributive in nature

                                          1 segment
                                              Or
                                         N segments?
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Previous Works - Monte Carlo
 Monte Carlo Analysis – vary wire size
  randomly for a large number of times
  and pick the worst case skew
 Advantages – reliable when repeated
  for a large number of times
 Disadvantages – slow and not suitable
  during design

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Previous Works – Interval Analysis
                        Interval Analysis – Use the
                       interval algebra to get the
Given A and B, such    worst case skew (Harkness et
that Amax ≥ A ≥ Amin   al. TCAD 1992)
Bmax ≥ B ≥ Bmin           Advantages – relatively
Algebra: F = A×B           fast
Interval algebra:         Disadvantages – cannot
                           handle the distributive
Fmax = Amax×Bmax           nature of wire variation
Fmin = Amin×Bmin           reliably

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Our Objective
 Quick estimation of unwanted skew due
  to wire variation
 Applied during clock tree design and
  chip design planning
 Different from post optimization
  analysis, speed is more important
 Good fidelity


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   Wire Width Variation
                              Consider wire width
                               variation only
                                  Smaller than thickness
                                  More sensitive to
                                   process variations
                                  Assume normal
                                   distribution
Wl           Ws       Wu          Can be extended to
 -3 -2 -1 +1 +2 +3           consider thickness or
           68.26%                  other variation
           95.44%
           99.74%
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Problem Formulation
 Inputs: Clock tree (or a partial clock
  tree) T, any sinks v1 and v2 in T, and
  wire width variation distribution
 Output : Skew variation bound between
  sinks v1 and v2
 Delay model: Elmore delay
       Easy to compute
       High fidelity



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  Observation
   Bound of unwanted skew due to wire
    width variation can be found via delay
    driven non-uniform wire sizing


           Rd        w(x) => wire shaping function


           Vs                              Cn
                C0      C1          Cn-1
                L             x      0

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Tree Reduction
                                       A
           A     Estimate skew bound
               B between A and D



               C

           D                           D




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Skew Bound
                               A
        Max-delay wire
        shaping for A
                          Maximum
                          branch load
              K           capacitance
                                        Skew bound =
                                        max delay at A –
                                        min delay at D
Min-delay wire
shaping for D


       Minimum branch      D
       load capacitance

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Delay Function
                                                 C(x) = Total
                w(x)
    Rd                      δ                    downstream
                                                 capacitance
                             y
                                            Cn    r , c: wire
    Vs                                           resistance and
           C0          C1            Cn-1
                                                 capacitance
           L                 x        0          coefficient
                                 L
   Delay t = RdC(L) + r ∫0 C(x)/ w(x) dx
   What is the wire shaping w(x) max/min
    delay?
   Fixing width everywhere except at
    infinitesimal strip at x = z
   dt/dy = Rd (z – δ/2)c δ - r δC(z+ δ/2)/y2
   d2t/dy2 = 2r δ C(z+ δ/2) / y3 > 0
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Properties of Delay Function
   Delay function is convex w.r.t. width
   Maxima occurs at one of the corner points.

       t

      tmax1

      tmax2


              wmin    wmax       Width

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Wire Shaping for Max-delay
                 Rd
                          Wmi           Wmax          CL
                          n
            Vs
                                Switching Point ‘P’
                      L         P              0

Switching point: Rd/(r/wmin) + (L – P) = P + CL/(c wmax)

                                    P       CL/(c wmax)
           Rd/(r/wmin)    L–P


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Wire Shaping for Min-delay
   Wire shaping for min-delay was solved by Chen et al
    (DAC 1996) and Fishburn et al. (IEEE Tran. Circuits and Sys.
    1995)
   The wire shaping is exponential with maximum width
    near the driver and minimum width near the load.


                    Rd

                                                    CL
               Vs




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Wire Shaping for Min-delay with
Branch Loads
   The wire shaping for min-delay with
    branch loads is piecewise exponential.


             Rd

                                             Cn
                                   Ci
                           C1




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   Common Path Resistance

Common Path Resistance          The max and min
                         A       delay wire shaping
                                 depend on upstream
                                 resistance
                                The skew bound
                                 depends on upstream
                     D
                                 resistance



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     Effect of Common Path
     Resistance on Skew Bound
                                  Skew bound - a
Skew
                                   convex function of
Bound
                                   the Rcommon
 Smax1
                                  Skew bound is
 Smax2                             maximum when the
                                   upstream resistance
                                   is either Rmax or Rmin

           Rmin   Rmax
                         Rcommon

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Skew Bound
                                         A
                 Max-delay wire
Max/Min          shaping for A
common                              Maximum
resistance                          branch load
                        K           capacitance




           Min-delay wire
           shaping for D
                                             Skew bound =

                 Minimum branch              max delay at A –
                                     D       min delay at D
                 load capacitance

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Experimental Results on Skew Upper Bound
   Difference of our bound from Monte Carlo
          Closer to zero – tighter bound
          Never less than zero – safer bound




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Experimental Results on Skew Lower Bound
   Difference of our bound from Monte Carlo
                          Closer to zero – tighter bound
                          Never greater than zero – safer bound

                                                                         400

                                                                         350

                                                                         300
      No. of Sinks Pairs




                                                                         250

                                                                         200

                                                                         150

                                                                         100
                                                                          50

                                                                           0
                           -5.1     -4.1     -3.1      -2.1       -1.1     -0.1
                                                                         -50        0.9

                                                    Skew difference

                           Skew difference Between Analytical Bound and Monte Carlo Method
                           Skew difference Between Interval Analysis and Monte Carlo Method
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      Runtime Comparison
            1000000
             100000
                 10000                                  Our Bound
                 1000
Runtime (s)                                             Interval
                  100                                   Analysis
                   10                                   Monte Carlo
                                                        Analysis
                    1
                   0.1
                         r1   r2   r3   r4    r5

                  Benchmark   r1   r2   r3   r4    r5
                  No. of sinks 267 598 862 1903 3100

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Conclusions
   An bound for unwanted skew due to
    wire width variations is found via wire
    shaping analysis
     Min delay wire shaping with branch load
     Max delay wire shaping
     Common path resistance analysis
 The bound is tighter, safer and faster
  compared to interval analysis
 The impact of wire width variation can
  estimated quickly via the bound
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           Thank you!


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