Defect Tolerance for Yield Enhancement by gnj21076

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									         Defect Tolerance
     for Yield Enhancement
      of FPGA Interconnect
Using Fine-grain and Coarse-grain
           Redundancy
             Anthony J. Yu

            August 15, 2005
                     Outline
   Introduction and motivation
   Previous works
   New architectures
     Coarse-grain redundancy (CGR)
     Fine-grain redundancy (FGR)

   Comparisons
   Conclusions


                                      2
        Introduction and Motivation
   Scaling introduces new types
    of defects
   Number of defects expected
    to increase as chip density
    increases
       As a result, chip yield is on the
        decline
   FPGAs are mostly
    interconnect

   To improve yield (and
    revenue), we must tolerate
    multiple interconnect defects


                                            3
General Defect Tolerant Techniques
   Defect-tolerant techniques minimize impact (cost) of
    manufacturing defects

   FPGA defect-tolerance can be loosely categorized into
    three classes:
       Software Redundancy – use CAD tools to map around the
        defects
       Hardware Redundancy – incorporate spare resources to assist
        in defect correction (eg. Spare row/column)
       Run-time Redundancy – protection against transient faults
        such as SEUs (eg. TMR)

                                                                  4
         Previous work – 1 – Xilinx
   Xilinx’s Defect-Tolerant Approach
       Customer (knowingly) purchases “less that perfect” parts


   Customer gives Xilinx configuration bitstream
   Xilinx tests FPGA devices against bitstream
       Sells FPGA parts that “appear” perfect
       Defects avoid the bitstream


   Limitation:
       Chips work only with given bitstream – no changes!

                                                                   5
         Previous work – 2 – Altera
   Altera’s Defect-Tolerant Approach
       Customer purchases “seemingly perfect” parts

   Make defective resources inaccessible to user
   Coarse-grain architecture
       Spare row and column in array (like memories)
   Defective row/column must be bypassed
       Use the spare row/column instead

   Limitation:
       Does not scale well (multiple defects)

                                                        6
                      Objectives
   Problem
       FPGA yield is on decline because of aggressive
        technology scaling
   Important objectives to improve yield:
     Tolerate interconnect defects (dominates area)
     Tolerate multiple defects (future trend)

     Preserve timing (no timing re-verification)

     Fast correction time (production use)



                                                         7
                         Contributions
   New fine-grain redundancy architecture
   Coarse-grain architecture with multiple spare rows and columns

   Detailed evaluation of fine-grain and coarse-grain redundancy
       Area, delay, yield estimates


   Publications:
       Non-redundant architecture paper, at FPT’04
       Fine-grain architecture paper, to appear in FPL’05
       Yield comparison paper, to appear in FPT’05




                                                                     8
Non-redundant Interconnect Switch




   a) Traditional     b) Single-driver   c) High-level Single-driver
  Connection Point   Connection Point        Connection Point



      OLD             MODERN             HIGH-LEVEL
 (bidirectional)     (directional)         MODEL
                                                                       9
         Coarse-grain Redundancy (CGR)
Row Decoder




                                                              Row Decoder
                                                                                                      Defect
                                                                                       Bypassed
                                                                                         Row




              Spare Row
              Fault Free                                                                     Faulty


                           Wire Extensions
                      F. Hatori et al., “Introducing Redundancy in Field Programmable Gate
                       Arrays,” presented at Custom Integrated Circuits Conference, 1993.




                                                                                                               10
              So…what’s wrong with it?
                     Spare Row and Column

        1.2

         1

        0.8
                                                 32x32
Yield




                                                 64x64
        0.6
                                                 128x128
        0.4                                      256x256


        0.2

         0
              1                             10
                     Number of Defects




                                                           11
       Improving yield for CGR –
      Adding Multiple Global Spares
   Add multiple global
    spare to traditional CGR
   Global spares can be
    used to repair any
    defective row/column in
    the array
   Wire extensions are now
    longer



                                      12
Yield Impact of Multiple Global Spares

                   Global Spare Rows+Columns (32x32)

         1.2                                           Baseline
                                                       2 Global
          1                                            4 Global
         0.8
 Yield
         0.6

         0.4

         0.2

          0
               1                                          10
                            Number of Defects

                                                                  13
Increasing Area+Delay Overhead
                    MORE SPARES  MORE MUX
                   OVERHEAD IN EVERY SWITCH
                           ELEMENT




   NO SPARES




                          2 GLOBAL SPARES

                       4 GLOBAL SPARES MAY BE
  1 GLOBAL SPARE           IMPRACTICAL !!!
                                                14
Fine-grain Redundancy (FGR) –
     Avoidance by Shifting

     Spare                 Defect


                      +1             -1
                 +1            -1
                                      -1
                      +1




   a) Original        b) Corrected




                                           15
Implementation Overview

                                    +2 +1 0        omux
                                    -2 -1 0



                                              -2    +2
                                              -1    +1
                                               0     0
              0    0
              +1   -1
              +2   -2


                          -2 -1 0
               imux
                          +2 +1 0




a) Original             b) Defect-tolerant

                                                          16
FGR Switch Element Details
              Defect




Upstream Switch Block   Downstream Switch Block
                                                  17
FGR Implementation Comparison




                                18
        FGR Architectural Summary
   Several implementations of FGR evaluated:
       Implementation with best yield improvement (EM22)
            Area +50%, delay + 20%
       Implementation with lowest yield improvement (EN11)
            Area +35%, delay +25%


   Perfect chips can be sold as interconnect-enhanced
    FPGAs
       Allow router to use spare routing resources (muxes, tracks)
       Gives more routing flexibility
       True area and delay overhead are 10-20% and 5-25%

                                                                      19
Comparison between FGR and CGR
 – FGR Tolerates Tens of Defects
                    Fine-grain Redundancy        CGR
                    (Best Yield Architecture)    32x32
          1.2                                    64x64
           1                                     128x128
                                                 256x256
          0.8
  Yield
          0.6
          0.4
          0.2
           0
                1                  10               100
                             Number of Defects

                                                           20
Estimated Area overhead at equal
          yield (80%)




         * CGR-G1 can only tolerate 1-2 defects
                                                  21
Limitations of Study & Architectures
   FGR
     Does not tolerate defects in the logic
     Cannot tolerate clustered defects

     Requires a detailed fault map

   CGR
     Assumes that all defects can be corrected with a
      single row/column
     Bypass circuitry is approximated



                                                         22
                  Conclusions
   CGR is effective for 1 or 2 defects
   FGR meets desired objectives:
     Tolerates multiple randomly distributed defects
     Defect correction does not perturb timing
     Tolerates an increasing number of defects as array
      size increases
     Correction can be applied quickly

   FGR potentially capable of correcting
    crosstalk faults, but is not explored in thesis

                                                       23
                        Contributions
   New fine-grain redundancy architecture
   Coarse-grain architecture with multiple spare rows and columns

   Detailed evaluation of fine-grain and coarse-grain redundancy
       Detailed circuit-level design  improved area, delay estimates
       Yield comparison


   Publications:
       Non-redundant architecture paper, at FPT’04
       Fine-grain architecture paper, to appear in FPL’05
       Yield comparison paper, to appear in FPT’05



                                                                         24
Thank you!


anthonyy@ece.ubc.ca
         Improving yield for CGR –
        Adding Multiple Local Spares
   Divide FPGA into subdivisions

   Each subdivision has local
    spare(s)

   Distributes spares across chip
       Reduces mux area overhead
        (of Global scheme)

   Limitation:
       Spare(s) can only repair defect
        within the subdivision


                                          26
Yield Impact of Multiple Local Spares
  (not as good as Global with same # spares)

                   Local Spare Rows+Columns (32x32)
                                                      Baseline
         1.2                                          2 Global
          1                                           4 Global
                                                      2 Sub, 1 Spare
         0.8
 Yield                                                4 Sub, 1 Spare
         0.6

         0.4

         0.2

          0
               1                                            10
                            Number of Defects

                                                                       27
                         Summary
   As the density of FPGAs increase, they become increasingly
    susceptible to manufacturing defects
   Defect-tolerant techniques alleviate this growing problem
   Depending on the desired level of protection, we can apply
    different techniques

   At low defect rates, the coarse-grain spare row and column
    approach has lower overhead than the fine-grain approach

   At the same area overhead, the fine-grain approach can tolerate
    more defects than the spare row and column approach


                                                                      28

								
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