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METHODS FOR MEMORY TEsnNG
by
ling Plaisted
A project
sulJmiued in partial fulfillment
of tile requirements for tile degree of
Master ofSeienee in Engineering, Electrical Engineering
Boise State University
October. 2003
The proje<:t presented by ling Plaisted entitled Methods for Memory
Tcsting is hereby approved:
Conumttcc Member
Commincc Mernbef
. t1..,.1""!.L1!.l]~jL:6.'!.:fJ..9-
G~:e~~ Date
"
.
ACKQWLEOGEMENT
1 ....1>U1d like 10 5incn'Cly ltwIk Dr. Baker for tw guidance. ~ and
alllbc 5UppOrt throughout tlu5 pro;eet. 1 also like 10 thank Dr. Hartman, Dr.
Smith for !heir $UppOf1 and bctp. My special thanb go 10 Albertson Libory sWT
for providing lbc materials that I need in timely manner. I..a5t but IlOI kast. I lite
10 thank Kent. Ben. and Johnny for their help and time.
'"
TABl.E OF COl'.'TE!'ITS
APPROVAl. PAGE .ii
A aN 0 W LEDGMENTS iii
INfRODUCrtON 1
Why Do Memories Need To Be Tested? I
Current Test Status_ 1
TEST DEFINITIONS 4
Quality Measure Slafldanl....•..................•...................•....................•••.......................••••. 4
De(eclS .•.•.•..............................•••.•..........•.•.....................••.•.•.•........•.......... 4
Faults....•....•.•.....•...._.......••.................••...................•••.•.................••.•....................••••.. 4
...................••••..••....... _.................•......... S
Fault CO,·enogc __.....................••••................. _
Failures.......................................•••........................................•..•••................................ S
Fault Models . __ 6
Stuck·at Fault Model __ 6
Delay Fault Models _ 8
TESTING TYPES _ 9
Funcllonal TesI _ ......................•...................... _
_ 9
Stn.ICtuni Test _.._ _ 9
CombinatlOna1 Test _ 9
ScqlKl\liai Test 10
TEST EQUIPMENT AA'D TEST PROGRAM _ 11
'"
.
.._
Automaled Test Equipment (ATEl ....•..••.............._ .......•.....•.•........_ ....••.•••.. _ 12
Automated Test Pattern Genention (ATPG) 13
Pseudorandom Test Generation 13
Detcnninistic Test Generation 14
BOUNDARY SCAN TEST 15
Boundary Scan Test MotIvations ···· 15
Boundary Sun Components and Tbetr Funetions 16
Boundary Scan Cell 18
Boundary Scan Architecture 19
Boundary ScM Applications 20
TCSling T001$ ....._...........••••.......•...........•••.....................•••........................•.••................ 2\
IDDQ TEST MEllIOOOLOGY _•......................... 23
IPIIQ Tesl. 23
The N~ of IDDQ Testing and its Shortcomings · 24
lOOQ Test Moods and Methods 26
looo Test Methods _ __ 26
IODQ Deslgn Concerns _ 21
IDOQ Otallenges and Future T rends 27
BUllT-IN_SElF _TEST (BIST) 29
BIST Advantages and Disadvantages 29
Testing T ype:s and Algorithms ..
_ __ 31
Testing Types _ 31
Testing Algonthrn.s 31
,
o
BIST Applications __ _ _ 32
BlST Design COncmlS - 33
SUM.MARY _ _ _ )S
REFERENCES __ 36
1
INTRODUCfJON
\Vh)' Do Memories Need To Be TCSlcd?
Many scientists and engincen; are striving to decrease the die size and lower the
development cost so thatlhe semiconductor industries arc able to increase their
productivity and profits_ With Integrated Circuits (IC)'s size shrinking smaller and
smaller and impmved layout topologies. more condensed memory armY'S are assigned to
much smaller chip area, it becomes more challenging to test memory devices, soch as,
flash, DRAMs, SRAMs, embedded memories, and other eritical memories for high defect
coverage and stuck-at faults. In order 10 maintain excellent product quality, to achieve
high stalldard reliability, and to meet customers' satisfaction, many advanced test
methods have been developed or are under development The basis fOT these efforts arc
to meet the roquirements of consuming less time to perform tests at different levels and
have higher defect or fault coverage. This paper will provide an overview of some
eurren! memory test techniques.
Current Test Status
Design-for-test (DFT) is strongly emphasized in the semiconductor industry
because it ean contribute to a major portion of reducing the overall product cost. The
goals of reducing test cost include: decreasing test time, simpler test steps, and less
testing data (a.k.a. data vectors) need be applied and generated. Therefore, tel/ability is
one of the major corocems when a device is under design. The contemporary testing is
2
mainly focusing on functional testing in order to detect (aulls thai arC caused during the
processing. [n some cases, the scan techniques and Automatic Test Patterns Generation
(ATPG) are used together to achieve higher fault coverage. Currently, the memory testing
tedmiques thai are used in the mdustry are IDlIQ test, which is currenl based measurement
lest, boundary scan test, Built-in-Self-tesl (BISl), and other voltage based measurement
tests. The tests may be performed on different hierarchy levels, which depend on a
customer's specification. If onc test method has lower defect coverage. a combination of
dilTerenllesllcchniqucs may be applied on the device under test (OUT) to achieve a
higher percentage of detecting defects and faults. Many materials and concepts that are
present in this paper are leamed from [Crouch] and [KJenke98] unless they are specified
otherwise. The remaining sections of this paper are organized in the following order:
• Chapter two will cover some of the test definilions, including defects, faults, fault
coverage, fault models, and failures.
• Chapter three introduces different types of testing, functionaltesl, structural test,
combinational test, and sequential test along with their models_
• Chapter four will cover testing equipment and testing programs including
Automatic Test Equipment (ATE) and ATPG.
• Chapter five will discuss the boundary scan test technique and its applications in a
detailed level.
• Chapter si~ will introduce the quiescent CUTTent (IOOQ) based testing technique and
compare it to other testing techniques.
• Chapter seven will coveT BlST, including its advantages and disadvantages,
applications and some of the design concerns.
3
• ChaptCf eight ....i ll summarize the testing techniques thaI are discussed in this
paper, !he testing problems, design ~ggestions. and !he future Imld for tcsting.
t
TEST DEFINITIONS
The hasic rationale of testing is to check whether the device under test (DUT)
including chips, pnnted circuit boards (PCB), and system can produce expectoo results
when known inputs or "input stimuli" arc applied. In general, a simple test program will
produce results like "pass" or "fail," while a more advanced testing procedure will not
only verify DUTs pass or fail, but also detennine the type of defects or faults, and report
their locations. This information is important when repair is needed. [fthe defects or
faults happen in a pattern, then it indicates an improvement in the process is necessary
[Chen200I].
Quallt}· Measure Standard
Defects
The physical flaws that occur HI the chip are called defects_ In a CMOS process,
Shorts between two terminals, gate oxide shorts or pinholes, and metal trace shorts or
opens arc considered defects [Klenke98] and [Sidorowicz2002]. These defects can
usually be identified with functional testing, which will be discussed in ncxt chapter.
A fault is a logic error that is caused by a defect and can be modeled by a fault
model. Many defects may exist in a circuit, hut only some of these dcfects result in a
fault. There are many possihilities that can trigger faults in a circuit. Fig. 1 illustrates
potential areas that can cause faults.
,
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Extent
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Figure 1 Areas Ihm can cause faults (Ref: [Klenke98])
Fault Coverage
Faul! coverdge is defined as the ralio of the detected faults to the lolal fault
amount. One must be careful when determining the raul! coverage because the total fault
can he different depending on the circuit design and testing tools. Some designs may
only COveT a certain number of faults, in Ihis case, the relative fault coverage (using total
detectahle fault as lolal fault) is higher than the absolute fault coverage (using all possible
faults as total fault).
Failures
II may not always cause a failure when a defe<;t is found in a chip by a fault model.
A failure should obtain the characteristics, such Ilial the fault model can evaluate th.e fault
and provide ajudging standard for determining a failure.
6
Fault Model!
The frequently used fault models include: stuck-at faults, stuck-opcn faults,
bridging faults, delay faults (transition fault), and pattern-sensitivity faults in dynamic
memories [Klenke98], [Sidomwicz2002]. The examples often seen in a circuit are stuck-
3t-0 (a signal tied to ground) and stuck-at-] (a signal lied to VOD or power).
Sluck-at Fault Model
There are many types of stuck-at fault models. We will focus on the single sroek-
at faull model and muhiple stuck-at fault model.
Single Slllck-al Fault model
There are some assumptions fOT using lhis model:
• Only one fault exists at a lime.
• The faul! is stable,
• The faull is either sillclr::-al-O or stuck-at-\.
• The gate function should be predictable whell the fault exists_
In order to delect a single stuck-al fault, cenain conditions need 10 be satisfied
before using the general steps of the model. The conditions to be satisfied include the
testing node be ohserved, and a "golden board" is available to compare the tested results
to the "ideal" or expected results. Some of the manufacturing industries have heen using
"golden board" as part of their normal procedure at the tesling stage. The node to be
tested is made active by pUlling restrictions on all the other nodes' value that can affect
the output. The input stimuli - all possible combinations of logic "O"s and "l"s are
7
applied lO the Dlrr. A fault is detected when the output and cltp<x:led values or IOgil; are
different.
A simple example would be an inverter in a digital circuit. If input X is stuck-at
logic 0, then the oulpul Y will alwllY1 produce the same output, logic 1, even when a I is
applied to X. The correct result appear.; when X ., 0 hut incorrect when X., I. [(tile
input is stuck-at logic I, then the output Y will always produce me same logic 0 even
when 0 is applied to X. The output is correcl when X - 0 and inrorrccl when X" J.
Laslly, if the outpul Y is stuck-atlogie 0 or I, then the oulpul of the inverler will be logic
o or I, respectively, no maller what the input is.
There are many advantages of using the single stuck-at fault model: The model is
easy to use wilh. well developed algorithms and fault simulation; higher defect coverage-
about 90"10 of defects in a CMOS process can be achieved; stuck-open or shorts can bc
"mapped" to single stuck-at fault model. Because of these reasons, the single stuck-at
fault model is well accepted in testing digital CIrcuitry.
Although this model can delect a high percentage of defects, the drdwbaek of this
model is thaI it is not able to cover defects one hUlldred pereC1lt of the time iflhe logic
has multiple stuck-at faults or iflhe fault is transIent. Therefore, multiple stuck-at fault
models have becn developed to overcome part of the problem.
Multiple Stuck-at Fault Model
The assumptions 10 use multiple stuck-at fault model are similar to that of single
stuck-al fault model, except thaI the faults are multiple inslead of only one in the DUT
Although lhis model has higher defect coverage when it is used together with the single
stuck-at fault model, Ihere arc many drawbacks of this model. The model is not well
I
8
developed due 10 the fact thallhe defect coverage does not increase dramatically and it is
a much more complicated testing technique.
Delay Fault Models
The cOllditions to use a delay fault models are thai the logic function of a testing
device is coTTed and the delay caused by inconsistent processing exceeds the specified
value. The transition delay and path delay fault models are commonly used for the delay
fault model.
The Transition Delay Fault Model
The transition delay model (a.k.a. gale delay fault model), is a timing fault model.
Il is used 10 detect a single gale delay by applying the Slow-lo-rise or slow·lo-fall signal
to the input. The transition delay fault is detected when lhe time from input to output
surpasses the defined value. Iflhe delay is long enough. it can be modeled as ajustificd
vcrnion orlbe single-stuck-at faull model.
The Path Delay Faull Model
The path delay fault model is used to determine the total delay of a definite circuit
path in combinational circuitry. The analyzed objective for this model is the path through
multiple gates rather than a single gate when compared to the transient delay model. The
benefit of using this model is that it can detect multiple gate delay faults along the path,
as the model's name indicates. Then again, the trade ofT is that the test can be more
complicated since there are many paths from point A to point B in a complex circuit.
•
,
TESTING TYPES
Functional Test
Conducting a functional test is 10 ch«k if a device's designed functiOIl mcets the
desired specification. To achieve this goal, a set of known inputs are applied \0 evaluate
the output al the gate level or behavioral level of tile design. The standard requiremCllt
for functionaltcst is 100% accuracy.
Structural Test
The purpose of the structural test is 10 check the cllips' topology correctness at
gate-level. The stuck-at faull model is used (0 conduct this kind of lest. An e~arnple
would be forcing an opposite value on a stuck-at fault suspicious node (apply a 0 when it
is stuck-at-] fault), and then switching the inputs to such a value that the circuit would
produce the correct output. This lest can detecllhe faul! point whcnlhe circuit fails to
yield the correct output if the appropriate inputs are applied. Iligh fault coverage (950/.-
99.9"10) is ell:pected in the semiconductor industry_
Combinational Test
The Combinational Test is used to check .f1he circuit can produce the correct
result when all possible input combinations (if the deviee has N input, then the total
possible input combination is 2N) are applied to the DlIT. This test is normally
perfonned in order to characterize a logic circuit for "timing Or logic operation'"
.
10
Sequential Test
The Sequential Test is the combination testing ofsequential clements and
combinational circuit test. This lest is onc orlhe most difficult to conduct, as well as,
time consuming because the sequential stales are embedded within the circuit Even
when applying all the exhaustive testing inputs 10 the circuit it will not be slIccessful
enough to generate a full coverage oflhe output. A circuit with an M element state
machine and N inputs will require as many as 2(101+1') tests. A better solution to this
complicated test is to use the sclln technique or ATPG algorithm, which will be covered
in more depth in the second section nflhe next chapler.
II
TEST EQUIPMENT AND TEST PROGRAM
The test equipment (or tester) and test programs vary depending upon the variety
of the memory and quality requirements. The trade orrfor the sophisticated testers,
normally performed by trained enginef<rs, is between degree of operational difficulty, and
high fault ooverage. On the other hand, memory diagnostic software is inexpensive;
therefore it offers a lower 0051 testing tool oplion. Its purpose is to generate test patterns
to detect potential problems during memory testing. The major problem with using the
software is the possibility that it willoot function properly or may evclJ become
meffective when a falal memory fault or failure c:<.iSlS in the DUT (device under Icst). In
shon, the goal is to use a simpler and faster tester with demonstrated cost-effectiveness,
and most imponantly, to catch the maximum amounl of memory faults and defects.
Automated Ted E:quipmenl (ATE:l
As previously mentioned, both hardware and software can be used to lest memory
chips, boards, and systems. In general, Automated Test Equipments (ATE) are used to
test memory chips dunng their linal process. However. the hardware memory tester is
more difficult to build into the testcr because of its complexity and various tcst
Characteristics. This is the main reason why thc high-end ATE can cost a million dollars
or more. Micron is One of the companies in ofthc semiconductor industry, which utilizes
the ATE for testing mcmories_
12
The three components orthe integrated Circuit ATE are shown in Fig. 2:
numerous "channels with memory depth;' multiple clock gellCT1ltoTS, and multiple power
supplies.
"'""",.
'"
Figure 2 ATE components (Ref: [Crouch])
The cost for ATE is dependent on the size orlhe memory being tcsted, process
uSllge, and the precision oCthe results. The cltpense for ATE increases when testing the
larger size memory due 10 considerable amOUI\! ofvcclors that need to be generated and
the circuitry is more complicated. AJ; we expect. lower usage afthe ATE will increase
overall testing COS! per unit There are many ways to reduce the ATE OOSt, such as,
making the testing program Simpler, usillg smaller vectors which can also reduce the
testing time.
13
Automatic Test Paltero Generation (ATPG)
If the memory cireuit is considerably large and complicated, the use of Automatic
test pattern generation (ATPO), 10 generate the test vectors, is essential In order to
achieve high fault coverage since it is nOl praclicallo manually apply all the test vectors.
The main techniques used in the A TPG to detect the sluck-at faults are
pseudorandom and dctcnninistic lest generation. In addition, algorithms that are used
include: ad hoc, D algorithm, PODEM, and olhers.
Pseudorandom Test Generation
When the probability of identifying any detectable faulls is the same, then it is
called a pseudorandom lesl generator. The pseudorandom test generation is usually
conducted at the beginning of the lest and is used to detect "easy-lo-dclecC faults. The
pseudorandom tcst is efficient because it has fairly good fault coveragc (nearly one-
hundred perecllt) usillg smallcr test vecton;. A Linear Feedback Shin Register (LFSR) is
used to gencratc Ihe pseudorandom palters.
--------------------------------------~------_.
•
•
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•
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•
o jo
•
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Figure 3 Pseudorandom fault coverage (Ref: (Klenke98j)
7
14
Fig. J shows that fault coverage will nO longer increase significantly when the;:
quantity oftest vectors reaches a certain level (pseudorandom testing can not detect allY
additional expected faulls while increasing the number of lest vectors)_ This is where the
deterministic ATPG is needed to detect the rest of the expected faults.
Deterministic Test Generation
The detcnninistic lest is defilled as the repeatable response of the unit·under-tesl.
The deterministic test generation IS used ill order [0 achieve higher fault ooverage since
the pseudorandom test can not cover all possible faults. A5 a result, the manufacturers
compromise chip area (more overhead) and the related excessive cost for the higher
product quality and reliability [BI5T of Memory).
BOUNDARY SCANTEST
A successful test design basically has three criterions, high quality, quick results,
and desirable economics. To achieve these goals, the Joint Test Action Group (lTAG)
was formed in late 80's. The group of professionals, who came from circuits and
electronics product manufacturing and test engineering fields, defined four wire test bus
that are required for boundary scan architecture [Gopel electronic] and a optional
common asynchronous reset signal [1149.1-2001]. The resuh of their work became the
industry standard. also known as IEEE Std 1149.1.
Boundary Scan Test l\1otivation~
Boundary scan architecture became IEEE Std 1149.1 10 1990 in order for the test
bus to be utilized effectively as a universal lest platfonn [Oopel electronic]. With the
increased usa8e of Ball·Grid-Array (BGA) packaging and other newly developing
packaging styles, it become more challenging to access c.ach component for testing,
therefore. boundary-scan became well accepted for board manufacturing testing
[Wondolowski99]. Sioce IEEE 1149.\ was published, a few extensions have bttn
developed and released, namely, IEEE 1149.I-b, IEEE Std 1149.4, used for analog
testing, and IEEE Std 1149.5, used for testing at system level [Gopcl electronic].
Boundary scan made it possible to use the same test for dilTerem boards or at the
difTcrentlevels if the device is scan capable [Wondolowski99J. It makes the higher level
testing more efficient, yet less costly, since it is now possible to skip testing the ''bug-
free" boundary scan portion instead of building a much more complicated test fixture to
16
cover every segmCIlt. The ability 10 acceSs 1'01 (boundary scan test data in) and TOO
(boundary scan lcst data oul) is highly valuable because the functional tests and
debugging can be conducted in an easier way now. Another benefit of using boundary
scan is that it made the difficult testing tasks easier to handle in a software form
[Boundary Scan]. The Boundary scan test can still be more efficient, even when a board
contains some non-boundary scan logic, since the software is able III facilitate the testers
to access them via boundary scan cell.
However, like oth~'f testing techniques, boundary scan is not perfcct since Ihe area,
speed, and tcsting overheads are necessary for the lest design and these elements can
slow down the speed and mcrease the chip area.
Bouodal"}' Scan Cumponcuu and Their Functions
Originally, boundary scan was designed to lest the chip and extend its test
availability to the next integrated cin;uitlcvel so the ATE can be used repeatedly at
difTcrem levels. The Boundary scan te<:hnique provides overall "conlrol and access to the
boundary pins," eliminating the requiremem of the bed-of-nails Or other testing
equipment (Gopel electronic). as shown in Fig. 4.
Figure 4 Boundary scan transforms the physical piru; 10 ··electronic nails" (Ref: (Gopel
electromc])
17
The basic lxIundary-scan structure includes shift-register, which is positioned in a
scan cell and next to the physical pins so that the signals can be slored and tested at the
boundary([Rcf: 1149.1-2001]).
The boundary-scan lest logic consists oflhree parts: the test access port (TAP)
controller, the instruction register, and the data register. The TAP controller, a H,-state
finite stale machine (FSM), see l'ig.5.2, is used to generale the clock and 10 select the
correct signals. The state machine changes states only at the rising or falling clock edge.
The control signal for state transition is the lest mode signal (fMS). 'The instruction
register functions as the decision matrix, and gives direction on corresponding steps
based on stored instructions. Series ofinpul stimulus are stored in the data registers then
executed based On the operation commands.
.
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Figure 5 TAP controller stale machine diagram (Ref: [1149.1-2001])
80undary Scan Cell
Fig. 6 shows an exantple of a boundary scan cell. Every bouudary scan device
consists of one or more boundary sean cells. The most common modes used 1Il a cell are:
nonnal mode, sean mode, caplure mode, and update mode. The control signal, MODE
Control, selects the functional mode or test mode according to the operating instruction
but not both at the same time. Il is called llOnnal mode when the functional mode is
selected and the input signals simply pass through. The scan mode is whCTI Shift DR
selects SIN, SIN (Scan IN) goes to QA thCTI to SOUT (Scan OUT). If Shift DR selects
IN, then QA gets the value of IN, whieh complete the capture mode. Under the update
mode, OUT gets the value ofQA.
~
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Figure 6 An example ofa boundary scan cell (Ref: [Klenke9glJ
The connections between scan cells can be serial or parallel or a mixture of the
two. 1l is considered a serial connection as shown in Fig.7. if TOO and TO! arc tied
together as a chain. The advantage of the serial connection is lhal less chip area is needed.
For pardUel conncction, the benefit is that it can increase the circuit reliability if the
---- - - .. _--
19
design is structured so the system can still work properly, even when I dcrox:tivc scan cell
exists somcwbcre in I cIrcuit. Another advanllgc of panlllci eonnection is WI il.lloW$
the deb\lgging and fault analysis 10 be perfonned during oormaI opc:nlion [1149.1-2001 J.
1be b"Idc offs for having high rcliabillly is that UlOl"l' chip area is JM'll"6ed, Oll)f'e
eomplicaled designs are required, and the ioc~ bwdaI au ICSl de$ign mgincas
IBounlbly Sean I-
Figure 7 An example OfOOlindary scan cell serial connection (Ref: [Gapel electronic]).
Boundary 5(10 ArcbitKtUR
Fig..8 shows a chip containing boundary scan an:hitIXture and the <::onneclio11S of
the four-wire lc:sI bus., TCK. TMS. TOl and 100. Otba ICSUIlg techniques, such u,
BIST may be used as well in the same chip. In [1149.1-2001). the pIlfpll$e$ of these lest
bus are as follow:
• TCK is lhe lest clock; it is used in TAP controller and Olhel'" registers
• TMS is the test mod<: select; it controls TAP controller's 5lalc machine.
• TDI is the Icst instruction and dala input.
20
• TOO is the sai.lle$!. data and instructions output; TOI and TOO are not
acti~·e at the 5aIDe lime since TOI is updated.t TeK'I rising edge and TOO 15
updaIed aI TCK', falling edge.
• TRST. a common asynchronous reset, is optional to extend the arehitccturc
[1149.1-200 11.
Figure 8 An:hitceture of a boundary scan capable chip (Ref; [KJenke98)
Boundary Sun Applications
Since 1149.\ became: the: standard. it made lC$ling easier at these dilTCTmt levels:
components (or chips), modules. PC&.. and 1)'Stefl1$. Tbis is unponalll btt,"selOlDe
modules and PCBs, in nany cases, need to be intc:gnled 'A,th other boards 10 make.
system level pmdUCl In Wondolowsti, Bametts. and Lay's ~I\,!heyexplomllhe
11
method known as "daisy-£hain" (daisy stands for data acquisition and interpretation
system). "Daisy-chain" refers to a connection between the TDO of one boundary scan
capable device to the TO! of another in a hierarchy siruclllre. The first device and the last
device are placed in an area that allows easy access to the higher level testing. For
e~ample, in Fig.9, the upper right comer is connected to the serial data input and the
lower right comer logic is connected to the serial data output.
......."
"",n cell
Figure 9 Boundary scan design in board level (Ref: [Klenke98) and [1149.1-2001 J)
Testing Tools
The optimum testing tOQls are those that arc capable of use with a maximum
nwnber of products in order \0 reduce the overall manufacturing cost. However, this is
not possible in every instance, especially when a new testing technology is introduced
into a manufacturing environment and because some vendors cannot provide boundary
scan compliant products as tile system demands. In addition, if tile test vectors can be
12
generated automatically, the tests are more user friendly. Therefore, some software is
used 10 lest the product combined with the use ofb<:lundary scan. This makes the lest
efficient by allowing access to the non-scan devices via the boundary scan celL
7
23
IDDQ TEST METHODOLOGY
100Q teSting technique is. methodology 10 deteel faults and defcets with quiescent
CUJTmls at the transistor level in CMOS devices. In Ibis chapta:,1DDQ testing and its
perspectives will be discussed. The chapler will discuss some of the design issues and
{ullin: testing development with this unique technique.
IDOQ Test
The main difference between lOOQ testing and voltage-measurement based circuit
testing methodoklgy is thaI the lOOQ test is based on current measurement. The faulty
~. quiescent ClUT'alllnerea5CS 5e\'e:r:aI orden of magnitude ~ to a defect-
free device, therefore the defeet is able to be detected This technique assumes that the
faull-free CMOS circuit consumes very little current (lhe range is within fA) in the lalie
state. 100Q testing became one ofttle well de\-eloped and ubiquitous currm( based
techniques.
-
-
Figure 10 Quiescent CUfTml sho..-s physical defect effect (Ref: [1UenJ;:c9SJ)
· - . . --
24
An example of using lD[lQ testing 10 delect a gale-source shon, in the PMOS of an
inverter is shown in Fig.IO. 1000 increases significantly compared to lhe defect-frec
device. When lhe input voltage changes from high 10 low, the PMOS lurns on and pulls
the output voltage to high. IOOQcould increase sevenll orders of magnitude because the
short enables the current to now from source to gale. We lIOtke that whether this
particular defecl exists or not, the output voltage is high for bolh cases. However, the
1000 test can dcternline this defect while the voltage measurement method docs not. It
gives the impression this is oot as critical al first glance since the defect does oot affect
the iovcrters function. In fact, the ability to detect lhis kind of defect is important because
the defed could seriously degrade lhe product reliability, and consequently, cause a
failure in thc future.
The Need of 1[}l>Q Testing and Its Shortcomings
The lOOQ tcst presents a number of benefits. First, 100Q can detect many defects in
the CMOS eircuil, that many other methods cannot, such as bridging faults. gale oxide
defects, shorts, some delay faults, and somc open faults [Rajsuman2000]. These defects
can cause thc current 10 increase dramatically (sevenll orders of magnitude) compared 10
quiescent current. For example, 1000 CaIl detect source-gate shons as mentioned before,
bmthe stuck-at fault would not delect this defect. Ho"-'ever, this method cannot detect
some of the open faults depending 011 the circuit design [RajsumanlOOOJ.
Another benefit of 1000 is thaI lhis current-based measurcmC1lt is elTective
because all of the nodes in a circuit are observable but not necessarily all controllable so
that the fault is ·'activated." Therefore, the defect is evident and, as a result, the fault can
be detected without the requiremcnt of propagation.
Iow-cost, hip quality, suppkmenlal lC'S!" [RajIUlIWl2OOOJ.
Fig. II shows that using loooean achieve high fault COVer1lge with a low number
of vectors (leu than 20 in the case of bridge faults).
rv---\-::_:-'<-- -
•
•
·
:.
· -
.-- --
·.,•
•
. .
·,
•
• • •
Figure II 1000 &ult C(lva1lge V$.. \~ number (Ref: (Klenke9g])
Like other testing techniques, 1000 has some negative sides as well. Since the ltsl
is based on a very small amount of current, during lhc test. the DUTs must be in a steady
state for evaluation to satisfy the basic condition - quiescent CUlTC11l. Therefore, any pull-
up oc pull-down logic. and RAM sense amplifiers in the design. can grady decrease the
fault detection sensitivity.
Aoo!ber downside of the 1000 lwing is !hat il is lime COl'ISuming SInce accurate
results can nOt be obtained until the cin:uit is $tilled to ils steady Slate aftcr the input
Slimulus is applied, Consequently, this technique is oot a good applicant for at-speed
testing.
It is diflkultto set the 1000 cWTeotlimiwion to II certain value for all OUTs as
the 1000 thte$hold can vary depending upon the design and pro<:ess. In lIddition, high
"
precision measurements are required for 100Q testing since the leakage current is very low,
therefore, lIIc signal 10 noise I1Ilio (SNR) is vcry low as well.
IODQ T6t Moods and MEthods
'Then: arc many models used in [00010 ddect il variety of faults, befe are some
models often seen in the lest.
• Stuck-at fault mockl: 10 detect a fault by fon:ing the opposite VlIIluc ofituck-at
raul! al defective node. Using this model is able to Iktc:cl bridgIng fault
(Raj~OOO).
• TraR$I$lOr short model: A eenain pattern ofinpuu are applied for detectUlg 5hofu
between lhc terminals.
• Bridging fault model: FOf'Cing 1\1;"(1 opposite values at the 1 nodes in orda 10
.....0
detect shorts bmoo'ttfI these 1\li0 adjacent nodes.
lpoo Tcs Metbods
Dltrel'ml 1000 IllC'Ihods along with othu testing techniques, 5llcllas \'01u.ge-bascd
measurements, are used In order to achieve the optimal results and minimixe thcir
dlgdvanllgc:s. 1lle target applicant for Meo,'ay vector IDDQ" leSling. which will perfonn
1000 lest after every vector is applied to lhe input, is normally a prototype device. In
otha ClISe$, "$elective 'OOlt testing. which only uses a portiOll aCthe ,,«ton instead of
every one. is an efTc:divc method to detect the majority of the faults. "Supplemental
'000;,' lest is used, in addition to voltage based lesting lechniques, ""hen ··full-speed
funclional tests" are conducted_
21
II}()Q Oesign Concerns
Some oflhe important factors, which will determine lOOQ testability, need 10 be
considered when designing an 100Q test arc:
• Conlcmion current should be avoided in the design since the test is based on
Ihe quiescent current. Moreover, no floating nodes should be present in the
testing circuit
• If current sources or sinks and sense amps are necessary for the circuit, then
the use of a different power supply from the testing circuit may prevent them
from affccting the testability.
• Any dynamic nodes should be fully charged or discharged on each clock cycle.
• A switch or controller is highly recommended for shuning any wmeccs.sary
stalic current (Rajsuman2000).
• Disable any free running oscillators during lhe (cst as Ihey can draw a certain
amount orthe currenl.
II)DQ Challenges and Future Trends
Seuing the 1000 thrcsl10ld becomes more challenging as transistor size shrinks
smaller and smaller and it also can be a factor in causing the lOOQ values to vary.
Therefore, it is eriticalto identify tbe elements that will cause [OOQ to nuetuate. For
example, temperature, voltage, and other parameters can vary the lOOQ values.
The testing time can be long sioce a period of time is needed before the circuit
settles into a steady state. 100Q testing remains problematic if a eircuilunder test CQntains
non·CMOS devices since it is designed based on CMOS leakage current.
28
There are many areas in lOOQ testing that slilloeed to be improved, particularly,
the delay fault and using IDDQa5 an analysis tool.
29
BUILT-IN-SELF-TEST (BIST)
With memory size on the increase. the complexity and testing time rise as well.
This mear1$WI the cost crlesting goes up and. as a result, the products ovenll costs rise
100. II becomes Il'lOfe and more challenging 10 perform the pecnnry lcSlS outside the
circuit when thete is DO ph)'5ical pin 10 xcc:u the integra10d circuit memory, for example,
circuits in embedded memory. To cru;urc: those memories' quality and reliability. il built·
in-self4eSl (915T) circuit is added internally \0 test Ihe circuit. [n addition to detecting
faults and defects, BiST is able to supply the failure dala for the defect types and their
loca!iOllS for analysis and repair. This information is important because the testing rcsulu
can help detmnine if the ewteI'Il process has problem or iflhe defects can be eliminllled
in the future.
B1ST Advallt~ge5 and Disadvantages
There are many advantages for using 81ST. The testing cost can be reduced
because It docs IlOl require the expcnsi~'e automatic Ie$l.ing equipmml (ATE). The fault
covenge increases siflCe il a1~'1 muluple lescing - inkmll and extemaltes15 are
perfonned al1hc same time. The on-lille B1ST allows perfonning the lest while the
normal operation is In process or conducts ofT-line BIST when the system is under the
diagnosis tem. Testing lime, one of the key oontribulOB to cost, will be reduced due 10
the posIlibdllyof running the lest simultanrously if the memory is di\·ided Into $eVen!
banks. Sux:c: the manory chips are abo integrated onto boan.b and systems, 51ST can be
conducted at each l~·el.
30
The ~nefit of using 81ST in high-dcllsily memories can he extended ifil is
associated wilh Built-in-self-rcpair (BISR). The reason fOT this is whenever random
failures and their locations are found in a hit, 81SR is able 10 replace the defective bit
wilh spare rows or columns. However, as we expect, if the failure rate is high, BISR is
no longer practical due to the large amount of extra rows and columns needed.
According 10 PalerM, the Director of Engineering for manufacturing tcst software
al LogieVision Inc., the BJST has some advanced benefits compared to ATPG techniques.
ATPG will normally generate a larger test veclor and pin-Io-pin timing can be very
critical. On the other hand, B1ST does not need to slore testing data, and the timing
restriction is insignificant [Pateras2002].
However, the benefit for adding 8151 to a small memory array is insignificant in
relationship to the high percentage oflhe chip area usage. llccause of this, the BIST ean
seriously degrade the memory circuits operation ifthe controller size and memory array
size are comparable [Boyer2003}. Boyer also indicated, that "all memory input pins have
a multiple:o;:er to select between BIST and system signals and that can lead to routing
congestion." Therefore, the best applicants for adding BIST should be to those cireuits
having large memory size with a minimum number of ports [Boyer2003j.
Other downsides of the BIST are revealed when the memory density is reduced
due to the added circuit; the circuit design will be more complicated as the additional
CircUlt also requires e:o;:tra pins to connect other circuit; the testing speed is possibly
reduced due to the longer testing path and higher overhead of the cireuil.
"
Testing Types and Algorithms
Testing Types
• Exhaustive testing
Exhaustive testing can be time consuming since;1 needs 10 lest all2 N logic
values ifthe device has N inputs. The benefit of exhaustive testing is thaI it is
capable of discovering all detectable faults since all possible combinations of the
input stimulus are applied. On the olher hand, it is not praclicallo conduct
exhaustive testing if N is a large number (>20) due to the enormous test vectors
and the mailer orthe lengthy lest time.
• Pseudo-exhaustive testing
The bellcfit of the pseudO--f:xhaustive testing is that it IISCS fewer test
pauems 10 achieve exhaustive testing results. The overhead is lower than
exhaustive testing.
• Pseudorandom testing
Tes1 pallems are less than IN, or are partial of cxh~ustivc testing. The
characteristic ofpseudor'otndom is the mi:\ture ofrandom and detenninistic.
Linear feedback shift registers (LFSRs) arc used to generate the test panerns.
Testing Algorithms
March Tests
March test is when a sct of test instruction steps (nonnal1y is generated by LFSRs)
are pcrfonned to test each cell of memory array in orner. It is not critical as to wherc the
tcst is staning, at the bonom or at the begirming of the memory array, as long as a
complete test is conducted for each cell before moving to the next one. The test usually
takes 4 to 17 ns to finish per cell [BIST of Memory]. The March test is commonly used
to dete<:t stuck-at faults in both RAM and address decoders on top of all transition faulls
and some coupling faults [OUerstedt98].
Neighborhood Patlem Sensitive Tests fNPSF):
"A NPSF tests every cell of the memory in relation to its set of 5 or 9 neighboring
cells (including the base cell)"". This test takes 195 ns to be completed [BIS1 of
Memory), longer than the march test.
81S1 Application!
BIST is widely applied in various memory circuitries: SRAMs [Tehranipour2(00),
DRAM, flash [Yeh2002]. and emlx:dded memories.
Using BIST in SRAM testing was approved effective in Tehranipour and
Zavabi's paper. They implemented a so called "length 9N test algorithm" to conduct
March testing on SRAM. Their testing method was able to utilize the existing hardware
and soll.ware and the results showed an achievement of 100"/0 fault coverage without
increasing any overhead ITehrampour2002].
Using B1ST for testing embedded memories also showed great advantages simply
be<:ause the memory is very compacted, consequently, the BlST overhead is small in
comparison to the overall memory cireuit [Burgess2000].
Figure 12 shows the block diagram of memory with B[ST. The BIS1 circuitry is
cnlarged for explanatioll purpose. Once a failure is flagged, its address will be seanrted
out for diagnosis [Burgcss2000].
n
- -- ,
II.....·
...
...... -~
Figure 12 Memory with BIST block diagram (Ref: [Burgess2000J)
8151' Design CODeno,
There are many dIfferent designs in which to conduci a BIST. The following are
some conccms when dcslgrnng a BIST so thai each test will meet spec:i1ie goals.
• Faults: We WOlild like I(l mow what faullS lbc lest should delcct. In Olterstodl and
Niggamcya', paper, they usuI modiliod IJW'Ch lest 10 deled addre:u faults,
stuck-a! faults, coupling faults, and transition faults (Oltenk:dr9llJ. The NPSF can
&teet ""the class of Active, Passive, and Sutic Neighborhood Pattern seos;live
faull$, wltic.h includmg stuck-at faults and all coupling trarl$i11Ona1 faults" fBIST
ofMemoryj.
• Time: Timing is always a big issue because the goal is to reduce the le:sllime 10 a
minimum. The bollom line is how much more lime is allowed befon: it slows
down the device significantly.
l4
• Area: How much area should we sacrifice to gain the BIST benefits? For instance,
the small memory arrnys normally do not justify the benefits of the mST because
their high pen:entage of area usage can decrease COTe circuit's performance. The
sizes of the B[ST are varied depending on the purpose of the design.
• Overhead: There are alleast two issues we need to coll5ider for minimizing
overhead when designing a BiST. First of all, the need to detennine which
method is required in order to keep the overhead low, and secondly, what type of
memory is suitable for adding BIST circuit.
• Cost: Since testing expenditure is part of overall product cost, it is critical 10
design a Icst metllod thai is economic but has high performance. Consequently,
the trade oITs between the testing time, the fault covernge, testing method
complexity of each test methods and their costs are need to be considered as well
at the designing stage.
• Others: More advanced techniques, sueh as Automatic Built-in Self~Test (ABIST)
has been developed based on rEEE Sid 1149.1 and its extensions. The goal for
testing in the near future is to apply Electronic Systems Test Automation (E$TA)
when design a Hicran:hical and Integrated BIST (HffilST) where it is possible 10
test the chips all the way [0 the systems.
"
SUMMARY
The intent for this paper is 10 introduce VariOllS testing concepts and to disl:uss
some of the current testing techniques and !heir set of trade olTs. In addItion. some of the
design concerns are addressed in order 10 deal with dilTemll testing needs.
l1lere are many "vanagel5 of using Ibc: boUDdaTy sean testing technique. l1Jc:
boundary JC&II enabled te$ling the same device at differmt levels including: componenu.
PCBs.. and systems. Fwthtt. this method is also able to enhance and support Olbef testing
fCiitures and makes the lesllOg more efflcienl Ho,...: va,!he O\1:rhead CUI become the
hmmog fKIOl'. In gmenl, the design goal is to decrease !he overhead and il"lClQSe clup
usage area .....hile maintain high fault covcnge.
IDOQ IC:Sl showed its unique "\'aIlt.ages---Oetect some ofw dcfecl$, while tDe
"oltage ba$cd tne&$t1ml1ell1 method docs DOl have the AIDC capability. The limitation
when IlSIng IDDQ is thal any dynamic circuit will reduce the 6efec:t detec:tion sensitiVIty.
SInce IllDQ IC$l: is dcsip>cd for CMOS circuit only. it becomes useless"ben non-CMOS
cireults exia in the omS.
Using BIST has been pro,'en beneficial in embedded memory circuits, high
density DRA.\i and other large memory circuits. Mareo"tt, BIST reduces the use of
expensive external ATE. Iloweva-, when BIST is oot designed propcrly, c:spa:iaIly, in
the small memory circUli, lhe advantages disappear. The problem is that Clltr1l O\'erhead
causes complexity, as result resulting in low yield. Then:fore, a BIST design that can
achieve maximum fault coverage, minimum overhead. and more nex;bility are strongly
preferred,
36
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