Timing Yield Enhancement Through Soft-Edge Flip-Flop Based Design by via28446

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									Timing Yield Enhancement Through Soft-Edge
Flip-Flop Based Design
Youngmin Park, Carlos Tokunaga, Michael Wieckowski, Daeyeon W. Kim,
David T. Blaauw, and Dennis M. Sylvester
A finite-impulse-response (FIR) filter and a bank of balanced inverter chains were fabricated
in a 0.13µm CMOS process. The packaged IC’s were analyzed to measure the yield impact
of “soft-edge” flip-flops (SFF) when compared to data flip-flops (DFF).




         SEM image showing non-rectilinear poly gate and diffusion (courtesy TI).

As the device variation inherent to semiconductor manufacturing continues to
increase from such causes as dopant fluctuation and other random sources, the
complexity in CAD analysis for timing closure tends to limit the performance and
yield of ASIC designs. Traditionally, variation tolerant, two-phase, latch-based
designs have been used as a solution to this issue. Alternately, hard-edge data flip-
flops (DFF) with intentional or “useful” skew can be used. Both of these tech-
niques, however, incur a significant penalty in design complexity and clocking
overhead.
In this work, we investigate a new type of soft-edge flip-flop (SFF) that maintains
synchronization at a clock edge, but has a transparency window, or “softness”. Two
finite-impulse-response (FIR) filters and several balanced inverter chains were
fabricated in a 0.13m CMOS process using both DFF and tunable SFF elements.
By measuring the maximum frequency of operation over a large number of IC’s,
the impact of softness on yield could be ascertained. We show that small amounts
of softness achieve improvements in performance of 11.7% over a DFF and 9.2%
when a DFF with useful skew is optimized. These increases in performance can
alternately be interpreted as greater tolerance to intra-die variation. As such, for a
particular timing target, softness can be employed at design-time or tuned after
fabrication to guarantee a particular yield. Continued work on this project is aimed
at gaining some insight into the effect of softness on critical paths in a variation-
constrained pipeline. This project is supported by the Semiconductor Technology
Academic Research Center of Japan.

                                 SSEL Annual Report 2007

								
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