Tutorial I: Technology scaling, multi-gate devices and reliability 1. Scaling challenges and need for multi-gate devices Presenter: Ali Keshavarzi, Intel Abstract: Scaling of CMOS technology continues in spite of tremendous technology development barriers, design challenges and prohibitive costs. Today, the 65nm CMOS technology node is moving from development to high volume manufacturing while research and development continues on future technology nodes including 45nm, 32nm and beyond. However, design of ICs in these scaled technologies faces growing limitations. On the technology front, the question arises whether we can continue along the traditional CMOS scaling path – reduce effective oxide thickness, improve channel mobility, and minimize parasitics. We will try to introduce the challenges associated with scaling of CMOS technology in this tutorial. We will present a case for multi-gate devices to continue the scaling trend. Bio: Ali Keshavarzi received his Ph.D. degree in electrical engineering from Purdue University, West Lafayette, Indiana. He is a senior staff research scientist at Microprocessor Research Laboratories (MRL) of Intel Corporation, Portland, Oregon. He is currently focusing on long-term research in low-power/high-performance circuit techniques and transistor device structures for future generations of microprocessors. Ali has been with Intel for thirteen years, has published more than 20 papers and has more than 30 patents (15 issued and the rest are pending patents). Ali has received the best paper award at 1997 IEEE International Test Conference at Washington, D.C. on testing solutions of intrinsically leaky integrated circuits. Ali is a member of the ISLPED & ISQED technical program committees. Tutorial I: Technology scaling, multi-gate devices and reliability 2. Multi-Gate MOSFET Design Presenter: Gerhard Knoblinger, Infineon Technologies Abstract: Multi-gate MOSFET (MuGFET) e.g. FinFET, TriGate devices are the most promising candidates for beyond 45nm technology CMOS nodes. For future SoC solutions in these technologies the ability to realize digital, analog and RF building blocks is of utmost importance. The tutorial will start with CMOS scaling trends, followed by an example for a typical MuGFET technology and an overview of the available devices. The second part will cover compact modeling of MuGFET devices with special emphasis on self heating effects. We will then discuss the impact of different technology options on the performance of digital circuits and the design and realization of typical analog building blocks, including also measurement results. Furthermore RF circuits realized with MuGFET devices and the most important issues of ESD robustness will be presented. Bio: Gerhard Knoblinger was born in Upper Austria in 1968. He received the Dipl.-Ing. Degree in technical physics from the Technical University of Graz, Austria, in 1996 and the Ph.D. degree from the Universitaet der Bundeswehr, Munich, Germany, in 2001. From 1996 to 1998, he was with the Microelectronics Design Center of Siemens AG Austria, Villach. From 1998 to 2003 he was with the Process and Device Characterization Group of Siemens AG Germany, now Infineon Technologies. In 2003 he moved to the Analog Technology and Exploration department in the Infineon Design Center Villach. His research interests are design and simulation of analog, mixed-signal and RF-CMOS circuits in advanced ultra deep sub-micron CMOS and SOI technologies, high-frequency and noise characterization of deep-submicron CMOS devices, modeling of inductors and varactors. Tutorial I: Technology scaling, multi-gate devices and reliability 3. The challenge of the high-k dielectrics reliability Presenter: Luigi Pantisano, IMEC Abstract: The high-k dielectrics are actively investigated as a replacement for thermally grown SiO2 for sub-1nm equivalent oxide thickness. These high-k materials are commonly deposited on an ultra thin SiO2 and generally feature higher defect densities with respect to the conventional thermally- grown SiO2. Defects may be present in the interfacial SiO2 layer and the bulk of the high-k material itself and may have a severe impact on the reliability of CMOS devices with high-k dielectrics. The challenge in the reliability is how to correctly quantify this impact from an experimental point of view in both the high-k itself and the interfacial SiO2 and the physical mechanisms involved in the degradation. This tutorial will first give a brief overview of the high-k dielectrics and then focus on the reliability problems encountered, like Bias Temperature Instabilities (BTI), Time-to-Dielectric-Breakdown (TDDB), defect creation mechanisms and charge centroid, etc. Experimental tools to determine these quantities will be discussed together with the most recent understanding and development on the subject. Bio: Luigi Pantisano received his MS and PhD in Electrical Engineering from University of Padova in 1997 and 2001, respectively. From 2000 to 2001 Luigi was working at Bell Labs on the plasma damage impact on RF devices. Since 2001 Luigi joined the IMEC Reliability Group as a research scientist working on the reliability and characterization of high-k dielectrics for CMOS applications. Tutorial I: Technology scaling, multi-gate devices and reliability 4. Low-K integration and production - issues and solutions Presenter: Dr. Dorel Toma, Tokyo Electron US Holdings Abstract: Historically, microprocessors migrated from Al/SiO2 interconnect integration schemes to Cu/low- scaled, simple geometric scaling of the Cu/Low-K will become limiting factor of device speed. To minimize the impact of interconnect delay, an introduction of new Ultra Low-K (ULK) materials The new materials being investigated have a high degree of porosity. This presents integration issues due to weak mechanical and chemical characteristics of the film. The issues are compounded by post-deposition processing such as cure, etch, ash, cleaning and others, which induce a degradation of film properties and added complexity in integration. For 32nm technology node and beyond, the conventional processes are unlikely to be sufficient. Innovative solutions are needed to eliminate dielectric degradation and minimize integration concerns. We will present and discuss the influence of different technology paths for creating and integrating new low- - and areas identified with minimum negative effect on the ULK, including methods for process degradation recovery. For completeness, metrology related issues with ULK will be presented. Bio: Dorel completed his MS in Electrical Engineering in 1966 at Polytechnic Institute, Timisoara, Romania, PhD in Applied Physics at Institute of Atomic Physics, Bucharest, Romania in 1987 and numerous scientific studies with the Russian, Chinese, German and Czech Republic Academies of Science in Solid State Physics from 1987 to 1990. He was employed by the Institute of Physics Bucharest – Romania and Institute of Space Research (Intercosmos Program) Moscow Russia from 1987 to 1992 as the Senior Engineer and Divisional Chief of the Department of Quantum Electronics and Microelectronics Materials and Technologies. From 1993 to 1995, He was Director of R&D for Raphael Glass, Plumsteadville, PA. He has worked for Tokyo Electron Limited from 1996 to present. Initially, as the Director of US Back End of Line (BEOL) Process Technology Group, he was coordinating US activities in process and tool development for low-k materials and technologies for integration with Cu/low k integration. Presently, he is Director of the newly created US Technology Development Center where he is responsible for all advanced development technologies for TEL in the US. With more than 25 years experience in Technical Physics and Engineering Research in Material Science for Quantum Electronics and Microelectronics Industry, Dorel has published and presented more than 50 papers, published and contributed to 2 books, holds 7 patents and 11 pending. Dorel is member of American Ceramic Society; Material Research Society; Electrochemical Society and IEEE. He holds “Constantin Miculescu” Physics Prize Presented by Romanian Science Academy. Tutorial II: Sub-65nm design challenges 1. Statistical analysis of variations and leakage Presenter: Sachin Sapatnekar, University of Minnesota Abstract: As device dimensions approach their physical limits at 65nm and below, the effects of variations are seen to dramatically affect the behavior of integrated circuits, and with each technology generation, the effects of variations are seen to more profoundly affect digital circuit behavior. These variations may arise from fluctuations attributed to the manufacturing process (e.g., drifts in channel length, oxide thickness, threshold voltage, or doping concentration), which affect the circuit yield, as well as variations in the environmental operating conditions (e.g., supply voltage or temperature) after the circuit is manufactured, which affect the correctness of the behavior of the design. Some of these variations are entirely deterministic (metal fill density, etc.), while others are considered to be random, as their cause is either unknown, unattributable, or too difficult to model. These effects can cause unacceptable alterations in circuit performance parameters such as timing and power, and therefore, variation analysis and variation-tolerant design is imperative for next-generation designs. This presentation begins with a discussion of the sources of variation, and then overviews recent research in this area, and includes methods for the statistical analysis and optimization of timing and power at the design phase, as well as built-in compensatory techniques to recover performance through post-silicon tuning. Bio: Sachin Sapatnekar received the B.Tech. degree from the Indian Institute of Technology, Bombay in 1987, the M.S. degree from Syracuse University in 1989, and the Ph.D. degree from theUniversity of Illinois at Urbana-Champaign in 1992. From 1992 to 1997, he was an assistant professor in the Department of Electrical and Computer Engineering at Iowa State University. He is currently a Professor in the Department of Electrical and Computer Engineering at the University of Minnesota. He has coauthored two books, ``Timing Analysis and Optimization of Sequential Circuits,'' and ``Design Automation for Timing-Driven Layout Synthesis,'' and is a co- editor of a volume, ``Layout Optimizations in VLSI Designs,'' all published by Kluwer. He has been an Associate Editor for the IEEE Transactions on VLSI Systems, the IEEE Transactions on CAD, and the IEEE Transactions on Circuits and Systems II, has served on the Technical Program Committee for various conferences, as Technical Program and General Chair for the Tau workshop and the International Symposium on Physical Design. He is currently a Distinguished Visitor for the IEEE Computer Society and has been a Distinguished Lecturer for the IEEE Circuits and Systems Society. He is a recipient of the NSF Career Award, of best paper awards at DAC 1997, ICCD 1998, DAC 2001, and DAC 2003, and is a fellow of the IEEE. Tutorial II: Sub-65nm design challenges 2. Variation tolerant design for SOI, multi-gate devices Presenter: Rajiv Joshi, IBM Abstract: To continue scaling of the CMOS devices deep into sub-90nm technologies, fully depleted SOI, strained-Si on SiGe, FinFETs with double gate, and even further, three-dimensional circuits will be utilized to design high-performance circuits. We will discuss unique design aspects and issues resulting from this scaling such as gate-to-body tunneling, self-heating, reliability issues, and process variations. As the scaling approaches various physical limits, new design issues such as Vt modulation due to leakage, low-voltage impact ionization, and higher Vt,lin to maintain adequate Vt,sat, continue to surface. In this part of tutorial, we will discuss these emerging trends and design issues related to aggressive device scaling. Bio: Rajiv V. Joshi is a research staff member at T. J. Watson research center, IBM. He received his B. Tech degree from Indian Institute of Technology (Bombay, India), M.S degree from MIT and Doctorate in Eng. Science from Columbia University, USA. From 1981 to 1983, he with GTE research lab in Waltham, MA. He joined IBM in Nov. 1983, and since then is working in VLSI design systems, science and technology. He worked on 1.25um NMOS, and CMOS, sub-0.5um CMOS logic, DRAM and SRAM technologies. He developed novel interconnect processes and structures for Aluminum, tungsten and Copper technologies which are widely used in IBM for various sub-0.5um memory and logic technologies as well as across the globe. His circuit related work includes design of register files, registers, latches, L1 caches, Directory, TLB, IO circuits development of physical design tools, and CAD based library generation and circuit designs in SOI technology. He contributed to S/390 Alliance processor design, working in both circuit design and CAD tools. The Alliance G5 chip was a very successful IBM product and Joshi received IBM Research Division Awards for his contributions to it and each of the follow-on processor designs. His 2 GHz SRAM design fro G6 received outstanding technical achievement award. His work also involved design related to SRAM designs, which are widely used across IBM System 390. He has won twenty-six invention plateau achievement awards from IBM and won two patent portfolio awards for cross-licensing and utilization of his patents in the IBM products. He has received 5 Research Division Awards, and several top 5% and top 30% patent awards (for licensing activities). On June 6, 2002 he received Corporate Patent Portfolio award from IBM. He is a master inventor & key technical leader at IBM research division. He has authored and co- authored over 95 research papers and presented several invited and keynote talks. He holds 60 U.S. patents in addition to 40 pending patents. He received the Lewis Winner Award in 1992 for an outstanding paper he coauthored at the International Solid State Circuit Conference. He was instrumental in starting interconnect workshop in early 1980s. He chaired advanced interconnect conferences sponsored by MRS and served as an editor of the proceedings. He was elected as an IEEE fellow in 2002 for contributions to chip metallurgy materials and processes, and high performance processor and circuit design. He is actively involved in IEEE ISLPED, IEEE VLSI design, IEEE Int. SOI conf Program committees. Tutorial II: Sub-65nm design challenges 3. Low power and variation tolerant design challenges Presenter: Ruchir Puri, IBM Abstract: It is well known that with CMOS technologies beyond 90nm, leakage power is one of the most crucial design components which must be efficiently controlled in order to utilize the performance advantage from these technologies. We will focus on various techniques to analyze and control all components of leakage power placing particular emphasis on sub-threshold and gate leakage power. In addition, this part of tutorial will discuss low voltage circuit design under high intrinsic leakage, leakage monitoring and control techniques, effective transistor stacking, multi-threshold CMOS, dynamic threshold CMOS, well biasing techniques, and design of low leakage data-paths and caches. Nanometer design technologies must work under tight operating margins, and are therefore highly susceptible to any process and environmental variabilities. This part of the tutorial will consider several factors related to reliability and yield. With regard to environmental variations, it is important to build circuits that have well-distributed thermal properties, and to carefully design supply networks to provide reliable Vdd and ground levels throughout the chip. On the process variation front, the effects of uncertainties in process variables must be modeled using statistical techniques, and they must be utilized to determine variations in the performance parameters of a circuit. Instead of pessimistically treating timing in a worst-case manner as is conventionally done in static timing analysis, statistical techniques will have to be employed that directly predict the percentage of circuits that are likely to meet a timing specification. Bio: Ruchir Puri is a Research Staff Member in Design Automation and VLSI Design group at IBM T J Watson Research Center since 1995. He received M. Tech. degree in electrical engineering from Indian Institute of Technology, Kanpur, India in 1990, and a Ph.D. degree in computer engineering from University of Alberta, Canada in 1994 where he received ACM/IEEE design automation scholarship for his resaecrh. His current research interests include logic, physical design issues for IBM's low-power and high-performance microprocessors and ASICs. He has also been responsible for analyzing and evaluating the design and reliability issues involved in implementing high-performance circuits in advanced technologies. He is inventor of 12 issued/pending U.S. patents and has authored over 50 papers including chapters in John Wiley’s Encyclopedia of Electrical & Electronics Engineering and Encyclopedia of Computer Science. His paper on domino logic synthesis was rated the best synthesis paper in ICCAD-96 and the patent related to this research also received IBM's significant patents award. He was an adjunct assistant professor in Electrical Engineering at Columbia University, New York where he taught VLSI design and Circuits during 2000-01. He has served on technical program committees of several conferences and National Science Foundation review panels. He has also presented/authored tutorials at various conferences such as ICCAD, VLSI Design, ISSCC. He is included in Marquis "Who's Who in America" and "Who's Who in Science and Engineering". Tutorial II: Sub-65nm design challenges 4. Soft Error tolerant architecture and design challenges Presenter: Tanay Karnik, Intel Abstract: Soft errors pose a major challenge for the design of memories and logic circuits in high- performance microprocessors in technologies beyond 90nm. Soft errors and single event upsets are gaining increased attention as the technology scales. Measured data shows 8% soft error rate (SER) increase per bit per technology generation. As the number of memory bits and sequential elements increases across generations, the soft error problem is likely to become a serious barrier for advanced microprocessors. Historically, we have considered power- performance-area tradeoffs. There is a need to include the SER as another design parameter. In this tutorial, we also present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SER using a high-intensity neutron beam, the characterization of SER in sequential logic cells, and technology scaling trends. Circuit techniques for soft error tolerance are also presented with their relative benefit. Finally, some directions for the future research will be given. Bio: Tanay Karnik (M’88, SM'04) is a Principal Engineer at Circuit Research Lab in Intel. He received his Ph.D. in Computer Engineering from the University of Illinois at Urbana-Champaign in 1995. From 1995 to 1999, he worked in the Strategic CAD Lab at Intel working on RTL partitioning, physical design and special circuits layout. Since March 1999, he has lead the power delivery, soft error rate, and optoelectronic circuits research in the Circuits Research, Intel Labs. Earlier, from 1987 to 1988, Tanay worked on programmable logic controller design at Larsen & Toubro Ltd.* in India. He spent the summer of 1994 at AT&T Bell Labs* developing a timing and synthesis module for FPGAs. His research interests are in the areas of power delivery, soft errors, voltage regulator module (VRM) circuits, leakage tolerance and physical design. He has published over 30 technical papers, has 19 issued and 53 pending patents in these areas. He has presented several invited talks and tutorials. He serves on ICCAD, ISQED, DAC and ICICDT committees. He is on the review committees of JSSC, TCAD, TCAS and TVLSI. He served as the Technical Program Chair for ISQED'06. He has also graduated 3 PhD students as an industrial advisor.