# Instruction Set - Excel by aof75410

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```									                                                                            RISC Instruction Set for COP 3402

Arithmetic / Logic                       Opcode First  Second Third Opcd # of Example asm code                   Action taken
Name Operand Operand Operand Type Opr
Add                                      ADD     Dest Reg   Src Reg 1   Src Reg 2   2    3   ADD R1, R2, R3      R1   <-   R2 + R3
Add Immediate                            ADDI    Dest Reg   Src Reg     Immediate   1    3   ADDI R1, R2, 100    R1   <-   R2 + 100 (16-bit signed int)
Add Unsigned                             ADDU    Dest Reg   Src Reg 1   Src Reg 2   2    3   ADDU R1, R2, R3     R1   <-   R2 + R3
Add Unsigned Immediate                   ADDUI   Dest Reg   Src Reg     Immediate   1    3   ADDUI R1, R2, 100   R1   <-   R2 + 100 (16-bit unsigned int)
Subtract                                 SUB     Dest Reg   Src Reg 1   Src Reg 2   2    3   SUB R1, R2, R3      R1   <-   R2 - R3
Subtract Immediate                       SUBI    Dest Reg   Src Reg     Immediate   1    3   SUBI R1, R2, 100    R1   <-   R2 - 100 (16-bit signed int)
Subtract Unsigned                        SUBU    Dest Reg   Src Reg 1   Src Reg 2   2    3   SUBU R1, R2, R3     R1   <-   R2 - R3
Subtract Unsigned Immediate              SUBUI   Dest Reg   Src Reg     Immediate   1    3   SUBUI R1, R2, 100   R1   <-   R2 - 100 (16-bit unsigned int)
Multiply                                 MULT    Dest Reg   Src Reg 1   Src Reg 2   2    3   MULT R1, R2, R3     R1   <-   R2 * R3
Multiply Immediate                       MULTI   Dest Reg   Src Reg     Immediate   1    3   MULTI R1, R2, 100   R1   <-   R2 * 100 (16-bit signed int)
Divide                                   DIV     Dest Reg   Src Reg 1   Src Reg 2   2    3   DIV R1, R2, R3      R1   <-   R2 / R3   (integer division)
Divide Immediate                         DIVI    Dest Reg   Src Reg     Immediate   1    3   DIV R1, R2, 100     R1   <-   R2 / 100 (16-bit signed int, integer division)
AND                                      AND     Dest Reg   Src Reg 1   Src Reg 2   2    3   AND R1, R2, R3      R1   <-   R2 & R3   (bitwise AND)
AND Immediate                            ANDI    Dest Reg   Src Reg     Immediate   1    3   ANDI R1, R2, 100    R1   <-   R2 & 100 (bitwise AND, 16-bit signed int)
OR                                       OR      Dest Reg   Src Reg 1   Src Reg 2   2    3   OR R1, R2, R3       R1   <-   R2 | R3   (bitwise OR)
OR Immediate                             ORI     Dest Reg   Src Reg     Immediate   1    3   ORI R1, R2, 100     R1   <-   R2 | 100 (bitwise OR, 16-bit signed int)
Shift Left Logical                       SLL     Dest Reg   Src Reg 1   Src Reg 2   2    3   SLL R1, R2, R3      R1   <-   R2 << R3 (fill with zeros)
Shift Left Logical Immediate             SLLI    Dest Reg   Src Reg     Immediate   1    3   SLLI R1, R2, 4      R1   <-   R2 << 4   (fill with zeros)
Shift Right Arithmetic                   SRA     Dest Reg   Src Reg 1   Src Reg 2   2    3   SRA R1, R2, R3      R1   <-   R2 >> R3 (extend sign bit)
Shift Right Arithmetic Immediate         SRAI    Dest Reg   Src Reg     Immediate   1    3   SRAI R1, R2, 4      R1   <-   R2 >> 4   (extend sign bit)
Set if Less Than                         SLT     Dest Reg   Src Reg 1   Src Reg 2   2    3   SLT R1, R2, R3      if   R2   < R3 then R1 <- 1 else R1 <- 0
Set if Less Than Immediate               SLTI    Dest Reg   Src Reg     Immediate   1    3   SLTI R1, R2, 100    if   R2   < 100 then R1 <- 1 else R1 <- 0
Set if Greater Than                      SGT     Dest Reg   Src Reg 1   Src Reg 2   2    3   SGT R1, R2, R3      if   R2   > R3 then R1 <- 1 else R1 <- 0
Set if Greater Than Immediate            SGTI    Dest Reg   Src Reg     Immediate   1    3   SGTI R1, R2, 100    if   R2   > 100 then R1 <- 1 else R1 <- 0
Set if Less Than or Equal                SLE     Dest Reg   Src Reg 1   Src Reg 2   2    3   SLE R1, R2, R3      if   R2   <= R3 then R1 <- 1 else R1 <- 0
Set if Less Than or Equal Immediate      SLEI    Dest Reg   Src Reg     Immediate   1    3   SLEI R1, R2, 100    if   R2   <= 100 then R1 <- 1 else R1 <- 0
Set if Greater Than or Equal             SGE     Dest Reg   Src Reg 1   Src Reg 2   2    3   SGE R1, R2, R3      if   R2   >= R3 then R1 <- 1 else R1 <- 0
Set if Greater Than or Equal Immediate   SGEI    Dest Reg   Src Reg     Immediate   1    3   SGEI R1, R2, 100    if   R2   >= 100 then R1 <- 1 else R1 <- 0
Set if Equal                             SEQ     Dest Reg   Src Reg 1   Src Reg 2   2    3   SEQ R1, R2, R3      if   R2   = R3 then R1 <- 1 else R1 <- 0
Set if Equal Immediate                   SEQI    Dest Reg   Src Reg     Immediate   1    3   SEQI R1, R2, 100    if   R2   = 100 then R1 <- 1 else R1 <- 0
Set if Not Equal                         SNE     Dest Reg   Src Reg 1   Src Reg 2   2    3   SNE R1, R2, R3      if   R2   != R3 then R1 <- 1 else R1 <- 0
Set if Not Equal Immediate               SNEI    Dest Reg   Src Reg     Immediate   1    3   SNEI R1, R2, 100    if   R2   != 100 then R1 <- 1 else R1 <- 0
RISC Instruction Set for COP 3402

Load / Store                    Opcode First  Second Third Opcd # of Example asm code                  Action taken
Name Operand Operand Operand Type Opr
Load Byte                       LB     Dest Reg     Src Reg     Var Name   1    3   LB R1, R2, name    R1 <- MEM[R2+name]           (copy 8 bits, extend sign bit)
Load Byte Unsigned              LBU    Dest Reg     Src Reg     Var Name   1    3   LBU R1, R2, name   R1 <- MEM[R2+name]           (copy 8 bits, fill with zeros)
Load Halfword                   LH     Dest Reg     Src Reg     Var Name   1    3   LH R1, R2, name    R1 <- MEM[R2+name]           (copy 16 bits, extend sign bit)
Load Halfword Unsigned          LHU    Dest Reg     Src Reg     Var Name   1    3   LHU R1, R2, name   R1 <- MEM[R2+name]           (copy 16 bits, fill with zeros)
Load Upper Halfword Immediate   LUHI   Dest Reg     Immediate              1    2   LUHI R1, 100       R1 <- 100 << 16              (value loaded into upper half)
Load Word                       LW     Dest Reg     Src Reg     Var Name   1    3   LW R1, R2, name    R1 <- MEM[R2+name]           (copy 32 bits)
Store Byte                      SB     Dest Reg     Var Name    Src Reg    1    3   SB R1, name, R2    MEM[R1+name] <- R2           (copy 8 bits to memory)
Store Halfword                  SH     Dest Reg     Var Name    Src Reg    1    3   SH R1, name, R2    MEM[R1+name] <- R2           (copy 16 bits to memory)
Store Word                      SW     Dest Reg     Var Name    Src Reg    1    3   SW R1, name, R2    MEM[R1+name] <- R2           (copy 32 bits to memory)
Move                            MOV    Dest Reg     Src Reg                1    2   MOV R1, R2         R1 <- R2                     (copy, does not erase R2)

Branch / Jump                   Opcode First  Second Third Opcd # of Example asm code                  Action taken
Name Operand Operand Operand Type Opr                                 (note: label offsets are signed)
Branch if Equal to Zero         BEQZ   Src Reg      Label                  1    2   BEQZ R1, label     if R1==0 then PC <- PC + (label offset)
Branch if Not Equal to Zero     BNEZ   Src Reg      Label                  1    2   BNEZ R1, label     if R1 !=0 then PC <- PC + (label offset)
Jump Absolute                   JA     Dest Reg                            1    1   JA R1              PC <- R1                         (absolute address in R1)
Jump Absolute and Link          JAL    Dest Reg                            1    1   JAL R1             R31 <- PC, PC <- R1
Jump Relative                   JR     Label                               3    1   JR label           PC <- PC + (label offset)
Jump Relative and Link          JRL    Label                               3    1   JAL label          R31 <- PC, PC <- PC + (label offset)
No Operation                    NOP                                        3    0   NOP                takes no action
Exit                            EXIT   Error Code                          3    1   EXIT code          exits from program                (if error then code != 0)

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