BI ANNUAL REPORT JANUARY INTRODUCTION Gary Kelson Executive Director

BI-ANNUAL REPORT JANUARY 2009 INTRODUCTION Gary Kelson, Executive Director Berkeley Wireless Research Center The Berkeley Wireless Research Center is pioneering a new wave of university-industry-government research partnerships. The Center is focused on forging deep relationships with leading wireless and semiconductor companies so that industry can rapidly transfer new technologies and university researchers can benefit from industrial experience. BWRC provides an environment for research into the design issues necessary to support next generation wireless communication and integrated systems and expand the graduate research program in these segments. The research focus is on highly-integrated CMOS implementations with the lowest possible energy consumption and advanced communication algorithms. Components are fabricated using state-of-the-art processes and evaluated in a realistic test environment. Center membership provides access to faculty and graduate students involved in a large interdisciplinary research effort with a modest investment. The critical-mass combination of UC Berkeley researchers, government funding agencies and leading companies in their respective areas has the potential of making truly significant advances possible. BWRC research is grouped into the following six themes: 1. Advanced Spectrum Utilization The goal of this group is to fundamentally change the operation of wireless communication systems. One hundred years of spectrum sharing based on fixed frequency allocations have led to fracturing and poor utilization. Due to the explosive growth of wireless communications over the last decade, reliance on mobile telephones for daily voice and data communication, and often for first contact in case of emergency, has become pervasive. Present methods of frequency allocation combined with a reliance on fixed infrastructure threaten to halt this growth. An additional consequence is the deployment of fundamentally less robust systems, prone to disruption in major disasters or overload. By enabling the secondary use of spectrum on an opportunistic basis, ubiquitous, robust and agile wireless systems can be realized that are able to support further traffic growth and changing demands in traffic, while ensuring operation in case of emergencies. As such, it will enable the extension of wireless data-rates and coverage for many decades to come and open the door for exciting new applications to emerge. This group will lay the theoretical foundation, develop the necessary systems knowledge, and demonstrate a prototype of a new kind of a wireless system, which will operate in a very broad frequency spectrum with bands of operation that can be dynamically allocated. Such a system would be able to reuse the frequency bands that the primary users are not using at a particular time and a particular location. Demonstration of a wireless terminal, a prototype device, will be a centerpiece of this program. This wireless terminal will replace today’s mobile phone, and will interoperate with a ‘connectivity broker’, a device that will ultimately replace today’s access points, to support a diversity of radio technologies and innovative rules of cooperation to couple to the wireless infrastructure. The terminal will be able to migrate from infrastructure-supported operation to communication within a mesh network, using either centralized frequency allocation or intelligent and cooperative sensing of unutilized bands. The concept of secondary use of the spectrum in combination with advanced cooperation between system 1 components is revolutionary, and is enabled by advances in fundamental communications and networking theory and continued improvements in integrated circuit technology. 2. 60 GHz and Above The aim of this group is to design and implement highly-integrated mm-Wave transceivers using conventional silicon technology. The group consists of circuit designers who interact with system engineers to design efficient communication systems. Our current focus is to exploit the 7 GHz of unlicensed spectrum around 60 GHz to provide very high data rates (~1 Gbps) to multiple users within an indoor wireless environment. We are also exploring application at frequencies up to 100GHz such as imaging. Operating at mm-wave frequencies using technologies with lossy substrates requires novel circuit design techniques as well as accurate high-frequency modeling of active and passive devices. Also, new system design methodologies will be needed to account for the limited performance of CMOS microwave circuits at 60 GHz along with the huge amounts of available bandwidth. To accomplish this goal, our group combines Berkeley's traditional expertise on integrated circuit design, device modeling, and system design with the state-of-the-art silicon technologies and vast experience with mm-wave circuit design provided by the BWRC industrial partners. 3. Ultra-low Power Wireless Moore's law keeps increasing the number of transistors per die, decreasing electronics’ cost and making truly ubiquitous electronics a potential. In order to achieve this potential however, power dissipation remains a bottleneck. This group explores the boundaries of low-power design, seeking new design paradigms in order to enable massive power reduction and hence increase integration. In order to achieve these goals, we combine the potential of MEMS resonators and state-of-the-art CMOS. This project is building on the foundations of the now infamous PicoRadio project, which ran at the BWRC between 1999 and 2005. 4. Energy Scavenging & Storage Energy scavenging is a critical enabling technology for energy self-sufficient systems (no replaceable batteries). Potential energy sources being studied include: Photovoltaic (Solar), Vibrations, Air Flow, Temperature Gradients, Pressure Gradients and Human Power. This group is developing an infinite-life power source for Demand Response wireless temperature sensor nodes by using piezoelectric materials to convert ambient environmental vibrations to usable low-level electricity, thus eliminating the need for batteries as primary power storage. 5. Reconfigurable Systems The BWRC reconfigurable systems project is concerned with the design, application, and dissemination of FPGA-based computing systems. These activities include hardware system design with a major focus on using commercial off-the-shelf technologies, but also extend to design of novel computing fabrics. A particularly challenging problem in the successful application of these systems is in providing a convenient programming model and associated mapping and support tools. This challenge has been a major emphasis of this research. Reconfigurable computing platforms have evolved to be an indispensable part of the research infrastructure at BWRC. They help support the other activities of the center and have stimulated and enabled research that would otherwise not have been possible. 2 Three generations of the Berkeley Emulation Engine (BEE), a modular, scalable FPGA-based computing platform with several software design methodologies have been designed. They target a wide range of high-performance applications, such as: cognitive radio testbeds, novel communication algorithm and chip simulation, electronic circuit simulation, emulation of future manycore computer architectures, real-time radio telescope signal processing, and bioinformatics. 6. Leading Edge Circuits Technology As in the past, current and evolving applications (and the integrated systems that enable them) continue to require significant advances in their underlying circuit implementation. However, as CMOS scaling has shifted into a regime where most of the device parameters do not significantly improve with miniaturization, realizing these circuit advances has become increasingly difficult to achieve. Thus, driven by the over-arching themes of energy-efficiency and robustness in the face of variability, our goal in this group is to develop and demonstrate leading edge circuit technologies to tackle these challenges. Given the many different functions integrated into modern ICs, researchers within this group focus on a variety of building blocks and their associated design methodologies, including digital computing and signal processing circuits, memories, data converters, clock generation and synthesis circuits, embedded testing and characterization circuits, RF components, integrated voltage regulators, and high-speed serial transceivers. In order to evaluate our techniques in the most realistic environment possible, many of the concepts developed within the group are demonstrated in some of the most advanced CMOS processes available (including 45 and 32nm). To push the boundaries even further, our group is also exploring circuit designs exploiting the properties of next-generation and alternative switching devices such as FinFETs, spin-based transistors, and nano-mechanical relays. 3 BWRC FACULTY Elad Alon Assistant Professor of Electrical Engineering and Computer Sciences E-mail: elad@berkeley.edu Research Web Page: http://www.eecs.berkeley.edu/~elad Professor Alon received the B.S., M.S., and Ph.D. degrees in Electrical Engineering from Stanford University. He joined the faculty at the University of California, Berkeley in January 2007. During his time as a student, he also held visiting positions at Intel, AMD, Rambus, HP and IBM, where he worked on integrated circuits for a variety of applications. His current research interests are in energy-efficient integrated system design, including analog, digital, and mixed-signal circuits, onchip power conversion and management, and broadband communications. Bob Brodersen Professor Emeritus of Electrical Engineering and Computer Sciences BWRC Scientific Co-Director E-mail: rb@eecs.berkeley.edu Research Web Page: http://bwrc.eecs.berkeley.edu/People/Faculty/rb/ A pioneer in the field of computer speech recognition and a leading authority in wireless communication. Professor Brodersen received his Ph.D. from MIT in 1976 and was associated with the Central Research Laboratory, Texas Instruments until 1976, when he joined the EECS faculty at the University of California, Berkeley. A member of the National Academy of Engineering, his research interests include communication systems, signal processing and design, layout, simulation, and testing of integrated circuits. 4 Ali M. Niknejad Associate Professor of Electrical Engineering and Computer Sciences E-mail: niknejad@eecs.berkeley.edu Research Web Page: http://www.eecs.berkeley.edu/~niknejad Professor Niknejad was born in Tehran, Iran. He received the B.S.E.E. degree from the University of California, Los Angeles, in 1994, and his Master's and Ph.D. degrees in Electrical Engineering from the University of California, Berkeley, in 1997 and 2000. His current research interests lie within the area of RF/microwave and mm-wave integrated circuits, particularly as applied to wireless and broadband communication circuits in the 60 GHz band. His interests also include device modeling and numerical techniques in electromagnetics. Borivoje Nikolić Professor of Electrical Engineering and Computer Sciences E-mail: bora@eecs.berkeley.edu Research Web Page: http://www.eecs.berkeley.edu/~bora/ Professor Nikolić has main interests in the implementation of communications circuits and systems. He received his Dipl. Ing and M.Sc. degrees in Electrical Engineering from University of Belgrade, Yugoslavia in 1992 and 1994, respectively. He received a Ph.D. degree in Electrical and Computer Engineering from University of California, Davis in 1999. Before coming to Berkeley, he had appointments as a lecturer at the University of Belgrade and with Silicon Systems, Inc., Texas Instruments Storage Products Group, San Jose, CA, where he worked on disk drive signal processing electronics. 5 Jan Rabaey Donald O. Pederson Distinguished Professor of Electrical Engineering and Computer Sciences BWRC Scientific Co-Director Director Gigascale Systems Research Center (GSRC) E-mail: jan@eecs.berkeley.edu Research Web Page: http://bwrc.eecs.berkeley.edu/People/Faculty/jan/ A leader in the domains of low power design technologies and methodologies. After receiving his Ph.D. degree in Applied Sciences from the Katholieke Universiteit Leuven, Belgium in 1983, he joined the University of California, Berkeley as a Visiting Research Engineer. From 1985 to1987 he was a research manager at IMEC, Belgium, and in 1987, he joined the faculty of the Electrical Engineering and Computer Science department of the University of California, Berkeley. From 1999 until 2002, he was the Associate Chair of the EECS department at UC Berkeley. He is also the director of the FCRP Gigascale Systems Research Center (GSRC). An IEEE Fellow and recipient of the 2008 IEEE CAS Mac Van Valkenburg Award, his current research interest includes the conception and design of next-generation wireless systems with a special focus on ubiquitous distributed systems. John Wawrzynek Professor of Electrical Engineering and Computer Sciences E-mail: johnw@eecs.berkeley.edu Research Web Page: http://www.cs.berkeley.edu/~johnw/ Professor Wawrzynek received his Ph.D. from the California Institute of Technology and holds an M.S. in Electrical Engineering from the University of Illinois, Urbana-Champaign. His current research interests are in the design and application of high-performance reconfigurable computing systems. He is currently Principal Investigator of the RAMP (Research Accelerator for Multiple Processors) project. Professor Wawrzynek teaches courses in computer architecture and digital design. 6 Paul K. Wright Professor A. Martin Berlin Chair in Mechanical Engineering E-mail: pwright@bwrc.eecs.berkeley.edu Research Web Page: http://www.me.berkeley.edu/faculty/wright/ Paul K. Wright is the Acting Director for CITRIS at UC Berkeley. CITRIS is the Center for Information Technology in the Interest of Society. It serves four University of California campuses and hosts many multi-disciplinary projects on large societal problems such as healthcare, services and intelligent infrastructures such as energy, water and sustainability. Professor Wright teaches in the mechanical engineering department, where he holds the A. Martin Berlin Chair. He also serves as codirector of the Berkeley Manufacturing Institute (BMI) and codirector of the Berkeley Wireless Research Center (BWRC). From 1995 to 2005 he served as co-chair of the Management of Technology Program (a joint program with the Haas School of Business). His research and teaching are in high-tech product design and rapid manufacturing. Currently, he and his colleagues are designing and prototyping wireless systems for "demand response power management" throughout California, funded by PIER/CEC (the Public Interest Energy Research program of the California Energy Commission). Born in London, England, he attended Birmingham and Cambridge universities prior to attaining previous U.S. faculty positions at New York University and Carnegie Mellon University. 7 1. 60 GHz and Above 1.1 A Fully Integrated 90 GHz Low-Power Phased-Array Transceiver in CMOS Ehsan Adabi, PhD 2010 Advisor: Ali Niknejad Email: adabi@eecs.berkeley.edu Publications Phased arrays are multiple antenna systems that can focus the signal energy into a narrow beam radiating into/from specific directions, and electronically "steer" the direction of signal transmission and reception. Beam steering capability and placing nulls at undesired directions alleviate impairments such as fading, delay spread, and co-channel interference. Also in a multi antenna system automatic spatial power combining relaxes the PA design requirements which improves the power dissipation and efficiency of the transmitter. Phased arrays have been used for high data rate communications, imaging, and radar applications due to their ability to form electronically steerable beams. They have been limited to discrete or hybrid implementations, where off-chip antennas are connected to their associated electronics (on-chip/off-chip). This approach is suitable for high-end systems and not efficient in terms of system cost, size, and power consumption. A monolithic phased array system in silicon that integrates all radiating antenna elements, RF and high frequency circuitry, and baseband digital processing building blocks is highly desired due to its lower complexity, power consumption and cost which make it suitable for consumer electronic applications. Nanoscale CMOS demonstrated the design feasibility at mmwave frequencies where antennas are not prohibitively large to be implemented on-chip. The goal of this research is to design a relatively wideband single-chip mm-wave phased array system. All building blocks performing up/down conversion, signal combining/dividing, low noise/high power amplification, and radiation should be capable of handling wideband signals which requires employing new techniques and architectures. This fully integrated architecture will generate and receive arbitrary two-dimensional beam patterns at mm-wave (90 GHz) regime. 1.2 Low Power 60GHz Receiver and UltraWideband Pulsed Transmitter Bagher Afshar, PhD 2010 Advisor: Ali Niknejad Email: b_afshar@eecs.berkeley.edu Publications Emerging applications for the 60GHz spectrum include extremely high-data-rate short-range communication systems. Many of these applications are expected to enter the realm of consumer electronics where low cost and mass production are prerequisites, favoring the application of digital CMOS technology. In this research, a highly integrated receiver front-end is demonstrated that is manufactured in a digital CMOS process using a design approach amenable to mass production. Unlike many previous attempts in CMOS, the results of the design are well predicted by the simulation results, matching the desired frequency band and the simulated gain to a very high accuracy. Low noise and high gain are demonstrated with low power consumption. These factors in unison make this front-end suitable for small footprint mobile applications such as a cell phone, PDA, or laptop computer. The die photo of the receiver is shown below. The receiver consumes 24 mW from a 1V supply and includes a low noise amplifier (LNA), an active Gilbert down-converting mixer, and a wideband variable gain amplifier (VGA). I have begun a new research project working on the design of an ultra-wideband pulsed transmitter which has potential application in very high resolution remote sensors and medical imagers. Challenges include the generation of very narrow pulses with high output power while minimizing low dispersion. The circuitry will be realized in a 0.13µm SiGe BiCMOS process. Die Photo of the Front-End Receiver (presented at ISSCC 2008) 1.3 Microwave Medical Imaging Amin Arbabian, PhD 2010 Advisor: Ali Niknejad Email: arbabian@bwrc.eecs.berkeley.edu Publications Cancer is the second leading cause of death in the U.S. and the world. Detection in early stages has proven to be essential for reducing the mortality rate. Medical imaging techniques are used to detect and classify potential cancerous tissues by the "traces" that are left from the abnormal cells. Depending on the imaging modality, tumor biology, and the physical parameters involved in the system, the effectiveness of the provided visualization for the process of detection is examined. The focus of this research is to use the contrast in microwave signals to various tissue abnormalities for the early detection of cancer. In order to achieve this, a large bandwidth is required to provide adequate lateral resolution. UWB signaling provides greater frequency information as well as sufficient tissue penetration, but requires a careful design to address concerns in various system blocks, from signal generation to detection and interpretation. To address the BW issue, frequencies in the sub-THz region are explored and the design of silicon based circuits in that frequency range investigated. In the initial phase of the project, blocks of this system have been designed and tested. For the desired bandwidth, a distributed amplifier (DA) is designed to meet the specifications. A new method and architecture is proposed for the design of wideband, high gains DAs. As a proof of concept, a DA in the 12-74 GHz range with 19 dB of gain is designed in a digital 90 nm CMOS technology. The whole system being designed by the group incorporates a wideband front-end, mm-wave frequency-agile PLL, and baseband signal processing consisting of a high resolution sampler and data converter and the interface to the external processor. Chip micrograph of the distributed amplifier 1.4 The Design of SAR Imager Baseband Processor Ashkan Borna, PhD 2012 Advisor: Ali Niknejad Email: ashborna@eecs.berkeley.edu Medical imaging techniques are used to detect and classify potential cancerous tissues by the "traces" that are left from the abnormal cells. By using the contrast in microwave signals to various tissue abnormalities, the special baseband processor for retrieving the returned signal is needed. The focus of this research is to implement a baseband system for processing the SAR imager high frequency sampler output. The challenges in the design of this system are due to the high resolution, high speed and area constraints. The resolution is due to the signal loss. Typically the received signals would be attenuated by 100dB. Also the PA for UWB has ringing effects that might be 60dB or 70dB higher than the received signal. As a result, the dynamic range should be above 70dB in order to successfully detect the signal. A 12 bit SAR ADC has been chosen for this system. The other issue is due to the wideband nature of the weak signal which would translate to the negative received SNR in the baseband. Considering the system is fed by the high frequency sampler every 1ns, this means that the integrator needed for improving the SNR has the criteria of settling to 12 bits accuracy in less than 1ns. 1.5 Programmable Biasing for mm-wave Circuits Steven Callender, MS 2009 Advisor: Ali Niknejad Email: steven86@eecs.berkeley.edu I am currently working on the Time Domain UWB SAR Imager (TUSI) project under the advisement of Professor Ali Niknejad. This project uses cutting edge, high-speed BiCMOS technology to design high frequency (> 90 GHz) and highly sensitive transceivers that will be used, collectively, to form a microwave imager. For this project, I am responsible for the design of the tunable biasing circuitry. Due to process and temperature variations, the performance of many analog blocks (amplifiers, samplers, mixers) is directly affected. It is desirable to have the ability to control the performance of each analog block via its biasing circuitry. Most analog blocks receive their biasing from current sources. I am currently designing digitally programmable current sources that can provide accurate currents over a specified range. These current sources come in two flavors: CMOS (for low current blocks, < 1mA ) and Bipolar (for high current blocks). In addition to controlling the amount of current being sourced/sinked by the current sources, it is also desirable to switch the current sources on/off in order to save power. For high current blocks that are active for a short period of time, a significant amount of power can be saved if the current to these blocks is turned off during that period of inactivity. However, the switching has to occur at very high speeds (sub nanosecond), which proves to be very challenging. Techniques on how to efficiently switch these current sources are currently being investigated. 1.6 90-GHz PLL and Clock Synthesis Jun-Chau Chien, PhD 2013 Advisor: Ali Niknejad Email: jcchien@eecs.berkeley.edu This research project focuses on the design of a 90-GHz PLL to generate I/Q LO signals for TimeDomain Ultra-Wideband SAR Imager (TUSI) transceiver in BiCMOS technology. Such UWB transceiver can be used in medical imaging for early detection of cancer. Several PLL architectures are compared, such as fundamental PLL, sub-harmonically injection-locked type, and push-push topologies. Important specifications of the PLL include spur levels, optimum loop bandwidth, phase margin, and area. To provide sufficient low reference spurs, a dual-loop fundamental PLL based on a XOR phase detector and 2nd-order loop filter is selected. A frequency detection loop is employed to maximize the locking range of the PLL. Noise from each building block is carefully considered in order to meet phase noise and jitter requirement. To sustain high-frequency oscillation while providing sufficient tuning range, a common-collector Colpitts oscillator with transmission line resonator is utilized. Quadrature outputs are generated through anti-phase coupling between two identical oscillators. The divider chain includes a regenerative frequency divider followed by current-mode-logic static frequency dividers with speed and power optimized. All signals are differential to provide excellent common-mode rejection. The voltage-controlled oscillator has an on-chip supply regulator to prevent noise coupling from the supply line. Block diagram of a 94-GHz PLL in BiCMOS technology. 1.7 Efficient Power Generation at RF and mmWave Frequencies Debopriyo Chowdhury, PhD 2010 Advisor: Ali Niknejad Email: ebopriyo@eecs.berkeley.edu Publications Efficient power amplifier (PA) in CMOS technology has been an area of active research over the last few years. The low supply voltage of CMOS process together with the loss of on-chip passives and lossy silicon substrate make high-power fully integrated power amplifier design highly challenging. Moving up higher in frequency to 60GHz entails more challenges in terms of device and passive modeling. In this research, we have focused on transformer-coupled 60GHz power amplifier design. In the first phase, a 2-stage PA was designed that made use of optimized transformers for input, output and inter-stage matching. The 90nm PA was measured to have a Psat of 12dBm from a 1-V supply. Although the output power was high, the power gain was only 6dB, which had a big impact on the net power-added efficiency. At these frequencies, since power gain of transistors is limited, simultaneous optimization based on both gain and output power needs to be performed. In addition, driver stage sizing has a significant impact on the overall performance, since the gain of the output stage is usually not too high. These considerations were taken into account to design a new 3-stage 60GHz PA. This PA has a measured Pout of 11dBm at 60GHz but a power gain greater than 14dB as well. This has enables us to achieve a net PAE in excess of 15%, which is one of the highest in literature. The 3-stage PA has been integrated into a complete 60GHz transceiver consisting of RF, baseband and integrated PLL. The entire transmitter consumes 170mW, while the receiver burns 130mW from a 1.2V supply. The PA has been tested with modulated data and can support up to 10Gbps QPSK data transmission (eye diagram shown below). In addition to the design work, we have come up with lumped and distributed modeling of integrated transformers, which can enable efficient matching network design. Measured 60GHz transmitter eye diagram for QPSK data transmission 1.8 System Level Issues of the Wafer-Scale Distributed Radio Antoine Frappe, Postdoc Advisor: Elad Alon Email: antoine.frappe@gmail.com The wafer-scale distributed radio project aims to quantify the technical challenges and ultimate performance of a wafer scale distributed mm-wave radio implemented in deeply scaled silicon technology. This research focuses on the system level issues associated with its implementation, including: - Baseband clock distribution and synchronization over the whole wafer. The goal is to distribute a low-skew 1 - 10GHz clock that will be used both for baseband data synchronization and as a reference for the 90GHz local oscillators. Coupled standing-wave oscillators are good candidates for this type of distribution as they can be patterned, easily coupled, and are able to cover large areas with low skew. The study will include the impact of jitter on the performance of the whole radio. - Power distribution. As a preliminary approach, power would be supplied from the backside of the wafer using through-substrate interconnects, as the frontside will be patterned with antenna arrays. State-of-the-art 3D integration offers innovative ways of supplying power and signals to the chip and will be investigated in this project. - Antenna calibration. In order to form the best possible radiation pattern, the antennas must be calibrated to take into account non-idealities such as clock skew or phase-shifter static errors. The calibration scheme must be efficient for such a large array of transceivers and less than 5 degrees of phase error is targeted. Wafer-Scale CMOS Distributed Radio Clock distribution using coupled λ/2 standing-wave oscillators, designed to fit the slot antenna array pattern of the wafer-scale radio transmitter 1.9 10Gbps Baseband Receiver for 60GHz Transceiver Lingkai Kong, PhD 2013 Advisor: Elad Alon Email: konglk@eecs.berkeley.edu The 60GHz band offers the opportunity for wireless connectivity with several Gbps of throughput. However, traditional wireless transceivers require high-speed and high-resolution ADCs that would consume hundreds of mW of power at these rates. This research focuses on an energy-efficient baseband design by employing a high-speed link inspired approach. In our first implementation, the baseband consists of an analog phase rotator to compensate for the phase difference between transmitter and receiver LO, as well as a 5-tap complex DFE to counter channel ISI. The phase rotator consists of a bank of current-summed gm stages whose polarities and input sources are controlled digitally. In a direct implementation, achieving ~5° phase resolution requires 16 gm cells for each of the rotator’s amplifiers. However, all 32 of these cells could never be used while maintaining a fixed gain. Hence, in order to reduce parasitic drain capacitance and power consumption, 8 of the cells are shared between I and Q, resulting in only 24 total cells per output. Rather than a traditional ADC/DSP-based approach, this design makes use of a mixedsignal DFE. A loop unrolled implementation is used to move the critical timing path of the first tap purely into the digital domain. The unrolled first tap uses 4 comparators with tunable thresholds. The comparators use near minimum-sized devices and an 8-bit current-mode offset cancellation DAC to minimize power consumption. When clocked at 2.5GHz (10Gb/s QPSK), the entire mixedsignal baseband consumes only 12mW. 1.10 Low Power Frequency Synthesis for 60GHz Applications Cristian Marcu, PhD 2010 Advisor: Ali Niknejad Email: cmarcu@eecs.berkeley.edu Resume: http://www.eecs.berkeley.edu/~cmarcu/cmarcu_resume.pdf Publications The design of 60GHz transceivers requires a stable local oscillator for up and down conversion of the RF signal being transmitted or received. A voltage controlled oscillator (VCO) is used, locked to a stable frequency reference using a phase locked loop (PLL) as shown in the figure below. The VCO must have a wide tuning range in order to ensure the correct frequencies can be reached despite PVT variations and should have low phase noise so as to not corrupt the wanted signal through reciprocal mixing. Achieving a wide tuning range is difficult at these frequencies due to the low quality factor of varactors, while decreasing noise tends to increase power consumption. Moreover, the design of the PLL requires high speed dividers to bring down the oscillation frequency to the reference frequency for comparison. The first, highest frequency, divider stages are typically power-hungry and require careful design to assure their capture range exceeds the tuning range of the VCO. This research focuses on the design of 60GHz PLLs both from an architectural and circuit design standpoint with a particular emphasis on low power consumption. A General Phase Locked Loop 1.11 Integrated Antennas for Silicon Substrate Jungdong Park, PhD 2012 Advisor: Ali Niknejad Email: jungdong@bwrc.eecs.berkeley.edu Integrated Antenna on silicon is promising technology at millimeter-wave range. The size of the antenna unit element could be designed comparable to other circuits. Therefore, integrated antenna could be a more cost-effective way than a conventional packaging of the antenna with transceivers which causes large insertion-loss at millimeter-wave range. Moreover, a fully integrated system in a single chip provides extra design flexibilities by co-designing antenna with transceivers to achieve the broader space coverage, wide-band, and better beam shaping characteristics. The main challenge of the integrated antenna on a silicon substrate is its low radiation efficiency which is generally less than 10%. There are two main reasons for such a low radiation efficiency. One is the conduction loss owing to low resistivity of the silicon substrate and another is the surface wave mode excitation caused by the silicon substrate with a high permittivity. My research goal is to design on-chip antennas which have radiation efficiency of more than 60%. Several types of antennas have been designed which have a radiation efficiency of more than 60% in HFSS. The next step is to design fully integrated phased array systems consisting of many transceivers. Integrated Antennas for Silicon Substrate 1.12 High Speed mm Wave Transmitter Design Maryam Tabesh, PhD 2012 Advisor: Ali Niknejad Email: tabesh@eecs.berkeley.edu Our research is focused on the design of high throughput, low-power communication circuits and systems in CMOS technology in the 60GHz mm-wave band. A dual-mode fully differential combined DAC-mixer structure has been introduced to improve linearity and power consumption by omitting the transconductance stage. The quadrature, fully differential modulator can be used in QPSK or 64-QAM mode and has the ability to provide data rates up to 30Gb/sec. Using a double balanced switching pair with digitally controlled current sources replacing the gm stages, the required linearity of the switching transistors is reduced and current is reused between the DAC and the mixer. Also, this technique causes lower power consumption since the DAC bias current would be determined by the required output power and output impedance and is not limited by the linearity and the gain of the transconductance stage. The modulator provides -2.3 dBm output power in the nominal case and its total power consumption is 20 mW with an area as small as 380 ìm x 180 ìm. Chip micrograph of the modulator (DAC/Mixer) in 90nm CMOS 1.13 Multi Gb/s 60 GHz Wireless Mobile Transceiver Design Chintan Thakkar, PhD 2012 Advisor: Elad Alon Email: cthakkar@berkeley.edu In order to demonstrate techniques suitable for high data rate communication in mobile handsets, BWRC has recently developed a 60GHz transceiver with integrated baseband circuitry. In contrast to OFDM-based transceivers for set-top boxes, our design is inspired by low-power highspeed chip-to-chip serial links. These links have shown that for high bandwidths and relatively low dynamic range (implying simple modulation), analog processing and a minimal number of comparators is significantly more efficient than multi-bit ADC/DSP-based solutions. Our first transceiver design included a 6-bit digitally programmable analog phase rotator and a 5tap mixed signal decision feedback equalizer (DFE) to validate the high-speed link-based approach. However, even directional communication at 60 GHz can contain significant multi-path energy beyond 10 taps at rates of 5 GS/s. Due to their power consumption increasing quadratically with the number of taps, extending a purely mixed-signal DFE to a large number of taps would be inefficient . We are therefore exploring a hybrid DFE design consisting of a digital FIR filter and DAC combined with mixed-signal taps. The mixed-signal taps relax the latency constraints of the FIR filter, thus enabling the use of parallelism or pipelining to reduce the filter’s power. To complete the rest of the baseband system, we are also exploring a sign-sign LMS based carrier recovery that re-uses one of the DFE comparators for minimal overhead, as well as a mixed-signal baseband phase shifting/power combining technique for phased arrays. 2. Advanced Spectrum Utilization 2.1 A Scalable Power-Efficient Phased-Array Antenna Design for WLANs Omar Bakr, PhD 2009 Advisor: Ali Niknejad Email: ombakr@eecs.berkeley.edu Phased-array antennas can have a considerable impact on how we design wireless systems in the future. Most of the current wireless systems (e.g. WiFi) are based on broadcast. Broadcast reduces range and increases interference levels in wireless systems. Both of these factors significantly increase the overall cost of network deployment. These short comings can be addressed by using phased-arrays, which enable electronic beam-steering or beamforming. However, building scalable, low cost and low power phased-arrays is a challenging problem. Complexity and power requirements grow with the size of the array. In addition, good design and careful layout are required to minimize pattern distortion and cross-coupling between elements of the array. Finally, network protocols must be optimized to take advantage of the beamforming capabilities of these antennas. In this project, we address some of those challenges. First, we are designing an integrated circuit in nanometer CMOS that supports multiple RF channels. Each channel has a complete RF frontend (e.g. PA, LNA, phase-shifters, and switches). Integrating all these components in a single die leads to significant cost savings. We have also built a phased-array prototype on a printed circuit board (PCB) using discrete passive and active RF components at the 2.4GHz band in order to demonstrate the feasibility of low cost phased-arrays for WiFi systems. A photo of our first prototype, a 16-element planar array, is shown in Figure 1. Figure 1: 16-element array prototype (top half) 2.2 Direct Waveform Synthesis Transmitter for Cognitive Radio Stanley Chen, PhD 2009 Advisor: Jan Rabaey Email: yschen@eecs.berkeley.edu Publications The target of this project is to design a frequency-agile transmitter for TV band Cognitive Radio. The transmitter consists of Digital Waveform Synthesizer (DWS), Digital-to-Analog Converter (DAC), clock generation circuitry and the analog front end. The baseband waveforms with various modulation schemes are directly synthesized in digital domain. The transmission characteristics can be dynamically adapted and controlled in DWS. By utilizing the proposed sub-Nyquist rate conversion technique, the DAC converts the sampled digital waveforms into continuous-time analog waveforms and enhances image spectrum located in the target channels. A processindependent, fully-differential regulated Phase-Locked Loop (PLL) generates the low jitter clock for the whole transmitter. This mostly digital transmitter architecture enables reconfigurability and frequency-agility of cognitive radio base station. System-level simulation and analysis are implemented in Matlab. The prototype system of the proposed transmitter architecture will be implemented in the future. Transmitter Architecture 2.3 Broadband Highly Linear CMOS LNA Designs Employing Noise/Distortion Cancellation Wei-Hung Chen, PhD 2008 Advisor: Ali Niknejad Email: whchen@eecs.berkeley.edu Publications The emerging 4G telecom system envisages ubiquitous wireless connectivity that supports multiple radio standards across multiple frequency bands and features reconfigurability for agile service switching and adaptive power consumption in response to the radio dynamics. One key challenge in bringing out a multi-standard multi-mode front-end resides in fulfilling the high linearity and low noise over a wide frequency range. Even in a “digital” receiver application, employing discrete-time signal processing, a linear front-end amplifier is required to reject the noise and relax the performance of the subsequent samplers. The straight solution for multistandard multi-mode front-ends employs reactive tuning and multiple receiving paths at cost of die and board area, high pin count, and lack of reconfigurability. Recent demonstration of ultrawideband (UWB) LNAs ranging from several hundreds of MHz up to 10GHz suggests an alternative that uses single LNA for contiguous broadband signal receiving and has achieved comparable performances to its narrow-band counterparts by exploiting high fT /fmax transistors available from nano-scale CMOS. In this project, we investigate the linearity enhancement by cancelling the second- and third-order distortions of the LNA circuit through multiple techniques. We present two wideband LNA circuit topologies based on simultaneous noise and distortion cancellation and capable of achieving low noise figure and high IIP3 at the same time. The proposed LNA topologies also provide great reconfigurability of trading LNA power consumption off other performances such as noise figure, linearity and gain. Two prototypes manufactured in 0.13um and 65nm CMOS technology have measured IIP3 of +16 dBm and minimum NF of 2.6 and 4dB respectively LNA chip microphotograph 2.4 A Revenue Enhancing Stackelberg Game for Owners in Opportunistic Spectrum Access Ali Ercan, Postdoc Advisor: Jan Rabaey Email: aliercan@eecs.berkeley.edu Web Page: www.eecs.berkeley.edu/~aliercan Publications We investigate a Stackelberg game between three players; spectrum owner, primary users and secondary users under the opportunistic spectrum access (OSA) model. In this model the secondary users share the channel with primary users in time and secondary user access is performed through a non-perfect listen-before-send scheme. We can show through simulations that the spectrum owner can enhance her revenue by allowing OSA with a non-zero interference probability to the primary users. The subscription fee of the primary users is lowered in exchange of the non-zero interference probability. The revenue enhancement results from the subscription fees of the secondary users and better utilization of the spectrum. We can also show through simulations that the enhancement is available for a large range of user preferences such as the value of primary service relative to the secondary, and optimal action of the spectrum owner is robust against estimation errors in these preferences. For the complete paper: http://bwrc.eecs.berkeley.edu/php/pubs/pubs.php/41/dyspan08.pdf. Three player Stackelberg Game. The PO is the leader and the PU and SU are the followers. PO sets the subscription fees of the PU and SU, Gain in the PO revenue by allowing OSA, versus the value and the maximum tolerated interference. In response, the PU and SU set of primary service relative to secondary, for 3 different the probability at which they buy the service. levels of PU channel usage statistics. 2.5 Cooperative Cognitive Radio Networks Milos Jorgovanovic, PhD 2014 Advisor: Borivoje Nikolic Email: milos@eecs.berkeley.edu This research focuses on understanding and implementing current theoretical results in collaborative communication - how to achieve higher data rates and more reliable communication by nodes collaboration and spatial diversity. We are also interested in investigating diversity multiplexing tradeoffs for given communication system, as well as schemes that can achieve these expected values. Realizing a practical wireless network with a relay node that should support communication between source and destination within theoretical limits is an immediate goal. We are working towards understanding practical algorithms and architectures of distributed MIMO systems that can be utilized for this implementation. Simple Collaborative Radio Network 2.6 Low Jitter, Fully Differential Regulated PLL for TV Band Cognitive Radio Nam-Seog Kim, PhD 2012 Advisor: Jan Rabaey Email: namseog@eecs.berkeley.edu One of the critical issues in implementing high speed, high resolution DACs is sampling clock jitter. The DAC SNR degrades as the sampling clock jitter increases and the input signal frequency becomes higher. Power supply noise on a PLL¡¯s supply inputs, which appears on the output as jitter. This is the largest, though not always constant, contributor to jitter. Power supply noises are VDD noise and ground bounce. In this work, both power supply and ground are included in the regulation loop. This can be achieved by using the difference between positive and negative VCO supplies as a differential control voltage as shown in Fig.1. A much smaller decoupling capacitor is included to reduce noise not attenuated by the imperfect regulation loop and for stability of the regulation loop. Another challenge is the distribution of the generated onchip clock with a small uncertainty. To reduce jitter, a compensator circuit is added to the differential clock drivers that offsets within 10% supply-induced delay variation. Fig.1. Fully differential supply regulated adaptive band width PLL 2.7 System Issues in Cognitive Radios Mubaraq Mishra, PhD 2009 Advisor: Bob Brodersen, Anant Sahai Email: smm@EECS.Berkeley.EDU Web Page: http://bwrc.eecs.berkeley.edu/~smm/ Publications Detection sensitivity for sensing is determined using worse case models for multipath and shadowing which makes it difficult to achieve. Furthermore, uncertainty in noise/interference can dramatically reduce the achievable sensitivity [1]. Even if we could achieve this sensitivity through calibration, a conservative specification of the detection sensitivity can lead to a loss in potential white space [2]. Cooperation between cognitive radios has been advanced as a technique to alleviate some of these sensing requirements and regain white space [2, 3]. Differences in performance of various cooperation techniques depends on the number samples and the relative SNR regimes of the cooperating radios [4]. Multiband sensing helps us change detection sensitivity dynamically by calibrating the sensitivity level for a given primary by using sensing measurements from nearby frequencies [5]. The issue with multiband sensing is that it works best with primaries that are off but does not aid in the area recovery problem. Using the FCC TV database together with a geo-location device is a potential way around these issues [6]. [1] S.M.Mishra et al. Detect and Avoid: An Ultra-Wideband/WiMax Coexistence Mechanism, IEEE Comm. Mag., 45(6), p6875, 2007. [2] R. Tandra, S. M. Mishra and A. Sahai, “What is a spectrum hole and how can we recover it?”, Proceedings of the IEEE, 2009 [3] S. M. Mishra, A. Sahai, R. W. Broderson. Cooperative sensing among Cognitive Radios. IEEE ICC, p1658-1663, 2006 [4] S.M.Mishra, R. W. Brodersen, Cognitive Technology for Improving Ultra-Wideband (UWB) Coexistence, IEEE ICUWB, p253-258, 2007. [5] S. M. Mishra, R. Tandra and A. Sahai, “The case for multiband sensing”, Allerton Conference, 2007 [6] S. M. Mishra and A. Sahai, “How much white space is there?”, In Submission. How much white space is there? 2.8 Cooperative Spatial Multiplexing in the Relay Channel Vinayak Nagpal, PhD 2010 Advisor: Borivoje Nikolic Email: vnagpal@eecs.berkeley.edu Web Page: http://www.eecs.berkeley.edu/~vnagpal Publications The half duplex wireless relay channel is a fundamental building block for cooperative wireless communication systems. This channel has generated a lot of recent interest in the wireless communication and information theory community. Most known results for the relay channel have focused purely on cooperative diversity, i.e. it has been established that relay cooperation can improve communication reliability. Performance limits for this have been calculated. Can relay cooperation also provide rate improvement? If yes, what sort of cooperative multiplexing gain is possible and under what conditions? What sort of cooperation strategies are needed? My research focus is to find answers to these questions, both from the theory and implementation perspectives. (1,1,2) MIMO Relay Channel 2.9 Connectivity Broker Arash Parsa, PhD 2013 Advisor: Jan Rabaey Email: aparsa@eecs.berkeley.edu Publications The information-technology infrastructure is moving away from the desktop/laptop model to centralized servers, communicating with ubiquitously distributed (and often mobile) access devices. To address the challenges in dynamically managing the spectrum and energy resources in diverse wireless networks, the concept of “connectivity brokerage” has been introduced. At its core, the brokerage is a distributed function that helps to map traffic requests on the wireless resources (platform) such that reliable operation is ensured. Currently I am working on the architecture of the connectivity broker which is in a sense a distributed network/resource manager. One of our goals is to have an architecture which let us experiment with different levels of distribution in terms of processing and information (distributed data base) and also utilize different optimization algorithms. 2.10 Time Domain Digitally-Assisted Active Interference Cancellation Jing Yang, PhD 2009 Advisor: Bob Brodersen Email: yangjing@eecs.berkeley.edu Web Page: http://bwrc.eecs.berkeley.edu/People/Grad_Students/yangjing Publications There is a challenging dynamic range requirement in the analog to digital conversion for Cognitive Radio applications, since there are large interfering signals which are effectively in-band and cannot be removed by fixed RF pre-filtering. Using a mixed analog digital system architecture which uses multiple low accuracy ADCs with digital adaptive filters, it is possible to increase the effective dynamic range of the input by subtracting off the unwanted signals in the time domain. To provide the maximum flexibility, the sensing and transmission function of Cognitive Radios is performed over the widest possible bandwidth consistent with implementation constraints to give the highest probability of detecting unused spectra. Furthermore, since it is desirable to be able to detect the CR signal in the face of much stronger primary interference, the signal to interference (SIR) ratios could range downwards to -50dB. This results in a large dynamic range requirement for the front-end circuitry and in particular for the ADC, which must accommodate the large interfering signals while still providing sufficient quantization performance for the weak CR signal. The whole system can be regarded as a selective AGC which amplifies the CR signal, but not the interfering signals. This technique allows two low-resolution ADCs with N and M bits to substitute for a single high-resolution ADC of greater than N + M bits with GHz range speed. Two interleaved asynchronous SA ADCs had been implemented. A peak SNDR of at least 30dB is achieved at 700MS/s in 65nm CMOS technology with minimum power consumption and an area of 0.25mm2 including analog, digital, memories and pads. System is demonstrated using MCMA board, with sampling frequency of 64MHz, two 10-bit ADCs, 20dB PGAs and one reconstruction 14-bit DAC. By using mixed signal, which contains two low resolution ADCs, it effectively acts as a high-resolution ADC. Architecture for time domain interference cancellation a) An incoming of multiple interfering signals. b) The power spectrum after interference cancellation 3. Energy Scavenging & Storage 3.1 Manufacturing of Dispenser Printed Thermoelectric Energy Harvesting Modules for Wireless Sensor Networks Alic Chen, PhD 2012 Advisor: Paul Wright Email: alic.chen@berkeley.edu To enable wireless sensor nodes to become ubiquitous in the environment, the nodes must have a power source which can run in excess of 10 years. Despite advances in low duty cycling and low power electronics, the practical realization of primary batteries for this task requires cost and form factors which are too great for mass implementation. Instead, this research considers the use of ambient thermal energy harvesting to power the nodes. This research is concerned with the fabrication and manufacturing of dispenser printed thermoelectric elements. The device consists of alternating P and N doped semiconductor elements placed electronically in series. Dispenser printing is being considered because it is a low-cost, production ready method for fabricating micro-scale devices without clean room processing costs. A PDMS stamping technique is used to form a template to which the active thermoelectric materials are dispensed producing the devices. Prototype pneumatic dispenser printer Partially filled PDMS mold 3.2 Sensing for Unhealthy Underground Power Distribution Cables Giovanni Gonzalez, PhD 2010 Advisor: Paul Wright, Richard White Email: giova@me.berkeley.edu A little-known problem threatens systems that deliver electric power to residential and commercial customers: the underground distribution cables that operate at 12,000 volts or higher perform well for a few decades and then suddenly fail with a dramatic one-nanosecond arc. Pacific Gas & Electric alone has 25,000 miles of 3-phase distribution circuits (75,000 miles of aging underground cables), and no real economical way of telling which ones are unhealthy. The California Energy Commission has just funded a 3-year interdisciplinary (Electrical Engineering, Mechanical Engineering and Material Science Engineering) research program at University of California at Berkeley to understand the failure mechanisms and find feasible ways (feasible technically, economically, and organizationally) of checking the health of cables to prioritize replacement. The primary goal of this research is to develop an Intelligent Infrastructure to monitor in-situ maintenance and to explore the degradation of underground AC power distribution cables. Two sub-teams have been created to tackle specific sub-goals: • Scientific Underpinnings Team Goals o Improve understanding of the phenomena of tree growth and other causes of deterioration in underground power distribution cables. o Identify measurable property changes caused by tree growth. Technology Team Goals o Utilizing MEMS, energy scavenging and wireless sensing technologies to identify novel means for discovering and evaluating tree growth and other causes of deterioration in cables that might lead to failure. • During the course of this research, the interdisciplinary research team will work closely with the California Energy Commission and the three investor-owned utilities in the state of California (PG&E, Southern California Edison and San Diego Water and Power) to understand the needs of all the stakeholders involved and to be able to produce a user friendly infrastructure. 3.3 Printable Energy Storage Systems for Wireless Sensor Networks Christine Ho, PhD 2009 Advisor: Paul Wright, James Evans Email: ccho2005@berkeley.edu Publications We are using a direct write dispenser printing method for integrating both lithium ion batteries and electrochemical capacitors directly on a substrate. Our dispenser printer is a more viable fabrication method for making energy storage devices as opposed to typical casting processes, which require the battery or capacitor component(s) to be assembled and packaged separately from the device, as well as thin-film microfabrication approaches, which use deposition tools that are unable to deposit sufficient amounts of electrode material, therefore limiting the capacity of the system. With our printing system, we have been able to successfully demonstrate the construction and long term cycling of carbon based electrochemical capacitors (MCMB active material, PVDF and ionic liquid gel electrolyte/separator) as well as print lithium ion battery electrodes (MCMB, LiCoO 2 , Li4Ti 5 O 12 , LiMn 2 O 4 ), and gel-ionic liquid electrolytes. Printing can be used to tailor the thickness of electrodes and electrolytes of a capacitor or battery depending on a given application, and more complicated structures and geometries can be constructed in order to increase performance for a limited footprint area. This flexibility allows for the easy integration and customization of electrochemical storage components onto small device platforms for a given application. Battery electrode capacity tailored using dispenser printing Improved capacitor performance with higher surface area carbon 3.4 Modeling and Characterization of Dispenser Printed Thermoelectric Power Elements for Wireless Sensor Mike Koplow, PhD 2009 Advisor: Paul Wright Email: mkoplow@kingkong.me.berkeley.edu Publications Autonomous wireless sensor networks require long-lasting power solutions to realize long-term deployment in the field. The decreasing size and power consumption of these nodes enables the use of ambient energy sources (for example light, vibration, and heat) as power sources. This research explores the use of low-grade ambient heat sources (~10°C gradients) for power generation using thermoelectric power generators. Under applied temperature gradients (as low as a few degrees C), a 1 cm sized module can create DC power on the order of milliwatts with voltages up to a few Volts. Fabrication of these micro-scale devices requires hundreds of long, thin doped semi-conductor elements (~100 microns in diameter by 200 microns long) placed electrically in series and thermally in parallel. Traditional microfabrication techniques are ill suited to create cost-effective mass produced parts with these size requirements. Instead, a novel dispenser printing process is used to create the structures. This research investigates the materials processing and characterization of slurry based thermoelectric elements. SEM cross section of printed Antimony film Printed Antimony P type thermoelectric sample for materials characterization with silver contacts 3.5 Passive, Proximity-based AC Electric Current sensors for Residential and Commercial Loads Eli Leland, PhD 2009 Advisor: Paul Wright, Richard White Email: eli@me.berkeley.edu Publications Energy efficiency in residential and commercial buildings is viewed as the “low-hanging fruit” in regards to reducing overall energy use, greenhouse gas emissions, and dependence on fossil fuel energy sources. At present the end-use of electrical energy in homes and buildings is not understood in detail, and it is estimated that 10-30% of all electricity end-use is wasted “ghost load.” Energy-aware electric power networks and appliances in homes and buildings will enable significant reduction in energy enduse, but a cheap, compact current and voltage sensing solution is lacking in the marketplace. This project will develop the enabling sensor technology that can be combined with advances in wireless sensor networks to enable this energy efficiency and demand response technological vision. This research seeks to develop MEMS current sensors for residential and commercial environments, with a view to creating smart, energy-aware appliances and electric power networks downstream of the electric utility’s building meter. These MEMS current and voltage sensors should be self-powered, noncontacting, non-wraparound, small, and cheap. Ultimately they should be integrated or embedded into appliances or appliance power cables (“zip-cords”) themselves. The sensor design studied in this research consists of a piezoelectric cantilever with a permanent magnet mounted to its free end. When placed near a wire carrying AC current, magnetic coupling induces a sinusoidal force on the sensor magnet. This force deflects the piezoelectric cantilever, resulting in a sinusoidal voltage signal proportional to the current being measured. This sensor design is advantageous in that it requires no external power source (passive) and because it can accurately measure current while remaining electrically isolated from the current carrier (proximity-based). In the past year the microfabrication process for MEMS current sensor devices was developed and first prototypes were fabricated. Piezoelectric behavior of aluminum nitride cantilevers was verified. MEMSscale dispenser-printed magnets were successfully printed on to AlN cantilevers. SEM image of current sensor prototype Microfab process flow for current sensor 3.6 MEMS Piezoelectric Vibration Energy Harvesting for Wireless Sensor Networks Lindsay Miller, PhD 2011 Advisor: Paul Wright Email: lindsay@kingkong.me.berkeley.edu The goal of MEMS energy harvesting is to serve as an enabling technology for large, distributed wireless sensor networks by providing a maintenance-free, low-cost, low profile, replenishable power source for the network’s sensor nodes. Current wireless sensor network nodes are bulky, high maintenance, and expensive. MEMS energy harvesters allow for reductions in sensor node size, making the nodes un-obtrusive and suitable for small spaces. They reduce the time and expense associated with maintenance to change batteries because they provide a replenishable power source. They have the potential to provide cost savings, both from low bill of materials cost and from savings due to reduced maintenance labor. Applications of wireless sensor networks powered by MEMS energy harvesters include energy efficiency monitoring in buildings and vehicles, feedback and control of manufacturing processes, and management of patient information in hospitals. Recent progress in this research has resulted in the successful deposition of sol-gel PZT thin films on Pt/Ti/SiO2/Si substrates. This was a crucial step forward with respect to the mass manufacturability of these devices, as it allowed scale-up from 1cm2 chips to wafers of arbitrary size. The current PZT films have a piezoelectric coefficient of about 45 pm/V in the 11-direction. First-generation energy harvester prototypes have been fabricated from the sol-gel PZT films and successfully actuated by an input AC voltage. Power output testing, in which energy sinusoidal input vibrations excite harvesting devices, is currently underway. Approximately 0.1 µW/cm3 and 5 mV are expected from these devices. Work is in progress to improve the power output for second-generation harvesters by improving PZT film quality, optimizing device geometry, and adding a larger proof mass. Scanning electron micrograph of released trapezoidal cantilever beams with sol-gel PZT as the active layer. Scanning electron micrograph of cross-sectional view of 500 nm thick sol-gel PZT film. 3.7 Non-Contact Current Sensors for Power Distribution Christopher Sherman, PhD 2012 Advisor: Paul Wright, Richard White Email: ctsherman@berkeley.edu Project Background and Motivation: Presently, power operators have very little data in terms of realtime performance of the electric distribution grid. While overall load levels of the system are easily measured, localized data is typically unavailable due to the high cost of conventional sensor technologies. As a result, increased current draw due to loading changes or system problems may go unnoticed until a failure occurs. By adapting previously-developed non-contact current sensor technology in combination with readilyavailable wireless communications, it will be possible to produce inexpensive current sensors for distribution-level (25kV-40kV) power lines. By lowering the cost barrier to implementation, the sensors will allow the creation of a more intelligent power grid, enabling operators to make better informed realtime decisions. Progress Towards Solution: An aluminum test fixture has been developed, enabling testing of previously-developed non-contact current sensors on single-conductor wires at varying distances from the conductor. A signal conditioning board is used to convert differential signals from sensors to singleended signals readable by a Mote for transmission to a standard PC. Distance-dependent nonlinearities have been discovered and are presently in the process of being quantified by experimental and finite element analyses. 3.8 Sensor-based Cables For Underground Reliability of Electricity Infrastructures Zuoqian Wang, PhD 2013 Advisor: Paul Wright Email: zqwang@me.berkeley.edu The three year funded project by California Energy Commission mainly concerns underground power distribution cables. It seems like quite an ordinary topic but in fact, it poses a great challenge to the state of California, as well as utilities across the whole nation and the world. The thousands of miles of cables below ground for perhaps forty years are now aging rapidly and may finally come to failure. One of the main mechanisms of failure is the inception and development of trees roots in the insulation around the central conductors of the cable. Our primary goal is to gain a better understanding of the failure mechanisms and to develop an Intelligent Infrastructure to detect and evaluate various kinds of deterioration in cables using wireless sensing technologies. My research includes modeling electromechanical phenomena contributing to cable deterioration to indentify measurable property changes for the technology team. Based on the former graduate student Piero’s work, I have developed the AC environment simulation to see the electromagnetic field properties of the cable using COMSOL. I have also done simulation to see the elasto-plastic properties of the XLPE. The visco-elastic and fatigue simulations are also being conducted now to estimate the response of materials when undergoing permanent deformation. The other important work we are doing is micro-fatigue experiments on aged and new samples of XLPE at Lawrence Berkeley National Lab, which will verify the simulation and provide us with good vision to the material properties. The current along ground and conductor shields under ac environment The elasto-plastic properties of the poly-ethylene 3.9 Marco Vibration Harvesting Andrew Waterbury, PhD 2010 Advisor: Paul Wright Email: awaterbury@berkeley.edu Publications Energy harvesting extends the life of wireless sensor nodes which allows for longer deployments and greater application flexibility. One of several major sources of scavengable energy is ambient vibrations, but most of these vibrations occur at frequencies below 150Hz. To convert the mechanical oscillations into a useful electrical signal with piezoelectric materials or electromagnetic induction, a small mechanical structure that resonates at the target vibration frequency is necessary. The resonant structure amplifies the mechanical signal so that it can be converted to electrical energy. This research explores the design of structures on the order of a cm2 or less in footprint area that resonate at less than 150Hz and explores the use of those structures to convert from mechanical to electrical energy through electromagnetic induction. A multiple leg multiple turn beam geometry allows a central platform to resonate at target frequencies below 150Hz. The structure becomes a resonant generator by using the translating central platform to drive a generator based on the toothed architecture of variable reluctance motors. Analysis of the generator circuit indicates an upper bound power density of 4 - 8 mW-cm3 with a 1g input acceleration. Experimental results of a large scale prototype confirmed the trends of the modeling of the device, but the complexity of its assembly and some of the feature tolerances don’t enable the design to easily be scaled to cubic centimeter size. It can be scaled to a cube with 5cm sides, which is currently being pursued with a target application of harvesting large industrial vibrations. 3.10 Secure Infrastructure (Sensor‐Based Cable for Underground Reliability of Electricity Infrastructures) Qiliang Xu, PhD 2013 Advisor: Paul Wright, Richard White Email: qlxu@umich.edu Long distance underground distribution cables that operate at 12,000 volts or higher are likely to fail within a few nanoseconds after decades of operation. The unexpected electricity failure will lead to a catastrophic damage to both the electric power transmission systems and the commercial and residential consumers. The Secure Cable team is striving to develop an Intelligent Infrastructure to monitor in-situ maintenance and to explore the degradation of underground AC power distribution cables. Wireless sensing technologies have been introduced to discover deterioration in cables that might lead to failure. As a new member of the team, I have been attempting to establish a wireless sensing network (WSN) by integrating reliable and intelligent radio transceivers with the interdigital electric field sensors. Preliminary research has been conducted in another project led by Professor Richard White, named ‘Wiring the Cory Hall’ in which we want to monitor the power usage of Cory Hall, UC Berkeley by using the idea of the DUST WSN, an intelligent and novel network that can be powered by energy scavenging devices. Current and voltage sensors are desired to be placed at the front side of the circuit breakers in the electric panel box on each floor. Magnetic field in the vicinity of the circuit breaker has been carefully studied to identify the position where maximum gradient of the magnetic field is located. The piezoelectric sensor is able to pick up maximum signal at that particular location. The linear relationship between the current to be measured and the output voltage (shown in Figure) has been verified. Future work will focus on studying DUST WSN in greater depth and creating an interface device/circuit that connects the radios and sensors. 4. Leading Edge Circuits Technology 4.1 Energy-Efficient Supply-Regulated PLLs John Crossley, PhD 2011 Advisor: Elad Alon Email: crossley@eecs.berkeley.edu Ring-oscillator-based phase-locked loops for precision clock generation/multiplication are widely deployed in high-performance digital processors and high-speed serial communication links. Since ring oscillators are extremely sensitive to changes in their supply voltage, and since these loops are integrated into chips with significant digital functionality, reducing the effects of supply noise on the overall performance of these PLLs while maintaining low power dissipation is vital. Many charge-pump PLLs reduce the supply noise of the ring-oscillator by embedding a regulator between the high-impedance charge-pump output and the supply/control of the ring-oscillator. Placing the regulator in the loop forces the regulator to achieve high bandwidth in order to maintain the PLL stability - reducing the regulator's achievable supply rejection at a given power consumption. We will explore a method of improving both the supply rejection and overall efficiency of such PLLs by placing the regulator outside of the loop and controlling the oscillator frequency using digitally switched capacitors on the nodes of the ring oscillator. A digitally-controlled PLL requires a time-to-digital converter (TDC) in order to generate a digital phase-error signal. Digital PLLs usually use high-resolution TDCs to avoid excess output jitter from the TDC quantization noise but designing a high-resolution, low-power TDC is challenging. Our analysis of the digital PLL has shown that a low-resolution phase-detector, in combination with a low-bandwidth loop-filter, can achieve the same jitter performance as a high-resolution TDC with a high-bandwidth loop-filter. Proposed Digital-PLL TDC Resolution Tradeoff 4.2 Robust Design and Optimization of Deeply Scaled SRAM Zheng Guo, PhD 2009 Advisor: Borivoje Nikolic Email: zhengguo@eecs.berkeley.edu Publications Continued increase in the process variability is perceived to be a major challenge to future technology scaling. These effects are most pronounced in minimum-geometry devices used in SRAM cells and seriously limit the scalability of SRAM circuits beyond the 65nm node. To continue the investigation and modeling of future high density SRAM cache memory, over 6 sigma of parameter variability must be captured We have developed a large-scale read/write margin measurement methodology for characterizing stability in functional (~1Mb) SRAM arrays (Fig. 1). We have been able to investigate and measure systematic and random variations in large SRAM arrays and were also able to correlate large array measurements with measured data from padded-out single cell test structures. This methodology will help us to capture 6+ sigma of parameter variations and will benefit the investigation of future SRAM scalability. Fig. 1: Chip photo of the 45nm testchip (June 2007 Tape-out) 4.3 Detection and Compensation of SRAM Variations in Deeply Scaled CMOS Lauren Jones, MS 2009 Advisor: Borivoje Nikolic Email: ljones03@eecs.berkeley.edu As transistor dimensions continue to scale into the deep submicron regime, process variability is significantly impacting yield and performance, threatening future scaling. The impact of this variation on static random access memory (SRAM) is of particular interest, due to the large percentage of die area dominated by memory cells. With cache memories consisting of millions of cells, SRAM must tolerate variations of up to six sigma from the mean. Fluctuations in transistor parameters such as threshold voltage, gate length and effective width shift read and write margins and degrade cell stability. While new processing effects attempt to compensate for growing variations, their high cost motivates circuit based solutions for continued scaling. Recent studies in 45nm technology have shown systematic SRAM variation in mean read and write margins between alternating columns and rows. These studies suggest that layout variations due to processing effects cause structures that are physically mirrored across an axis to have different DC characteristics. It is likely that future scaling will increase this deviation. This presents a new challenge in variability compensation of SRAM arrays. We are exploring new techniques to sense variations in read and write margins on chip, and have developed methods to compensate for these asymmetries within memory arrays. Test structures will be implemented on a 45nm CMOS variability test chip. 45nm Variability Test Chip 4.4 Integrated Voltage Conversions for HighPerformance Digital ICs Hanh-Phuc Le, PhD 2012 Advisor: Elad Alon, Seth Sanders Email: phucle@eecs.berkeley.edu Web Page: http://www.eecs.berkeley.edu/~phucle/ High-performance CMOS digital ICs today operate in a power-limited regime at low supply voltage and high currents, thus requiring not only low supply impedance (~1mΩ in today’s 1V-100A microprocessors) but the ability to support multiple independent supply voltages on the die as well. To meet these requirements, we propose an architecture consisting of fully-integrated distributed switching converters. A switched-capacitor topology is chosen for the converter since on-chip capacitors in standard CMOS technologies have significantly higher Q and energy density than on-chip inductors. The proposed converter is comprised of an array of “standard-cells” which can be programmed to alter the converter’s topology and enable for variable voltage conversion ratios (1/2, 2/3 and 1/3 in this demonstration) for a range of output voltages (0.5V to 1.2V). In simulations of a 32nm SOI CMOS implementation (to be taped out as a test-chip), the converter achieves a peak efficiency of above 78% with 2V input and 0.9V output at a power density of 1W/mm2. Fig. 1. Eff. vs. Vout regulated by freq. (Vin=2V, br = 4%) Fig. 2. Layout of 1 standard cell • Tape-out: Dec. 2008 • Process: AMD 32nm SOI CMOS 4.5 Integrated Dynamic Power Supplies for SRAMs Kyoohyun Noh, PhD 2013 Advisor: Elad Alon Email: khnoh@eecs.berkeley.edu Scaling down on CMOS technology continues to benefit VLSI circuit design in terms of device speed and integration density. Supply voltage also has scaled down in parallel with the advancement of CMOS technology in order to maintain the device reliability. However, this has made it challengeable to control key parameters such as device threshold voltages due to random doping fluctuation. Thus, device variability has emerged a significant issue facing modern VLSI designers. This issue is particularly critical in SRAM designs since SRAM cells typically use more aggressive design rules to meet the stringent density requirements. Moreover, the demand for larger on-die memory in modern high performance systems leads to high leakage power in the memory arrays. While lowering the supply voltage is helpful to decrease the leakage power, the limited noise margins of some small number of cells often limits the minimum voltage to which the entire array can be scaled. In this project we are therefore exploring the use of integrated dynamic column-based power converters to compensate for variability. As shown by several research groups, dynamic supplies allow one to break the deadlock of traditional R/W margin sizing-based optimization and achieve minimal leakage power during standby mode. To implement these dynamic supplies we are focusing on integrated switched capacitor DC-DC converters to achieve high efficiency at acceptable area overhead. Fig.1 Integrated dynamic power supplies and Efficiency versus generated low supply voltage 4.6 Undergraduate Researcher Alex Pai, BS 2009 Advisor: Ali Niknejad Email: alexpai@berkeley.edu I am currently working on the TUSI project. This project seeks to create a UWB microwave medical imager. My current contribution to this project is to develop a testbench for characterizing a virtual antenna array, as well as to develop a 3D reconstruction algorithm. I am also aiding with designing a CMOS frequency divider for the circuits implementation of this project. 4.7 The Design of Baseband Circuits for a HighSpeed Wireless Receiver Ji-Hoon Park, PhD 2010 Advisor: Borivoje Nikolic Email: overlord@eecs.berkeley.edu The recent advances of the CMOS RF technology paved the way to commercially viable wireless communication systems working at multi-Gbps rate. The design of baseband circuits, however, still remains challenging because of its high data and sampling rate. The high sampling rate means that the system sees a large delay spread, which is hard to synchronize and demodulate. On the other hand, because the circuit power consumption is proportional to the data rate, reducing the power consumption of these systems is a major issue especially for a portable system. The purpose of my research is to develop algorithms and circuits for the multi-Gbps wireless receiver that can support multi-level modulations with as low power consumption as possible even in non-line-ofsight propagation conditions . Specifically, I've been working on high-speed, power-efficient carrier/timing recovery and equalization working in the WPAN environment. The research includes evaluation and development of algorithms and architectures, a proper partition between analog and digital circuits, and the VLSI implementation of the blocks. The Baseband Architecture 4.8 Circuit Models of Nano-Mechanical Relays Matthew Spencer, PhD 2013 Advisor: Elad Alon Email: mespence@berkeley.edu Traditionally, transistor scaling has improved both device speed and energy consumption. However, the threshold voltage of the transistors, and consequently their power supply voltage, can no longer be scaled without actually increasing the total power dissipation due to leakage current. This has led to an increase in power consumption and a rapid increase in chip power density. In order to circumvent this limitation, a new device with more ideal switching characteristics (specifically, a sharper sub-threshold slope) is necessary. To that end, we are currently researching nano-mechanical relays built from electrostatically actuated cantilevers. Since they can potentially eliminate leakage completely, these devices, at least in simulation, seem to be capable of comparable delay to subthreshold CMOS digital circuits with an order of magnitude less energy per operation and comparable area. Realizing these benefits in actual circuits requires a firm understanding of the underlying physics of the devices and how they impact the electrical behavior. In order to achieve this physical understanding, we are developing two types of models of the device behavior: simplified equations that are suitable for hand analysis of large systems, and compact models for computer simulation. As with CMOS designs, the simplified models are necessary to grant designers intuition for circuits and systems made of these devices, and the detailed computer models are necessary to simulate and verify their behavior. The key challenge in developing these models is that they must potentially capture complex physical phenomena such as switch bounce and quantum tunneling - both of which could alter the effective delay – and surface adhesion, which limits the minimum required energy per operation. A simplified model of the switch. Two switches actuating and bouncing in response to an input. 4.9 Background Calibrated Pipeline ADC Dusan Stepanovic, PhD 2012 Advisor: Borivoje Nikolic Email: balkanac@bwrc.eecs.berkeley.edu This research project investigates how low-power high-speed analog-to-digital converters for future digital communication systems can be built in modern digital processes. As the most promising in the range of moderate resolutions, the pipelined architecture was chosen. To decrease the power of the pipelined A/D converter a simple single stage OTA is used. However, due to low intrinsic gain of devices in modern technologies, the required gain cannot be achieved with a single stage gain, and some form of correction must be employed to recover from errors caused by the finite gain of the amplifiers. A slow, low-power and accurate sigma-delta converter is used to provide a reference signal for the calibration algorithm. In order to leave the analog path intact, so the converter can run without interruptions, we perform the calibration completely in digital domain using LMS algorithm. Nonlinear LMS filtering is used to correct for the nonoinearities originating from the finite gain of the amplifiers. 4.10 Stochastic Optimization of SRAM Arrays for Dynamic Performance Seng Toh, PhD 2010 Advisor: Borivoje Nikolic Email: sengoon@eecs.berkeley.edu Publications Dynamic SRAM performance is becoming more important in deeply scaled CMOS technologies where performance and reliability need to be maintained in the face of increasing process variation. Designing SRAM arrays based on margins derived from static performance of individual SRAM cells results in pessimism, thus causing overdesign or failure in meeting specifications. We are developing models of dynamic SRAM performance which allow stochastic optimization of the entire SRAM array. These models will be fitted to actual dynamic SRAM performance measured from a 45 nm testchip. To accomplish this, we have developed circuits for generating a high bandwidth pulse, on-chip, with picosecond pulse-width resolution. This pulse generator allows us to directly measure dynamic SRAM metrics from large arrays with excellent precision. High precision pulse generator 45 nm testchip characterizing dynamic SRAM performance 4.11 Using Ring Oscillators to Dynamically Characterize SRAM Cells Jason Tsai, MS 2009 Advisor: Borivoje Nikolic Email: jasontsai@berkeley.edu Determining accurate noise margins for SRAM functionality becomes increasingly crucial as they shrink with the scaling of device dimensions and power supply voltages. Most conventional methods employ static measurements to extract relevant parameters to determine the corresponding static noise margins. In contrast, my research focuses more on a dynamic approach by examining transient rather than steady state parameters. This is accomplished by utilizing custom ring oscillators to read from and write into SRAM cells and then correlating their oscillation frequencies to meaningful performance metrics. I demonstrate through SPICE and Monte Carlo simulations in 45nm technology that it is possible to achieve a correlation coefficient of more than 0.9 in both read and write scenarios. Layout of Ring Oscillator Block Schematic of ROs to characterize SRAM robustness 4.12 RF Receiver Architectures for Deeply-scaled Submicron CMOS Technology Renaldi Winoto, PhD 2009 Advisor: Borivoje Nikolic Email: winoto@eecs.berkeley.edu Resume: http://www.eecs.berkeley.edu/~winoto/resume Publications Current advancements in wireless receiver technology are primarily driven by (i) the need for integration of radio, A/D and digital baseband processor on a single CMOS die, and (ii) the demand for low-power multi-standard capable receivers. The goal of this research is to investigate novel receiver architectures that are amenable to modern CMOS processes. In doing so, we need to adapt designs to take greater advantage of the benefits offered by state-of-the-art CMOS devices, while avoiding their shortcomings. In this project, our focus will be in processing an RF signal using a discrete time ΣΔ modulator. The RF signal is first downcoverted using a current-commutating mixer with a single capacitor as the output load. This capacitor forms the first stage of a two stage passive switched capacitor filter that makes up the ΣΔ modulator loop filter. The switched-capacitor filter is run at radio frequencies which gives rise to a large oversampling ratio. Availability of very good switches is one of the advantages of scaling, as for a given on-resistance; the parasitic capacitance of MOS switch becomes increasingly smaller. System Diagram Chip Photo 4.13 BSIM Nano-scale Multi-gate CMOS Modeling James Yao, PhD 2014 Advisor: Ali Niknejad, Chenming Hu Email: yaoshijing@gmail.com As CMOS scaling is approaching its limits, multi-gate MOSFET is generating tremendous interest as a possible alternative to the conventional bulk MOSFET. An analytic model for DG MOSFET will enable the circuit design community to evaluate DG MOSFET and use it in various applications. Currently, all the models address only common gate (both gates tied together) operation of a symmetric undoped device. There is a strong need to develop a model for a doped symmetric common device. In this work, a new surface-potential based model is developed which incorporates the effect of finite body doping on the electrical characteristics of the transistor. Starting from a symmetric DG-FET framework, the model is extended to tri-gate FETs using 3D modeling of SCE. Substrate current model enables the modeling of both SOI FinFETs, and bulk FinFETs. A full-fledged compact model BSIM-CMG has been developed through incorporation of additional physical effects and leakage currents. The model has been verified against TCAD and experimental MG-FET data for long and short channel lengths. Accurate fitting to drain current (Id), transconductance (gm), gm-efficiency (gm/Id), and output conductance (gds) are observed indicating the model efficiency towards digital and analog design applications. To demonstrate the use of this model, we will continue to explore the simulation of FinFET-based circuits using BSIM-CMG. One example is the variability study of FinFET-based SRAM cells. Common and Independent DG-FETs fabricated on bulk-Si and SOI I-V model verification 4.14 Design of High-throughput LDPC Decoders Zhengya Zhang, PhD 2009 Advisor: Borivoje Nikolic Email: zyzhang@eecs.berkeley.edu Publications Low-density parity-check (LDPC) codes have been demonstrated to perform very close to the Shannon limit when decoded iteratively. Sometimes excellent performance is only observed up until a moderate bit error rate (BER); at a lower BER, the error curve often changes its slope, manifesting a so-called error floor. Such error floors are a major factor in limiting the deployment of LDPC codes in high-throughput applications. We design a parallel-serial architecture to map the decoders of structured LDPC codes to a hardware emulation platform. Experiments in the low BER region provide statistics of the error traces, which are used to investigate the causes of the error floors. Different classes of errors cause error floors. But even with an optimal implementation, the error floors are inevitable due to certain combinatorial structures of the LDPC code, termed absorbing sets. The effect of absorbing sets in determining the error floor level is influenced by implementation. Conventional decoder implementations tend to induce low-weight weak absorbing sets, and, as a result, elevate the error floor. We propose alternative quantization schemes and demonstrate seemingly inferior algorithms that alleviate the effects of weak absorbing sets. Furthermore, we can exploit the structure of absorbing sets with a redesigned message-passing decoder to escape such local minimum states. The investigative approach and ASIC design approach are unified using a Simulink-based design flow. Rapid prototyping allows us to concurrently explore the algorithmic, architectural and implementation spaces in order to optimize the decoder design. Lowering LDPC error floor with a post-processor using a weighted message-passing algorithm 5. Reconfigurable Systems 5.1 Research Accclereator for Multiple Processors Greg Gibeling, PhD 2010 Advisor: John Wawrzynek Email: gdgib@berkeley.edu Web Page: http://www.cs.berkeley.edu/~gdgib Publications Research Accelerator for Multiple Processors (RAMP) aims to create cross platform architectural simulators for community research, which are orders of magnitude faster than current solutions. We hope to use FPGAs (e.g. on the BEE3 and ML505 boards) to provide simulators which are fast enough for interactive use, and software development. The first RAMP system, RAMP Blue, was a message passing multicore built around the Xilinx MicroBlaze CPU. This system was scaled to over 1000 CPUs in a single rack. RAMP Blue was released in early 2008 along with the final versions of RDLC2, the compiler for the RAMP Description Language, which was used in the implementation of RAMP Blue. With RAMP Blue complete we have put the development of RDL and RDLC3 on hold in order to focus on RAMP Gold. RAMP Gold is the second generation of RAMP systems from U.C. Berkeley and is being developed in conjunction with BWRC and the ParLab, a new research lab in parallel computing. RAMP Gold will be a multicore SPARC ISA simulator including, at the outset, a very simple timing model and high parallelism. We will eventually extend RAMP Gold to include more complex and accurate timing models, as well as architectural features tailored to the work in ParLab. RAMP Gold with thus serve not only as a simple experiment in simulator design but also a useful architectural simulation platform. Eventually we hope to generalize the techniques in RAMP Gold for application in a much wider range of simulators. RAMP Gold Layering 5.2 Channel Adaptive High-Speed Link Design Kwangmo Jung, PhD 2013 Advisor: Elad Alon Email: kwangmo@eecs.berkeley.edu The energy expended on communication among different parts of the digital systems at the core of the modern communication infrastructure is becoming both a significant cost factor and a performance limiter. One of the largest contributors to the energy consumption of these interconnects (including backplane links, optical drivers, and memory interfaces) is that today all of these links are designed to ensure a low bit-error-rate (BER) over the worst possible conditions. Thus, even if the actual channel seen by a link is typical or better than expected, the BER will be significantly lower than required, and the power consumption is largely unchanged from the case of the worst-case channel. If these links that operate under better conditions could instead be reconfigured to reduce its power and increase their BER back to only the required level, the power consumption of the system can be drastically reduced without any impact on performance. To achieve the goal of implementing links that reconfigure and optimize themselves based on their actual operating environment, we are first developing a framework to analyze link performance and power as a function of the link’s architecture and configuration. This framework will be leveraged to find the power-optimum link architecture and settings for a given channel/BER requirement. This analysis will not only point to optimal designs, but will provide insight into the methods by which fabricated links parameters can be optimized and reconfigured adaptively. 5.3 Toward Optimal Sound Reproduction: Closing the Acoustic Loop Alexander Krasnov, PhD 2010 Advisor: John Wawrzynek Email: akrasnov@eecs.berkeley.edu Publications The formulation of wave fields in terms of differential equations naturally leads to two interesting problems. The forward problem determines the scattered field given the incident field and the material properties. The inverse problem determines the material properties given the incident and scattered fields. The problems and solutions are nearly isomorphic for various fields with second-order space-time dependence: electromagnetic, acoustic, elastic. The numerical modeling of these fields in turn benefits many open application areas: chip and antenna design, seismic prediction and exploration, biomedical imaging, sonar and radar. In most cases, high speed and quality cannot be simultaneously achieved in current systems due to excessive d computational requirements, typically at least O(n ) for volumes with linear size n and dimensionality d. In order to advance the state of the art in the immediate future, we plan to combine commodity transducer and computing technologies with recent developments in modeling algorithms in a practical system. Without loss of generality, we limit our attention to another open application area: room acoustics. Here, the guiding goal is optimal reproduction of sound pressure fields in enclosed volumes. Efficient forward and inverse models are critical for implementing closed-loop control, missing from current systems. We recently demonstrated that such control can optimize the fields in subvolumes of interest, e.g., around listeners, in the presence of strong scatterers, e.g., other listeners. A reformulation of wave fields in terms of source-type integral equations limits computation to subvolumes of interest and, therefore, provides elegant and effective solutions to the forward and inverse scattering problems. We are currently developing efficient implementations of these solutions on commodity parallel architectures, likely combining CPUs and GPUs. Since room acoustics is among the hardest instances of the general problem due to very large material contrasts, our results are directly transferable to other application areas. Magnitude of optimized sound pressure field from linear transducer array. 5.4 Hardware/Software Co-Tuning for Multiprocessors Marghoob Mohiyuddin, PhD 2010 Advisor: John Wawrzynek Email: marghoob@eecs.berkeley.edu Traditional approaches to hardware design space exploration use benchmark codes to guide the design process. However, due to the inability of compilers to optimally tune code for emerging processor designs, static benchmarks are poor indicators of the performance potential of an architecture design. In this work, we propose hardware/software co-tuning as a novel approach for system design, where tradition architecture space exploration is tightly coupled with software auto-tuning to deliver significantly improved area and power efficiencies. The proposed methodology has been applied to three kernels from scientific computing---sparse matrix vector multiplication, dense matrix multiplication and stencil operation on the Stanford Smart Memories architecture using a software-based architecture simulator. Results show significantly improved power efficiency, which is important for high performance computing systems. Future work will use RAMP as the hardware simulation platform to explore a much larger design space. Improvement in power efficiency of optimal configuration (over traditional method of designing hardware using naive code) as the contribution of sparse matrix vector multiplication (SpMV), dense matrix matrix multiplication (GEMM) and stencil is varied. GEMM is implicit as the third axis (the sum of fractions from all the kernels is 1). The hardware design space varied DRAM bandwidth (0.8-3.2 GB/s), number of cores (1,4,16), data cache/private memory available (16/32/64/128 KB). 6. Ultra-low Power Wireless 6.1 Ultra-low Energy Logic Using Sense Amplifier-based Pass Transistor Logic (SAPTL) Louis Alarcon, PhD 2009 Advisor: Jan Rabaey Email: lalarcon@bwrc.eecs.berkeley.edu Web Page: www.eecs.berkeley.edu/~lalarcon Publications The SAPTL [1] is an alternative circuit topology that allows the reduction of energy per operation via voltage scaling even in the presence of leakage. It allows aggressive voltage scaling since the threshold voltage of the pass transistor network (the stack) can now be decoupled from its standby leakage energy. This allows for very low threshold voltages and thus allowing the stack transistors to remain in the super threshold region even at supply voltages of around 300mV. In addition, the differential signaling used by the SAPTL lends itself to synchronous and asynchronous operation and the inherent layout regularity points to the SAPTL as a very good candidate for robust ultra low energy operation. [1] L. Alarcón, T.-T. Liu, M. Pierson, and J. Rabaey, "Exploring Very Low-energy Logic: A Case Study", Journal of Low Power Electronics, vol. 3, no. 3, pp. 223–233, Dec. 2007 The energy-delay characteristics of SAPTL implementations of a CRC circuit and an 8x8 multiplier. The SAPTL architecture and the corresponding energy-delay characteristics of the various synchronous and asynchronous timing schemes, as compared with static CMOS and DCVSL implementations. 6.2 Ultra-low Power Transmitter for Biomedical Implants Yuhui Chen, PhD 2010 Advisor: Jan Rabaey Email: chen05@eecs.berkeley.edu Research in recent years has demonstrated the possibility of deploying wireless technology in a number of sensor networks. From the perspective of the communication link, a class of these applications possesses extreme asymmetry between receiver and transmitter. While the receiver is allowed to have higher power and larger size, the transmitter (a.k.a. transponder) is typically an integrated part of the sensor node and is subject to stringent power and size constraints. Examples of such applications include automotive and biomedical implants. This project seeks to explore the design opportunities presented by link asymmetry. Design parameters at both system and circuit levels are under careful study. While the choice of architecture may be scaled for a range of other applications, the primary objective is to develop an ultra low-power wireless transmitter for biomedical implants. Block Diagram of a Reflective Impulse Transmitter An Implanted Sensory Node for Brain Machine Interface 6.3 A Communication System for CM-range Wireless Data Transfer Simone Gambini, PhD 2009 Advisor: Jan Rabaey, Elad Alon Email: sssimone@eecs.berkeley.edu Publications In this research, we are exploring a communication system optimized for 5-cm range wireless communication. Such a system could be used in ultra-dense wireless sensor networks, communication between 3D integrated systems, and low-cost packaging/assembly. The system is optimized for energy efficiency by using pulse based transmission and choosing a carrier frequency that results in amplitudes large enough that the receiver can employ a simple AMdetector for down conversion. The interference susceptibility of the AM-detector is mitigated by using an adaptive scheme that employs Trellis-Coded-Modulation to estimate the B.E.R. in real time. When an outage due to a close-in interferer is detected, the receiver switches to a mixerbased mode of operation. The transceiver system is prototyped in a 65nm Low Power CMOS process, targets an energy dissipation lower than 60pJ/Bit, occupies less than 640x640um and does not require a precision clock for operation. A 1.4xcm x 1.4cm FR4 antenna with 3-10GHz bandiwdth is also realized, showing the realizability of a complete short range transmission system with small size and low cost. Prototype Chip Microphotograph and Transmitted Pulse Capture 6.4 Synchronization in Sensor Network On Chip Ping-Chen Huang, PhD 2012 Advisor: Jan Rabaey Email: pchuang@eecs.berkeley.edu This project explores communication/clocking design in sensor-network-on-chip applications, where no centralized clocking is present and the network is usually configured hierarchically. The goal is to achieve reliable communication with the least power/cost from the synchronization perspective. As the interconnects between nodes can be considered as communication links, a synchronization block will be needed in each link. The focus is on the optimization of the total power of the link among different synchronization schemes. The power on the link can be further minimized with reduced voltage. The following figure shows the optimization of the voltage swing on a 0.5um x 1mm link in UMC 90nm technology. 6.5 Low-energy Computation Using Self-timed Pipelining Tsung-Te Liu, PhD 2010 Advisor: Jan Rabaey Email: ttliu@eecs.berkeley.edu Publications Sense amplifier-based pass-transistor logic (SAPTL) is a promising candidate to realize ultra-low energy computation without soliciting sub-threshold operation and sacrificing performance. The asynchronous self-timed methodology can potentially apply to SAPTL architecture with very little overhead to further improve the energy-delay performance as well as reliability. The overall research focuses on the architectural optimization and design strategy for self-timed SAPTL in system level. The signal processing prototypes implemented by proposed design methodology and traditional CMOS flow will be used for final performance comparison. Self-timed SAPTL test chip 6.6 Powering Implanted Wireless BrainMachine Interfaces Michael Mark, PhD 2010 Advisor: Jan Rabaey Email: markm@eecs.berkeley.edu Web Page: http://www.eecs.berkeley.edu/~markm/ Publications The concept of implanted brain-machine interfaces (BMI) has gathered a lot of momentum in the past years. Ideally these devices operate completely wirelessly making any wires through the skin obsolete to reduce any risk of infection and increase the patient`s comfort at the same time. The potential impact of such interfaces is absolutely huge, leading from advanced prosthetics over micro-stimulation for treatment of certain brain illnesses to complete new user interfaces. Researchers at various institutions have already made major progress in the implementation of electrode arrays, signals acquisition techniques and communication links. One big challenge that is often overlooked though is how to power such devices. The size of an implant is ideally dictated by the size of the electrode array which can vary between 1 – 100 mm², depending on the application and kind of electrode. The goal of this research is to determine the maximum available power for a given overall size constraint in the range of 1x1 – 10x10 mm² and build systems in standard 65nm CMOS that deliver this power to the implant. Block Diagram of a Generic Wireless Neural Implant A possible application: A fully implanted wireless BMI used to control an arm prosthesis 6.7 Power and Area Efficient Neural Signal Acquisition Front-End Rikky Muller, PhD 2012 Advisor: Jan Rabaey Email: rikky@eecs.berkeley.edu The realization of a fully implantable brain-machine interface (BMI) chip will enable life-changing opportunities such as the development of motor prosthetics. The signals of interest, action and local field potentials, run at biological timescales in the range of 1-10kHz and can be as small as 10uV, which presents the challenge of low signal to noise ratio (SNR) at the sensor input. Thus a low-power low-noise signal acquisition front-end is critical to any brain-machine sensor array interface to amplify and convert the neural data for digital signal processing. A significant amount of work has been devoted to this problem over the last decade; however, the prior art has relied heavily on analog techniques and passives to perform signal conditioning and filtering, which significantly impacts die area and does not result a scalable solution. We propose an architecture in a fine-line process, which uses feedback from the digital domain to set filter pole locations thereby eliminating the need for the integration of large passive components. Combining oversampling acquisition and digital signal processing in a reconfigurable system can result in significant implant power and area reduction. Fig. 1: System Block Diagram 6.8 A MEMS Filter Bank Receiver Jesse Richmond, PhD 2010 Advisor: Jan Rabaey Email: jar@eecs.berkeley.edu A popular vision among many in the field of wireless communications has been to achieve ubiquitous communications, in which nearly everything we interact with is connected wirelessly to a network. Such a system could have applications ranging from biomedical ones, such as implantable sensors, to smart houses that can track their occupants’ presence and automatically adjust such things as lighting, temperature, and music or video to suit the individuals’ preferences. In both instances, the radios that comprise the network must consume very little energy, to allow long battery life or operation using energy scavenged from the environment, and must be very small in size to permit them to disappear into the environment. This project aims to provide a highly integrated, extremely low power radio that would be suitable for this type of application. The performance of traditional wireless receivers is limited in a large part by the lack of a narrow bandwidth, low loss, and reconfigurable filter at the RF band, which leads to designers needing to use circuit techniques to ensure adequate linearity and allow channel selection. Recent developments in high quality micromechanical resonators enable new circuit designs featuring ultra-low power consumption and an extremely small size. The system will be based around an array of filters with individual ultra low power receivers to perform sub-carrier separation and allow a multi-tone, OFDM-like signal to be received in the analog domain, enabling reliable and flexible wireless reception. A reconfigurable digital baseband will be used to allow the receiver to operate using a wide variety of configurations between the channels, allowing the user to change the performance characteristics, such as sensitivity and data rate, at run time. Block diagram illustrating the multi-tone receiver concept. 6.9 Low Power Active RFID TAG Wenting Zhou, PhD 2013 Advisor: Jan Rabaey Email: wtzhou@eecs.berkeley.edu Unlike passive tag, active RFID tag contains a small power source and some active circuitry to extend the range or provide extra functionality, thus it can achieve higher sensitivity, larger communication range as well as enable new applications. One example is a remote sensor that can be queried, not by a dedicated reader, but instead with a general-purpose wireless device like a mobile phone. Our low power active RFID tag is based on the idea of asynchronous wake-up by adding an auxiliary receiver called a wake-up receiver (WuRx) to every tag. WuRx takes the place of timer in traditional duty-cycle based methods, continuously monitoring the channel for communication requests or wake-up signals. The use of WuRx breaks the trade-off between latency and average power assumption. Our WuRx only consume 52uW and it makes tag respond immediately to requests, thus latency is effectively eliminated. The protocol design is mainly based on ISO Active RFID protocol, using packet format, randomnumber based collision arbitration and following the entire command format. However physic layer is redesigned by using on-off-keying (OOK), 2 GHz central frequency, 27.5 kHz symbol rate and shorter wake-up sequence. Digital synchronization method is used to simplify the analog circuitry. ADC oversamples the signal at 8 times to meet the resolution requirement. Also 3 bytes preamble is added every packet for amplitude and timing estimation. Block Diagram of Tag PUBLICATIONS – 2008 To search specific listings visit: http://bwrc.eecs.berkeley.edu/php/pubs/pubs.php • • • • • • • • • • • • • • • • • • • • • • • Beyond the Third Generation of Wireless Communications, Jan M. Rabaey, November, 2008 A Revenue Enhancing Stackelberg Game for Owners in Opportunistic Spectrum Access, Ali Ozer Ercan, Jiwoong Lee, Sofie Pollin, Jan Rabaey, Proceedings of DySPAN'08, October, 2008 Exploiting Interference Diversity for Event-Based Spectrum Sensing, Arash Parsa, A. Gohari Amin, Anant Sahai, IEEE Symposium on Dynamic Spectrum Access Networks (DySPAN), October, 2008 Integrated Regulation for Energy-Efficient Digital Circuits, Elad Alon, Mark Horowitz, IEEE Journal of Solid-State Circuits, 43, 8, 1795-1807, August, 2008 A Tapered Cascaded Multi-Stage Distributed Amplifier with 370GHz GBW in 90nm CMOS, Amin Arbabian, Ali Niknejad, Radio Frequency Integrated Circuits Symposium 2008, IEE RFIC, 57-60, June, 2008 Software-Defined Radio, Kees Van Berkel, 29, 2, June, 2008 Recovering Energy for Flexible Mobile Computing, Farhana Sheikh, 29, 2, June, 2008 Research Highlights: From Technology Explorations to Wireless Systems, Borivoje Nikolic, 29, 2, June, 2008 An Ultra-Low-Power Power Management IC for Energy-Scavenged Wireless Sensor Nodes, Michael Seeman, Seth Sanders, Jan Rabaey, IEEE 39th Power Electronics Specialists Conference Proceedings, PESC, 925-931, June, 2008 Transformer-Coupled Power Amplifier Stability and Power Back-Off Analysis, Debopriyo Chowdhury, Patrick Reynaert, Ali Niknejad, IEEE Transactions on Circuits and Systems—II: Express Briefs, 55, 6, 507-511, June, 2008 A 2.5mW Inductorless Wideband VGA with Dual Feedback DC-Off-set Correction in 90nm CMOS Technology, Yanjie Wang, Bagher Afshar, Tuan-Yi Cheng, Vincent Gaudet, Ali Niknejad, Radio Frequency Integrated Circuits Symposium 2008, IEEE RFIC, 91-94, June, 2008 Broadband Variable Passive Delay Elements Based on an Inductance Multiplication Technique, Ehsan Adabi, Ali Niknejad, Radio Frequency Integrated Circuits Symposium 2008, IEEE RFIC, 445-448, June, 2008 Low Power Wireless Systems, Jan Rabaey, 29, 2, June, 2008 New Directions in RF and mm-Wave Research, Ali Niknejad, 29, 2, June, 2008 Implantable Self-Powered Sensors, Paul Wright, 29, 2, June, 2008 Direct Waveform Synthesis for a Cognitive Radio Transmitter, Stanley Chen, 29, 2, June, 2008 Circuits and Techniques for a Dual-Mode, Energy Efficient Centimeter Range Wireless Communication Link, Simone Gambini, 29, 2, June, 2008 Microscopic Wireless, Jan Rabaey, 29, 2, June, 2008 Research Update: Energy Efficient Design, Elad Alon, 29, 2, June, 2008 Information Flow Over Wireless Networks: A Deterministic Approach, A. Salman Avestimehr, 29, 2, June, 2008 Measure of Variability in 45 nm CMOS Circuits, Liang-Teck Pang, 29, 2, June, 2008 A 60 GHz Fully Integrated Transceiver in 90nm CMOS, Debopriyo Chowdhury, Bagher Afshar, 29, 2, June, 2008 Design and Optimization of an MB-OFDM Ultra-Wideband Receiver Front-End, Yanmei Li, Chang-Ching Wu, Alberto Sangiovanni-Vincentelli, Jan Rabaey, 4th IEEE International Conference on Digital Object Identifier, Circuits and Systems for Communications, 502-506, May, 2008 74 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • A 5.8 GHz 1 V Linear Power Amplifier Using a Novel On-Chip Transformer Power Combiner in Standard 90 nm CMOS, Peter Haldi, Debopriyo Chowdhury, Patrick Reynaert, Gang Liu, Ali Niknejad, IEEE Journal of Solid-State Circuits, 43, 5, 1054-1063, May, 2008 A Highly Linear Broadband CMOS LNA Employing Noise and Distortion Cancellation, WeiHung Chen, Gang Liu, Boos Zdravko, Ali Niknejad, IEEE Journal of Solid-State Circuits, 43, 5, 1164-1176, May, 2008 RDLC2: The RAMP Model, Compiler & Description Language, Greg Gibeling, University of California, Berkeley, May, 2008 A CMOS IR-UWB Transceiver Design for Contact-Less Chip Testing Applications, Yanjie Wang, Ali Niknejad, Vincent Gaudet, Kris Iniewski, IEEE Transactions on Circuits and Systems—II: Express Briefs, 55, 4, 334-338, April, 2008 Digital Circuit Design Trends, Mark Horowitz, Donald Stark, Elad Alon, IEEE Journal of SolidState Circuits, 43, 4, 757-761, April, 2008 Statistical Compact Modeling of Variations in Nano MOSFETs, Chung-Hsun Lin, Mohan Dunga, Darsen Lu, Ali Niknejad, Chenming Hu, International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA, 165-166, April, 2008 Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic, Tsung-Te Liu, Louis Alarcon, Matthew Pierson, Jan Rabaey, 14th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC, 105-115, April, 2008 Fully Integrated CMOS Power Amplifier with Efficiency Enhancement at Power Back-Off, Cong Liu, Peter Haldi, Tsu Jae King, Ali Niknejad, IEEE Journal of Solid State Circuits, 43, 3, 60-70, March, 2008 Nanoscale CMOS Modeling, Mohan Dunga, University of California, Berkeley, March, 2008 A 2GHz 52µW Wake-Up Receiver with -72dBm Sensitivity Using Uncertain-IF Architecture, Nathan Pletcher, Simone Gambini, Jan Rabaey, IEEE International Solid-State Circuits Conference, 525-526 and 633, February, 2008 A Robust 24mW 60GHz Receiver in 90nm Standard CMOS, Bagher Afshar, Yanjie Wang, Ali Niknejad, IEEE International Solid-State Circuits Conference, Session 9, 6-8, February, 2008 BEE Project Update, John Wawrzynek, 22, 7, January, 2008 Keynote Address: Connecting Everybody to Everything, Bob Lanucci, 22, 7, January, 2008 Connectivity Brokerage for Spectrum Utilization, Ali Ozer Ercan, 22, 7, January, 2008 Challenges in IC Design for Measurement Instruments, Ken Nishimura, 22, 7, January, 2008 Embracing Uncertainty: Design for Correction in RF Instruments and Circuits, Joel Dunsmore, 22, 7, January, 2008 Robust Spectrum Sensing in Low SNRs, Rahul Tandra, 22, 7, January, 2008 Leading Edge Circuits Technology Research Update, Elad Alon, 22, 7, January, 2008 Interfacing the Brain: Current Trends in Neural Engineering, Jose Carmena, 22, 7, January, 2008 Spectrum Wars, John Notor, 22, 7, January, 2008 Research Highlights: Leading-Edge Circuits, Borivoje Nikolic, 22, 7, January, 2008 Design of LDPC Decoders for Low Error Rate Performance, Zhengya Zhang, 22, 7, January, 2008 Sigma-Delta Receiver, Renaldi Winoto, 22, 7, January, 2008 FLEET Update, Ivan Sutherland, 22, 7, January, 2008 Microscopic Wireless for Biomedical Applications, Michael Mark, 22, 7, January, 2008 An Ultra-low Power Wake-up Receiver Using Uncertain-IF Architecture, Nathan Pletcher, 22, 7, January, 2008 A UWB Receiver for Intelligent Tires, James Wu, 22, 7, January, 2008 Micro-manufacturing of Wireless Systems, Paul Wright, 22, 7, January, 2008 Wideband Circuits in 90nm CMOS, Amin Arbabian, 22, 7, January, 2008 75 • • • • • • • • • • • • • • • • • • • • • A 1Gbps Mixed-Signal Analog Front End for a 60GHz Wireless Receiver, David Sobel, 22, 7, January, 2008 Microscopic Wireless and Related Stories in Ultra-low Energy and Ubiquitous Wireless, Jan Rabaey, 22, 7, January, 2008 Content Management and Replication in the SNSP: A Distributed Service-based OS for Sensor Networks, Jana Van Gruenen, Jan Rabaey, IEEE CCNC (Consumer Communications and Networking Conference), 655-659, January, 2008 Design in the Power-Limited Scaling Regime, Borivoje Nikolic, IEEE Transactions on Electron Devices, 55, 1, 71-83, January, 2008 Low-swing Interconnect Interface Circuits, Hui Zhang, Jan Rabaey, 2008 A Baseband Mixed-Signal Receiver Front-End for 1Gbps Wireless Communications at 60GHz, David Amory Sobel, University of California, Berkeley, 2008 A Brand New Wireless Day, Jan Rabaey, Design Automation Conference, 2008, 2008 A 60GHz 1V +12.3dBm Transformer-Coupled Wideband PA in 90nm CMOS, Debopriyo Chowdhury, Patrick Reynaert, Ali M. Niknejad, 2008 IEEE International Solid-State Circuits Conference, 2008 A Broadband Distributed Amplifier with Internal Feedback Providing 660GHz GBW in 90nm CMOS, Amin Arbabian, Ali Niknejad, 2008 IEE International Solid-State Circuits Conference, 2008 Ultra-low Power Wake-Up Receivers for Wireless Sensor Networks, Nathan Michael Pletcher, University of California, Berkeley, 2008 RAMP Blue: A Message-passing Manycore System as a Design Driver, Alex Krasnov, University of California, Berkeley, 2008 Energy-performance Optimization of Synthesized Digital Integrated Circuits, Seng Oon Toh, University of California at Berkeley, 2008 Circuits for Measurement of Flip-flop Performance Variability, Kenneth Duong, University of California, Berkeley, 2008 Digitally Calibrated Analog-to-Digital Converters in Deep Sub-micron CMOS, Cheongyuen William Tsang, University of California, Berkeley, 2008 Efficient Programming of Reconfigurable Hardware Through Direct Verification, Kevin Brandon Camera, University of California, Berkeley, 2008 Design Without Borders, Jan M. Rabaey, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), 2008 System Design and Analysis, H. De Man, J. Rabaey, Kluwer Academic Publishers, 2008 A Lossless 2-D Image Compression Technique for Synthetic Discrete-Tone Images, Jeffrey M. Gilbert, Robert M. Brodersen, 2008 InfoNet: the Networking Infrastructure of InfoPad, My T. Le, Fred Burghardt, Srinivasan Seshan, Jan Rabaey, 2008 Architectural Implementation Issues in a Wideband Receiver Using Multiuser Detection, Nina Zhang, Craig Teuscher, Hungchi Lee, Robert W. Brodersen, 2008 BORPH: An Operating System for FPGA-Based Reconfigurable Computers, Hayden Kwok-Hay So, University of California, Berkeley, 2008 76 PUBLICATIONS – 2007 To search specific listings visit: http://bwrc.eecs.berkeley.edu/php/pubs/pubs.php • • • • • • • • • • • • • • • Millimeter-Wave Devices and Circuit Blocks up to 104 GHz in 90 nm CMOS, Babak Heydari, Mounir Bohsali, Ehsan Adabi, Ali M. Niknejad, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 42, 12, 2893 - 2903, December, 2007 Low-Power Successive Approximation Converter With 0.5 V Supply in 90 nm CMOS, Simone Gambini, Jan Rabaey, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 42, 11, 2348 - 2356, November, 2007 Radio Testbeds Using BEE2, Susan Mellers, Brian Richards, Hayden So, S. M. Mishra, Kevin Camera, P. A. Subrahmanyam, Bob Brodersen, Proceedings of the Asilomar Conference on Signals and Computers, Custom Circuits Integrated Conference, November, 2007 Exploring Very Low-Energy Logic: A Case Study, L. P. Alarcon, T.-T. Liu, M. D. Pierson, J. M. Rabaey, Journal of Low Power Electronics, 3, 223-233, October, 2007 Peak-to-Average Power Ratio Reduction in an FDM Broadcast System, Zhengya Zhang, Renaldi Winoto, Ahmad Bahai, Borivoje Nikolic, IEEE Workshop on Signal Processing Systems, October, 2007 Nanoscale CMOS for mm-Wave Applications, Ali M. Niknejad, S. Emami, B. Heydari, M. Bohsali, E. Adabi, 2007 IEEE Compound Semiconductor Integrated Circuit Symposium, IEEE, 1-4, October, 2007 A 1V 250Kpps 90 nm CMOS Pulse Based Receiver for cm-Range Wireless Communications, D. Guermandi, S. Gambini, J. Rabaey, Proceedings of the 2007 European Solid State Circuits Conference, 135 - 138, September, 2007 The Case for Multiband Sensing, Shridhar Mubaraq Mishra, Rahul Tandra, Anant Sahai, The 45th Annual Allerton Conference on Communication, Control, and Computing, The Allerton House, University of Illinois, September, 2007 Cognitive Technology for Improving Ultra-Wideband (UWB) Coexistence, Shridhar Mubaraq Mishra, Robert W. Brodersen, 2007 IEEE International Conference on Ultra-Wideband, IEEE, September, 2007 A 65μW, 1.9 GHz RF to Digital Baseband Wakeup Receiver for Wireless Sensor Nodes, Nathan Pletcher, Simone Gambini, Jan Rabaey, Custom Integrated Circuits Conference (CICC), September, 2007 Modelling and Simulation Techniques for Highly Integrated, Low-power Wireless Sensor Networks, B. Otis, S. Gambini, R. Shah, D. Steingart, E. Quevy, J. Rabaey, A. SangiovanniVincentelli, P. Wright, IET Comput. Digit. Tech, 1, 5, 528 - 536, September, 2007 Evaluation of the Low Frame Error Rate Performance of LDPC Codes Using Importance Sampling, Lara Dolecek, Zhengya Zhang, Martin Wainwright, Venkat Anantharam, Borivoje Nikolic, Information Theory Workshop, September, 2007 ASIC Design and Verification in an FPGA Environment, Dejan Markovic, Chen Chang, Brian Richards, Hayden So, Borivoje Nikolic, Robert W. Brodersen, 2007 Proceedings Custom Integrated Circuits Conference, 737-740, September, 2007 ASIC Design and Verification in an FPGA Environment, Dejan Markovic, Chen Chang, Brian Richards, Hayden So, Borivoje Nikolic, Bob Brodersen, IEEE Custom Circuits Integrated Conference, September, 2007 A 60 GHz Power Amplifier in 90nm CMOS Technology, Babak Heydari, Mounir Bohsali, Ehsan Adabi, Ali M. Niknejad, IEEE 2007 Custom Intergrated Circuits Conference (CICC), 769-772, September, 2007 77 • • • • • • • • • • • • • • • • • • A 100KS/s 65dB DR Σ − Δ ADC with 0.65V Supply Voltage, Simone Gambini, Jan Rabaey, Proceedings of the 2007 European Solid States Circuits Conference, 202-205, September, 2007 Adventures with a Reconfiguarble Research Platform, John Wawrzynek, Proceedings of the International Conference on Field Programmable Logic and Applications, IEEE, August, 2007 RAMP Blue: A Message-Passing Manycore System in FPGAs, Alex Krasnov, Andrew Schultz, John Wawrzynek, Greg Gibeling, Pierre-Yves Droz, Proceedings of the International Conference on Field Programmable Logic and Applications, IEEE, 54-61, August, 2007 UWB Mixed-Signal Transform-Domain Direct-Sequence Receiver, Sebastian Hoyos, Brian Sadler, IEEE Transactions on Wireless Communications, 6, 8, 3038-3046, August, 2007 Short Distance Wireless, Dense Networks and Its Opportunities, Jan M. Rabaey, Fred Burghardt, Yuen Hui Chee, David Chen, Luca De Nardis, Simone Gambini, Davide Guermandi, Michael Mark, Nathan Pletcher, August, 2007 A 1.5-V 0.7–2.5-GHz CMOS Quadrature Demodulator for Multiband Direct-Conversion Receivers, Nuntachai Poobuapheun, Wei-Hung Chen, Zdravko Boos, Ali M. Niknejad, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 42, 8, 1669 - 1677, August, 2007 Energy Efficient Inverse Power Control for a Cognitive Radio Link, Marko Hoyhtya, Anant Sahai, Danijela Cabric, Aarne Mammela, 2nd International Conference on Cognitive Radio Oriented Wireless Networks and Communication (CrownCom2007), August, 2007 Detect and Avoid: An Ultra-Wideband/WiMax Coexistence Mechanism, Ravishankar Mahadevappa, Stephan ten Brink, Shridhar Mubaraq Mishra, Robert W. Brodersen, IEEE Communications Magazine, 68-75, June, 2007 Addressing the Dynamic Range Problem in Cognitive Radios, Jing Yang, Robert W. Brodersen, David Tse, IEEE International Conference on Communications, 5183 - 5188, June, 2007 BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design, M. V. Dunga, C.-H. Lin, D. D. Lu, W. Xiong, C.R. Cleavelin, P. Patruno, 2007 IEEE Symposium on VLSI Technology, 60 - 61, June, 2007 Design Without Borders - A Tribute to the Legacy of A. Richard Newton, Jan M. Rabaey, 44th ACM/IEEE Design Automation Conference (DAC), xiii-xiii, June, 2007 Quantization Effects in Low-Density Parity-Check Decoders, Zhengya Zhang, Lara Dolecek, Martin Wainwright, Venka Anantharam, Borivoje Nikolic, IEEE International Conference on Communications, IEEE, 6263 - 6237, June, 2007 Analysis of Absorbing Sets for Array-Based LDPC Codes, Lara Dolecek, Zhengya Zhang, Venkat Anantharam, Martin Wainwright, Borivoje Nikolic, IEEE International Conference on Communications, IEEE, 6261-6268, June, 2007 A 5.8 GHz Linear Power Amplifier in a Standard 90nm CMOS Process Using a 1V Power Supply, Peter Haldi, Debopriyo Chowdhury, Gang Liu, Ali Niknejad, 2007 IEEE Radio Frequency Integrated Circuits Symposium, IEEE RFIC, 431-434, June, 2007 BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design, M. Dunga, C.-H. Lin, D. Lu, W. Xiong, C.R. Cleavelin, P Patruno, J.-R. Hwang, F.-L. Yang, A. Niknejad, C. Hu, 2007 VLSI Technology Symposium, June, 2007 A Highly Linear Broadband CMOS LNA Employing Noise and Distortion Cancellation, WeiHung Chen, Gang Liu, Boos Zdravko, Ali Niknejad, 2007 IEEE Radio Frequency Integrated Circuits Symposium, IEEE RFIC, 61-64, June, 2007 30 GHz CMOS Low Noise Amplifier, Ehsan Adabi, Babak Heydari, Mounir Bohsali, Ali Niknejad, 2007 IEEE Radio Frequency Integrated Circuits Symposium, IEEE RFIC, 625-628, June, 2007 Internal Unilaterization Technique for CMOS mm-Wave Amplifiers, Babak Heydari, Ehsan Adabi, Mounir Bohsali, Bagher Afshar, Amin Arbabian, Ali Niknejad, 2007 IEEE Radio Frequency Integrated Circuits Symposium, IEEE RFIC, 463-466, June, 2007 78 • • • • • • • • • • • • • • • • • • • • • • • • A 5.8 GHz Linear Power Amplifier in a Standard 90nm CMOS Process Using a 1V Power Supply, P. Haldi, D. Chowdhury, G. Liu, A. Niknejad, 2007 IEEE Radio Frequency Integrated Circuits Symposium, 431-434, June, 2007 Exploration of mm-Wave Building Blocks in 90/65nm CMOS, Cristian Marcu, 21, 29, May, 2007 Addressing the Dynamic Range in Cognitive Radios, Jing Yang, 21, 29, May, 2007 Trends In Cellular Communication, Avneesh Agrawal, 21, 29, May, 2007 Proposed NSF Center for Advanced Radio Spectrum Utilization (CARSU), Gary Kelson, 21, 29, May, 2007 Cooperative Communication, Anant Sahai, Pulkit Grover, Mubaraq Mishra, Rahul Tandra, 21, 29, May, 2007 Cognitive Radio Technology for UWB/WiMax Coexistence, Mubaraq Mishra, 21, 29, May, 2007 Advanced Spectrum Sharing Systems: A System Perspective, Jan Rabaey, Adam Wolisz, 21, 29, May, 2007 Visions of the Universal Wireless Terminal, Ali Niknejad, 21, 29, May, 2007 Connectivity Lab Research Programs, Ahmad Bahai, 21, 29, May, 2007 Cognitive Radio Systems and Test Beds, Mubaraq Mishra, 21, 29, May, 2007 Spectrum Sharing Applications, Paul Wright, 21, 29, May, 2007 Advanced Wireless Terminals, Ali Niknejad, Borivoje Nikolic, 21, 29, May, 2007 Silicon Valley Engineering Hall of Fame: Solar Energy, T.J. Rodgers, 21, 29, May, 2007 Proposed ERC Center for Advanced Radio Spectrum Utilization (CARSU), Paul Wright, 21, 29, May, 2007 Automated Design for Current-Mode Pass-Transistor Logic Block, Matthew Pierson, University of California, Berkeley, May, 2007 Wireless Sensor Networks for Home Health Care, Chris R. Baker, Kenneth Armijo, Simon Belka, Merwan Benhabib, Vikas Bhargava, Nathan Burkhart, Artin Der Minassians, Gunes Dervisoglu, Lilia Gutnik, Brent Haick, Christine Ho, Mike Koplow, Jennifer Mangold, Stefanie Robinson, Matt Rosa, Miclas Schwartz, Christo Sims, Hanns Stroffregen, Andrew Waterbury, Eli S. Leland, Trevor Pering, Paul K. Wright, 21st International Conference on Advanced Information Networking and Applications Workshops. Volume 2, 832-837, May, 2007 Mental Bounds on Power Reduction During Data-Retention in Standby SRAM, A. Kumar, H. Qin, P. Ishwar, J. Rabaey, K. Ramchandran, IEEE International Symposium on Circuits and Systems (ICAS), 1867 - 1870, May, 2007 Coexistence with Primary Users of Different Scales, S. M. Mishra, Rahul Tandra, Anant Sahai, IEEE DySpan Conference, April, 2007 Cognitive Technology for Ultra-Wideband/WiMax Coexistence, S. M. Mishra, S. ten Brink, R. Mahadevappa, B. Brodersen, IEEE DySpan Conference, April, 2007 Power and Area Minimization for Multidimensional Signal Processing, Dejan Markovic, Borivoje Nikolic, Bob Brodersen, Journal of Solid-State Circuits, 42, 4, 922-934, April, 2007 Designing and Managing Networks to Aid the Capture and Preservation of Evidence to Support the Fight Against e-Crime, Paul Wright, William Fone, Proceedings of the 2007 IEEE International Conference on Networking, Sensing and Control, 251 - 254, April, 2007 Cyclostationary Feature Detector Experiments Using Reconfigurable BEE2, Artem Tkachenko, Danijela Cabric, Robert W. Brodersen, International Conference on Dynamic Spectrum Access Networks, April, 2007 Fundamental Redundancy Versus Power Trade-off in Standby SRAM, A. Kumar, H. Qin, P. Ishwar, J. Rabaey, K. Ramchandran, IEEE International Conference on Acoustics, Speech and Signal Processing, Volume 2, y SRAM", IEEE Inter, April, 2007 79 • • • • • • • • • • • • • • • • • • • • • • • Multi-Dimensional Circuit and Micro-Architecture Level Optimization, Jerry Qi Zhenyu, Matthew Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan, 8th International Symposium on Quality Electronic Design (ISQED), 275 - 280, March, 2007 Beyond Sensor Networks: ZUMA Middleware, Mikael N. K. Soini, Jana Van Greunen, Jan M. Rabaey, Lauri T. Sydanheimo, IEEE Wireless Communications and Networking Conference (WCNC), 4318-4323, March, 2007 Beyond Sensor Networks: ZUMA Middleware, Mikael N. K. Soini, Jana Van Greunen, Jan M. Rabaey, Lauri T. Sydanheimo, IEEE Wireless Communications and Networking Conference, IEEE, 4318-4323, March, 2007 Integrated Circuit Transmission-line Transformer Power Combiner for Millimetre-wave Applications, A. M. Niknejad, M. Bohsali, E. Adabi, B. Heydari, Electronic Letters, 43, 5, 290291, March, 2007 Deep Sub-Micron SRAM Design for Ultra-Low Leakage Standby Operation, Huifang Qin, University of California, Berkeley, March, 2007 RAMP: Research Acccelerator for Multiple Processors, John Wawrzynek, David Patterson, Mark Oskin, Shih-Lien Lu, Christoforos Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic, IEEE Micro, 27, 2, 46 - 57, March, 2007 A Highly Integrated 60GHz CMOS Front-End, Sohrab Emami, Chinh Doan, Robert W. Brodersen, Ali M. Niknejad, 2007 IEEE International Solid-State Circuits Conference, IEEE ISSC, 190-191, February, 2007 Low-Power mm-Wave Components up to 104GHz, Babak Heydari, Mounir Bohsali, Ehsan Adabi, Ali Niknejad, 2007 IEEE International Solid-State Circuits Conference, IEEE ISSC, 200201, February, 2007 Low Energy Digital Circuits Using Current Mode Pass Transistor Logic, Matthew Pierson, Louis Alarcon, Tsung-Te Liu, Jan Rabaey, 20, 8, January, 2007 Measurement and Analysis of Variations in 90nm CMOS Circuits, Liang-Teck Pang, Borivoje Nikolic, 20, 8, January, 2007 Wireless Industry Trends and Technology, Bill Krenik, 20, 8, January, 2007 Towards MEMS-Based Receivers, Clark T.-C. Nguyen, 20, 8, January, 2007 Supply Noise Measurement and Regulation, Elad Alon, 20, 8, January, 2007 CMOS Technology for Wireless Communications, Ali M. Niknejad, 20, 8, January, 2007 Project Status, Bob Brodersen, 20, 8, January, 2007 Performance of LDPC Codes in the Very Low BER Regime, Lara Dolecek, Zhengya Zhang, Borivoje Nikolić, Venkat Anantharam, Martin Wainwright, 20, 8, January, 2007 60 GHz CMOS 90nm Front End & mm-Wave Update, Bagher Ali Afshar, Mounir Bohsali, Babak Heydari, Ehsan Adabi, Amin Arbabian, Cristian Marcu, Ali Niknejad, 20, 8, January, 2007 Cognitive Radio Spectrum Sensing: Energy, Pilot, and Feature Detection, Artem Tkachenko, Danijela Cabric, Robert Brodersen, 20, 8, January, 2007 60GHz CMOS Power Amplifiers, Mounir Bohsali, Babak Heydari, Ehsan Adabi, Ali Niknejad, 20, 8, January, 2007 Robust SRAM Design Under Process Variations, Zheng Guo, Borivoje Nikolić, 20, 8, January, 2007 Device Integrated Power Generation & Energy Storage, Dan Steingart, Beth Reilly, Christine Ho, James Evans, Paul Wright, 20, 8, January, 2007 Smart Tire, David Chen, Simone Gambini, Davide Guermandi, Jan Rabaey, 20, 8, January, 2007 RAMP Blue: A Message Passing Multi-Processor System on the BEE2, Andrew Schultz, Alexander Krasnov, 20, 8, January, 2007 80 • • • • • • • • • • • • • Dispenser Printing of Solid Polymer-Ionic Liquid Electrolytes for Lithium Ion Cells, Dan Steingart, Christine Ho, Justin Salminen, James W. Evans, Paul K. Wright, 6th International Conference on Polymers and Adhesives in Microelectronics and Photonics, 261-264, January, 2007 Overview of Research Results and Progress, Jan Rabaey, 20, 8, January, 2007 Overview of Research Results and Progress, Paul Wright, 20, 8, January, 2007 BEE Project Update, John Wawrzynek, 20, 8, January, 2007 System Support for Ambient Intelligent Environments, Chris Baker, 20, 8, January, 2007 Antenna Array Signal Processing: Architectures and Tools for High Performance DSP, Dan Werthimer, 20, 8, January, 2007 Research Highlights: Digital and Analog IC Designs, Borivoje Nikolic, 20, 8, January, 2007 CMOS Low Noise Amplifier with Capacitive Feedback Matching, Ehsan Adabi, Ali Niknejad, Proceedings of CICC, CICC, 643-646, 2007 Ultra Low Power Clock Generation Using Sub-threshold MOS Current Mode Logic, Asako Toda, University of California, Berkeley, 2007 A Power/Arera Optimal Approach to VLSI Signal Processing, Dejan Marko Markovic, University of California, Berkeley, 2007 Testbed Design for Cognitive Radio Spectrum Sensing Experiments, Artem Tkachenko, University of California, Berkeley, 2007 Jitter Reduction on High-Speed Clock Signals, Tina Smilkstein, University of California, Berkeley, 2007 The Application of Wireless Sensor Networks to Residential Energy Efficiency and Demand Response, Nathan Ken Ota, University of California, Berkeley, 2007 81 ACKNOWLEDGEMENTS We are grateful to our members for their support: Agilent Technologies Cadence Design Systems Fujitsu Laboratories Gigascale Systems Research Center Infineon Technologies Intel Corporation Korea Electronics Technology Institute Marvell Semiconductor Nokia Research NXP Semiconductors We wish to thank our research partners: Berkeley Manufacturing Institute Berkeley Sensor & Actuator Center Center for Astronomy Signal Processing and Electronics Research Center for Circuit and System Solutions Center for Information Technology Research in the Interest of Society Center for the Built Environment Institute of Digital and Computer Systems TKN - Telecommunications Networks Group VTT Technical Research Centre of Finland Wireless Foundations Research Center Panasonic Research Pirelli Tyre S.p.A. Qualcomm Inc. Samsung Electronics Sanyo Corporation STMicroelectronics Texas Instruments Toshiba Corporation Xilinx Incorporated We would like to recognize the following companies for their donations of wafer fabrication services: International Business Machines Corporation, East Fishkill, NY Jazz Semiconductor, Newport Beach, CA STMicroelectronics, Crolles, France Taiwan Semiconductor Manufacturing Company, Hsin-Chu, Taiwan, R.O.C. United Microelectronics Corporation, Hsin-Chu, Taiwan, R.O.C. 82 The Berkeley Wireless Research Center would like to acknowledge the support of the following research agencies: The National Science Foundation       UC Berkeley Wireless Infrastructure Program, Grant CNS-0403427 Theory and Methodology for the Design and Evaluation of High-Performance LDPC Codes, Grant CCF-0635372 CAREER: A Framework for addressing some fundamental challenges in deeply scaled CMOS circuit, Grant ECS-0238572 ITR-NHS-DMC: Making Speech Recognition Pervasive by Migrating it into Silicon, Grant 1120607-158712 Exploration of THz CMOS for Imaging Applications, Grant ECCS-0702037 CRI – Research Accelerator for Multi-Processors, RAMP, Award CNS-0551739 The Defense Advanced Research Projects Agency  Wafer Scale Distributed Radio, Award FA8650-08-1-7855 The Focus Center Research Program, Center for Circuits and Systems Solutions (C2S2)  Robust, Rapid and Wireless Chip Design, Grant 1120607-158712 The Focus Center Research Program, Gigascale System Research Center (GSRC)  Collaborative Research in the Design, Verification, and Test of Integrated Gigascale Systems, Award 2003-DT-660 Semiconductor Research Corporation   BSIM for Mixed Mode Circuit Simulation Using Advanced CMOS Technology, Grant 2006-VJ-1454 Robustness of Deeply Scaled CMOS Logic Circuits, Grant 2007-HJ-1600 California State Micro       Transceiver Circuits for Next Generation Broadband Wireless Systems, Award 06-257 Energy Efficient DSP Circuits: Iterative Decoding Algorithms and Their Implementation, Award 05-087 and Award 06-222 Raising the Bar on Self-Contained Wireless Sensor Nodes, Award 06-241 RAMP: Research Accelerator for Multiple Processors, Award 06-232 Smart Tires - Raising the Bar on Self-Contained Wireless Sensor Nodes, Award 07-017 Low Noise 90nm/65nm CMOS mm-Wave, Award 07-284 83 UC Discovery Grant  An Ultra Low Cost 10 GHz CMOS LNB Satellite Communication Receiver, Grant COM05-10191 California Energy Commission      New Thermostat, New Temperature Node and New Meter, Award DR-03-01 Network Agility and Service Management, Award DR-06-02B Fault Analysis in Cables Scoping Study, Award C-06-23 Fault Analysis in Underground Cables, Award MR-07-08 Programmable Communicating Thermostat, Award C-05-34 Jet Propulsion Laboratory  Digital Spectrometers for Microwave Spectrometers, Grant 1294652 Department of Energy, Lawrence Berkeley National Laboratory  Accelerating Science-driven System Design with RAMP, Award 6823313 Air Force Research Laboratory • FPGA Emulation for Computer Architecture Research Development, Award FA8650-09C-7907 We would also like to thank the BWRC staff who keep the center running and facilitate our research endeavors: Tom Boot Deirdre McAuliffe-Bauer Fred Burghardt Dan Burke Pierce Chua Brenda Farrell Brad Krebs Susan Mellers Brian Richards Ken Tang Kevin Zimmerman Thank you also to the technical staff that assisted with the production of this report: Dan Chapman Allen Hopkins 84 BWRC STAFF Gary Kelson BWRC Executive Director Manages BWRC business and technical operations. This includes member relations, research reviews, research publications, technical staff management, and collaboration with other academic institutions. He chairs the BWRC Board of Advisors. Gary was SVP and CTO of Silicon Systems and SVP and GM of Technicron Communications Systems before joining BWRC. Deirdre McAuliffe Bauer BWRC Business Director Business Director for BWRC. Responsible for industrial awards and grants, federal, and state funding in support of BWRC faculty, graduate students, research staff and visitors. Responsible for the financial planning and direction of the center and for developing and managing a two to five year business plan that drives the revenue, expenditures, staffing and infrastructure. Always available to encourage folks to have a good time and enjoy life while working hard towards our common goals. Fred Burghardt Research Staff Engineer (Cognitive Radio, Connectivity Broker and related projects) Provide technical staff support for BWRC research, in particular the Cognitive Radio and Connectivity Broker projects. Cognitive Radio work centers on the a collection of hardware and software called the Cognitive Radio Test Bed, which enables research at various levels including fine-grain physical layer control, a high bandwidth channel to configurable logic, software support, and a well-define user interface. The hardware platform consists of up to sixteen “front-end” boards and a BEE2. Fred is responsible for construction, development, and support of the Test Bed. The Connectivity Broker is a functional entity that is the core of an “absolutely reliable wireless systems” concept. The Broker is responsible for coordination of heterogeneous networks e.g. cell, sensor, Wi-Fi, Bluetooth including dynamic spectrum assignment, cognitive radio network management, and collaboration between wireless terminals and networks. Fred is currently working on architecture development for the Connectivity Broker. 85 Pierce Chua Part-time Computer Systems Administrator Provides end-user Windows client support. Also responsible for server and systems maintenance and security in the center. Currently a senior EECS undergraduate at UC Berkeley. Brad Krebs Systems Administrator Supports students, faculty and staff in using the diverse research computing environment at the BWRC. Since joining the staff in 2005, some of Brad’s major projects have included the installation of a Sun N1 Grid system on fifty computers, replacing the seventy Windows desktop machines with new hardware running Red Hat Linux, automation of systems administration tasks and updating the groups Unix computer servers. Susan H. Mellers Research Staff Engineer Primarily involved with the Hardware System Design, Development and Technical Support for the MCMA Multi-Carrier Multi-Antenna Transceiver system. Technical consultant of hardware systems including schematic and pcb design and development and system integration. Management of Printed Circuit Board Computer Aided Design, fabrication, and assembly. Manager of BWRC Laboratory. Brian Richards Research Staff Engineer; CAD Tool, Design Flow, and IC Technology Support Lead engineer on the Mars Spectrometer Project, an effort with the CASPER research team to develop an ASIC based on a design described using Matlab Simulink. This design exercises the INSECTA Design Flow environment for retargeting FPGA designs described in Simulink to equivalent ASIC designs. Also maintains CAD Tool installations, licenses, design flows, and technology libraries for the BWRC. PI: Borivoje Nikolic; Primary funding: DARPA C2S2. 86 Ken Tang Systems Administrator Ken Tang recently joined the BWRC as a full-time staff employee in October of 2008. His duties include providing overall user support to faculty, staff and students, as well as a wide range of systems administration for the Windows operating systems, Mac operating systems and various flavors of Unix/Linux. Also responsible for maintaining the BWRC web sites and developing internal and external web applications. In his spare time, Ken enjoys listening to and playing classical music. His primary instruments are the violin and viola. Kevin Zimmerman Computer Systems Administrator Member of the IT support team at BWRC. Current areas of activity are architecture, networking, security, storage and messaging. Professional interests also include project management, systems analysis and human factors. Dan Burke Ramp Engineer Primarily engaged in system design, ranging from next generation platform subsystem development (power, networking, mechanical) in support of advanced projects, implementation (algorithm design, operating system interaction, RTL emulation), up to large-scale exemplars (1008 processor many-core RAMP Blue). Current projects include: BEE2 support, research integration of BWRC efforts onto BEE3, RAMP port to advanced HW, joint Stanford bioinformatics large scale system design and deployment. 87 Brenda Farrell Administrative Specialist Provide administrative support to BWRC Professors Jan Rabaey, Borivoje Nikolic, Ali Niknejad and John Wawrzynek as well as their students. Also responsible for conference and event coordination, and assist in the maintenance and update of the BWRC website. Tom Boot Administrative Specialist Provides administrative assistance to BWRC Director Gary Kelson and Professors Bob Brodersen and Elad Alon; acts as the BWRC Retreat Coordinator and assistant BWRC facilities manager. 88