Convolution Codes by kjy11098

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									                                Convolution Codes

1.0 Prologue:
 Convolutional codes, why should complicate our lives with them
      People use to send voice waveforms in electrical form over a twisted pair of wires. These
telephone voice signals had a bandwidth of 4KHz. If the channel polluted the signal with a bit of
noise, the only thing that happened was that the conversation got a bit noisier. As technology de-
veloped, we digitized the voice signals at 8000 samples per second (twice the highest frequency to
prevent aliasing) and transmitted the bits. If noise corrupted a few bits, the corresponding sample
value(s) would be slightly wrong or very wrong depending on whether the bad bits were near the
most-significant-bit or least-significant-bit. The conversation sounded noisier, but were still dis-
cernible. Someone saying “cat” will not be thought to have said “dog,” and probably would not
even be thought to have said “caught.”
       When people started to send data files rather than voice, corrupted bits became more impor-
tant. Even one wrong bit could prevent a program from running properly. Say the noise in a chan-
nel was low enough for the probability of a bad bit to be 1x10-9 i.e. the chances of a bit being
correct is 0.999999999 (nine 9’s). The chances of 1000 bits being all correct is 0.999999 (six 9’s)
and the chances of 106 bits being all correct is 0.999 (three 9’s). A 1 megabyte file (8x106 bits) has
almost a 1% chance of being corrupted. The reliability of the channel had to be improved.
       The probability of error can be reduced by transmitting more bits than needed to represent
the information being sent, and convolving each bit with neighbouring bits so that if one transmit-
ted bit got corrupted, enough information is carried by the neighbouring bits to estimate what the
corrupted bit was. This approach of transforming a number of information bits into a larger
number of transmitted bits is called channel coding, and the particular approach of convolving the
bits to distribute the information is referred to as convolution coding. The ratio of information bits
to transmitted bits is the code rate (less than 1) and the number of information bits over which the
convolution takes place is the constraint length.
       For example, suppose you channel encod-
ed a message using a convolution code. Suppose                                    Convolution
                                                               00101101            channel
you transmitted 2 bits for every information bit                                   encoder
                                                                a   b
(code rate=0.5) and used a constraint length of 3.
 Then the coder would send out 16 bits for every
                                                                11 10 00 01 01 00
8 bits of input, and each output pair would de-
pend on the present and the past 2 input bits (con-
straint length =3). The output would come out at        a 3 bits in the input stream generate 2 bits
twice the input speed.                                    in the output stream.
                                                        b Take the most recent of these input bits
      Since information about each input bit is           plus one new input bit and generate the
spread out over 6 transmitted bits, one can usual-        next 2 output bits.
ly reconstruct the correct input even with several        Thus each input bit effects 6 output bits.
transmission errors.                                     FIGURE 1

Authors, Fred Ma, John Knight               January 26, 2001                                           1
                                                                                          Convolution Codes

       The need for coding is very important in the use of cellular phones. In this case, the “chan-
nel” is the propagation of radio waves between your cell phone and the base station. Just by turn-
ing your head while talking on the phone, you could suddenly block out a large portion of the
transmitted signal. If you tried to keep your head still, a passing bus could change the pattern of
bouncing radio waves arriving at your phone so that they add destructively, again giving a poor
signal. In both cases, the SNR suddenly drops deeply and the bit error rate goes up dramatically.
So the cellular environment is extremely unreliable. If you didn’t have lots of redundancy in the
transmitted bits to boost reliability, chances are that digital cell phones would not be the success
they are today. As an example, the first digital cell system, Digital Advance Mobile Phone Service
(D-AMPS) used convolution coding of rate 1/2 (i.e. double the information bit rate) and constraint
length of 6. Current CDMA-based cell phones use spread-spectrum to combat the unreliably of the
air interface, but still use convolution coding of rate 1/2 in the downlink and 1/3 in the uplink (con-
straint length 9). What CDMA is, is not part of this lab. You can ask the TA if you are curious.

2.0 Example of Convolution Encoding

                                        XOR                           Output u1

                                                                                  MUX       Double
                                              Shift register                                speed
                                                                                   0        output
         Input information                       Yester-    Day
                                      Today                 before                 1           z
            bit stream x                          days      yester-
                                                   bit      days
  The constraint length is 3.                               bit
  The output is effected                                                          clock
  (constrained) by 3 bits.
  The present input bit
  and the two previous bits
                                                                      Output u2
  stored in the shift register.          XOR
                                                                                            FIGURE 2

       This is a convolution encoder of code rate 1/2 This means there are two output bits for each
input bit. Here the output bits are transmitted one after another, two per clock cycle.
  The output u1 = x(n)⊕ x(n-1)⊕x(n-2).
Here x(n) is the present input bit, x(n-1) was the previous (yesterdays) bit, etc.
 The output u2= x(n)⊕ x(n-2).
The input connections to the XORs can be written as binary vectors [1 1 1] and [1 0 1] are known
as the generating vectors for the code.

Authors Fred Ma, John Knight                  January 26, 2001                                           2
                                                                                                                  Convolution Codes

2.1 The Encoder as a Finite-State Machine
     The correlation encoder can be described as a Mealy
                                                                                                   x=0/ z=00
machine. The state is the two bits in the shift register.
      Assume shift register was reset to zero and the first
data bit x(n) = 1. Then:-                                                                x=1         A=00
      State= 00 = A = [x(n-1),x(n-2)]                                                    z=11
      Output z=[u1,u2]                                                                                                  x=0
      u1 = x(n)⊕ x(n-1)⊕x(n-2)                                                                       x=1/ z=
         = 1⊕ 0⊕ 0 =1                                                                    B=10
      u2 = x(n)⊕ x(n-2).                                                                           x=0/ z=
         = 1⊕ 0 =1                                                                                                     C=01
      z=[u1,u2]= 11                                                                           x=1
      After the clock, state bit x(n-1)=0 will shift right
into x(n-2), the input x(n)=1 will shift right into x(n-1),                                                             x=0
and the next state will be 10 = B.                                                x = x(n)                   D=11
                                                                                  state =
2.2 The Trellis Encoding Diagram
                                                                                  FIGURE 3                   x=1/ z=10
       To get the trellis diagram, squash the state diagram
                                                                                   NOTATION               TRELLIS
so A, B, C and D are in a vertical line. This line represents
the possible states at time t=n (now). Make time the hori-                             x/z                    0/00
                                                                                                A                           A
zontal axis. Put another line of states to show the possible                                                 1/1
states at t=n+1.                                                                    1 input

       Then add the transitions to the diagram. Make the                                             B                0 B

                                                                                    0 input
them all go from states @ t=n to states @ t=n+1. Thus the                                                         1/0
self loop at state A in the state graph becomes the horizon-                                                        0/1

tal line from A@t=n to A @t=n+1 in the trellis diagram.                                              C                    C

     The complete trellis diagram extends past t=n+1 to as                         FIGURE 4                     1
many time steps as are needed.                                                                                1/10
                                                                                                    D                    D
       Suppose the encoder is reset to state A=00, and the                                         t=n                  t=n+1
input is 1,0,1,1,0,0. By following the trellis one sees that
the output is 11 10 00 01 01 11. Also it passes through
states A, B, C, B, D, C ending in A @ t=n+6.
                                        More Complete Trellis Diagram

           0/00                0/00              0/00                  0/00                0/00                   0/00
   A                   A                  A                    A                    A                    A                      A
           1/1                 1/1               1/1                   1/1                 1/1                    1/1
               1                   1                 1                     1                   1                      1






   B                 0 B                0 B                 0 B                  0 B


                                                                                                    0 B

                                                                                                                           0 B


                 1/0                1/0                 1/0                  1/0                1/0                    1/0
                   0/1                0/1                 0/1                  0/1                0/1                    0/1
                       0                  0                   0                    0                  0                      0





   C                     C                  C                   C                    C                  C






              1                    1                 1                    1                    1
          0/0                  0/0               0/0                  0/0                  0/0                   0/0
   D        1/10       D         1/10     D        1/10       D         1/10         D       1/10                  1/10
                                                                                                          D                    D
 t=n                  t=n+1              t=n+2               t=n+3                 t=n+4                 t=n+5              t=n+6

Authors Fred Ma, John Knight                            January 26, 2001                                                            3
                                                                                            Convolution Codes

2.3 First Exercise: A Convolution Encoder.
  1. Problem: Encoding a number
    • Take the last 4 digits in your student (the least significant digits).
    • Convert them to a hexadecimal number (Matlab has a function dec2hex).
    • Convert the hexadecimal number to binary (12 to 16 bits).
    • Use this as data for the encoder below. Feed in the least significant bit first. Also reset the
      shift register to 00 before you start.
    • Calculate the output bits and states when one encodes these bits using a code rate
      1/2, constraint length 3 encoder with generating vectors [111] and [101].
      Tabulate how the state and output values change with each clock cycle.

      Clock cycle        1     2   3   4   5      6     7     8   9   10   11   12   13     14   15    16

        input bit

   shift reg (state) 00
   Output [u1,u2]
  2. Problem: Draw the circuit for an encoder which has:
     a code rate =1/2,
     constraint length of 4,
     generating vectors [1111] and [1011], where the “0” means no connection to x(n-1).
  3. Problem: Draw the state graph for the above constraint length 4 encoder, and then the first
     three time steps of the trellis diagram for the above constraint length 4 encoder.

2.4 First Lab: Design a Convolution Encoder in Verilog
       The constraint length 4 encoder circuit is a finite-state machine. It is also a shift register.
One can code it following the standard finite-state machine model with three-bit states, or as a shift
          reg [2:0] State;
             always @(posedge clk)
                      State <=State >> 1; // Right shift 1 position
      The test bench is not part of the circuit. It supplies the input sig-
nals and may compare output signals with those that are expected.                Test Bench module
Test benches are easier to write and use if they are synchronous. This
means they always send out signals slightly after the clock (or at least        clk reset    x     u1 u2
never at the same time as the clock). It also means a writing style with
few #n delay.
                                                                                 ConvEncode module
    initial begin
...     #11 x=1;                   Poor
        #10 x=0;                                                              FIGURE 6
        #10 x=1;
        #20 x=0;
        #10 x=1;

Authors Fred Ma, John Knight                   January 26, 2001                                             4
                                                                                     Convolution Codes

2.4.1 A Synchronous Test Bench
      In a synchronous test bench, the test signals are timed by @(posedge clk) statements rather
than each having its own timing. There are only two delays here, one to set the clock period, and
the other to delay the input signal x so it’s changes are obviously past the clock edge.
       Note there are things not included here, like reset.
          module SyncTestBench;
            reg [1:8] data; //Fill this with the data stream to be encoded.
                            // Note the first bit is on the left
            reg x, clk;
            integer I;
                 data=8'b1010_1101; // Underscore has no meaning except
                                         // to visually space the bits.
                 forever #5 clk=~clk;
          // send in a new value of x every clock cycle
               always @(posedge clk)
                          if (I==9) $finish;
               // The #1 makes x change 1ns after the clock and never on the clock edge.
               // The nonblocking symbol “<=” on I ensures that any other clocked module using
               // I will grab the same I as this procedure, that is before I is updated to I+1.
                          x<= #1 data[I];
     For the constraint length 3 system, you must have the test bench automatically compare your
answer with the result you obtained from your student number.
  1.    Write a finite-state machine encoder for the constraint length 3 system.
  2. Write a shift-register based encoder for the constraint length 4 system (Sect 2.3 prob 2).
  3. Write a synchronous test bench so the other two modules can be simulated.
     3a) Compare the result for the data 1 1 0 1 0 0 1 0 1 1 0 0 0 0
          Ans: Constraint length 3 encoded data-
          Ans: Constraint length 4 encoded data-

2.5 Lab and Problem Rules
       The Viterbi decoder design problem will be done by a groups of three persons.
      The number of exercises is (usually) divisible by three so one person in each group does
one-third of the exercises. The three are to be submitted together with the name of the person do-
ing each part attached to the part.
       All members of the group are responsible for knowing how to do each exercise. Related
problems will appear on the examination. Also the TAs will ask other members of the group to ex-
plain the submissions they did not submit. This will effect their mark as much as their submission.

Authors Fred Ma, John Knight                 January 26, 2001                                        5
                                                                                                             Convolution Codes

3.0 Convolution Decoder
       The next part of the project will be to design a convolution decoder to retrieve the informa-
tion bits from the transmitted bits. It should succeed even in the presence of some errors in the
transmitted bits. The implementation we will use is called a Viterbi decoder.

3.1 Decoding Using the Trellis Diagram
       Consider a decoder that receives the transmitted signal 11 01 01 00 10 11 going from t=n to
t=n+6. Assume the trellis was reset to state A (00) at the start. One goes through the trellis as be-
fore, only for decoding the numbers are output\input. So the first input, 11, gives a decoded output
of 1 and takes the machine to state B.
        At t=n+1 in state B, the next input 01 causes a 1 output and a change to state D.
                               Trellis Diagram for Decoding (Receiving)                                           FIGURE 7
Received 11                      01                01                   00                  10                   11
Decoded 1                         1                 0                    1                   0                    0
        00/0                    00/0              00/0                 00/0                00/0                  00/0
   A                   A                   A                  A                      A                   A                     A
        11/                     11/               11/                  1/1                 11/                   11/
            1                       1                 1                    1                   1                     1





                                         1 B

    B               1 B

                                                            1 B      11       1 B

                                                                                                     1 B

                00/                  00/                00/               00/                                             1 B
                                                                                                 00/                  00/
                 10/                  10/                10/               10/                    10/                  10/
                     0                    0                  0                 0                      0                    0




    C                  C                    C                  C                 C                      C                    C




               0                   0                 0                   0
           01/                 01/                01/                01/                   01/
    D       10/1       D        10/1       D       10/1       D       10/1           D      10/1                  10/1
                                                                                                          D                   D
  t=n                 t=n+1               t=n+2              t=n+3                 t=n+4                 t=n+5             t=n+6

3.1.1 The Hamming Distance                                                                                        FIGURE 8
                                                                         Received 11                         11
       This distance is used to show how far apart two                   input
binary numbers are. Compare the bits in the same posi-
                                                                                         00 2                              A
tions in the two numbers. The number of positions that                         A                     A
                                                                                         11 0
are different is the Hamming distance (h).                                                           Hamming distance
        Thus 11and 01 are distance 1 apart (h=1),
                                                                               B                     B                     B
        1001001 and 1001010 are distance 2 apart (h=2).
 Applying the Hamming Distance to Decoding

                                                                               C                     C                     C

       Suppose the first four received bits have an error
so instead of 11 01, one receives 11 11. On the trellis
in Fig. 8, there are two choices leaving state A, one for                       D          D                D
input 11 0 and the other for input 00 2 . The number in                        t=n        t=n+1            t=n+2
the box is the Hamming distance between the received                    Instead of input/output (i.e. 11/1)
input and the bits for the transition. It is clear one                  we now show input Hamming distance
should make the transition from A⇒B.
       The next input has an error. Note there are no 11 or 00 paths leaving state B. Both possible
paths, 10 or 01, are at Hamming distance 1. At this time either transition looks equally likely, but

Authors Fred Ma, John Knight                        January 26, 2001                                                               6
                                                                                                                      Convolution Codes

                                                   Trellis Diagram                                                        FIGURE 9
Received 11                     11                    01                      00             10                           11

             00 2                              A                             00 0            00 1
      A                  A                                            A                  A                    A                                  A
             11 0                                                                            11 1                       11



      B                  B                     B

                                                                  1 B               0 B

                                                                                                          1 B

                                                             00                00                 00
                                     10                                         10                 10                             10
                                           1                                         1                    0                                1



      C                  C                     C                      C                  C                    C                                  C


                                                     010                                                                  1
      Outputs                                                                                                          01
           is 0        D                    D                       D                  D     10 0           D           10 1             D
           is 1       t=n+1                t=n+2                   t=n+3             t=n+4                 t=n+5                      t=n+6
      At t=n+2, if one starts from D, then h=0 for the path to state C. However if one starts from C
one has h=1 for either the path to A or to B.
Thus at t=n+1 the proper path was not obvious, at t=n+2, the choice is clearer. We will chose a
path through the trellis based on the cumulative Hamming distance, which is the sum of the Ham-
ming distances as one steps along a path through the trellis.
        Figure 10 shows how the Hamming distances sum as one goes down various paths through
the trellis diagram. At t=n+5, one path has a total distance of 1 from the input data. The others
                                                                                                                        FIGURE 10
            00 2                           A                              1+ 1+ 0                         3 1
  A                  A                                            A                      A                            A
              0                                                                              3 1

                                                                                                                                  Lowest cummultative
                                                                                     0                1

                                                                                                                                  Hamming distance
  B                  B                     B                  1 B                 0+ B                            1 B
                                                         1+                   1+                              4
                                       1                                     1+                            1
                                                                                 1+                               0
  C                  C                     C                  0 C                    1 C                              C

                                                         1+                  1+
  D                  D                  D                          D                   D                  3 0          D
                    t=n+1              t=n+2                      t=n+3              t=n+4                            t=n+5
  The sum of the Hamming distances is shown like 1 + 1 + 0 until this gets too messy.
  Then the sum, and the distance for the current step, are shown in a hexagon and a box like 2 1

have a distance of 3 or 4. Thus the most likely path is A⇒B⇒D⇒C⇒B⇒C with a cumulative
distance of 1, and the corresponding output data is 11010 (Recall   trellis edges represent a
receiver output of 0, and          edges represent an output of 1).

  Bernard Sklar, Digital Communications Fundamentals and Applications.
  B.P.Lathe, Modern Digital and Analog Communication Systems, Holt, Rinehart & Winston, 1989
  Prof. Ian Marsland,
          Click on "Convolutional Codes." You will need Ghostview (gv) to read the Postscript file.

Authors Fred Ma, John Knight                              January 26, 2001                                                                              7
                                                                                                      Convolution Codes

4.0 The Viterbi Decoder
      The decoding example shown above has to follow multiple paths through the trellis, and re-
member them for future decisions. For larger decoders, such the cell phone ones with constraint
lengths (shift-register lengths + 1) of 6 and 9, the number of paths can get quite large. This means
a decoding ASIC may take considerable storage, and one may have to use slower, more compact
RAM type memory rather than the faster flip-flops.
       Viterbi developed an algorithm 1n 1967, which allows the many paths to be discarded with-
out tracking them to completion. He noticed that if two paths merge to one state, only the one with
the smaller cumulative Hamming distance, “H,” need be remembered. The other one can never be
part of the most likely path.
       This means that with the constraint length 3 (shift-register length 2) system in the previous
examples only have to remember 4 paths. In general a constraint length K system will have to re-
member 2K-1 paths. In theory, the path length should go for the length of the message in order to
get the true maximum likelihood path. However it turns out that path lengths of 4 to 5 times the
constraint length can almost always give the best path.
        The next few figures show how the decoder picks the best path, even when there are errors.
                                                                                                       FIGURE 11
                                error                       At t=n
Received 11
input                          01→11                         Starting at state A, there are two possible paths.
                                                             The boxes 2 show one step Hamming distance
            00 2               00 2 4 A                       The hexagons 4 show “H”, the cumulative
    A                  A                                      Hamming distance
            11 0               11
                                  0                         At t=n+1
                                                                There are 4 paths out to t=n+2
    B                  B                     B                  Since the input has an error,
                                    1                           no path has a zero Hamming distance “H”.
                                                                C State

    C                  C                     C

                                                                 4 Cumulative Hamming distance

                                                                 2 Hamming distance for this step
    D                  D                     D                  00 Rec’d input to make this transition
                      t=n+1                                         Output a 0 if this transition is used
  t=n                                       t=n+2                   Output a 1 if this transition is used

Received 11
input                          01→11                  01
                                                                           Going out to t=n+3
                                                                           The paths temporarily double to 8
            00 2                002 4     00 1 5
    A                  A               A 11        A                       There are two paths to each node.
            11 0                11         1
                                   0          5  2                         One has a larger cumulative distance.
                                                            1              The larger “H” path can never be
    B                   B
                               10            B         11 1 2 B            the most likely path, hence we will
                                    1                    00
                                        1                                  erase it.
                                                        01 2 6

    C                  C                     C                 C

                                                      0 1

    D                  D                     D    10 2 3   D
  t=n                 t=n+1                 t=n+2        t=n+3                                          FIGURE 12

Authors Fred Ma, John Knight                            January 26, 2001                                             8
                                                                                                                                       Convolution Codes

                                                                                                                                         FIGURE 13
 Here just the cumulative Hamming distances                                              Here the unneeded paths are eliminated.
 are shown so it is easy to see which paths                                              This is all important information up to
 should be erased.                                                                       to t=n+3.
 Rec’d 11                error                                                                                         error
                        01→11                            01                                            11             01→11               01
           2                      4                      5                                                2
  A               A                    A                                 A                A                       A            A                  A
          0                                          5           2                                     0                                     2

  B                B                   B                                 B                B                       B            B                   B
                                                             2                                                                              2
                                 1                                                                                         1
  C               C                    C                     1           C                C                       C            C            1     C


                                                         3                                                                                  2
  D               D                    D                               D                  D                    D                D                  D
  t=n            t=n+1                t=n+2                          t=n+3                t=n                 t=n+1            t=n+2             t=n+3

                                                                                                                                          FIGURE 14
                        error                                        2nd error
Rec’d 11               01→11               01                         00→01                       Entering t=n+4,
                                                            00                                      Eight paths are created temporarily
   A             A               A                       A 11 1 3                         A
          0                                     2            1                                            Again at each node, only the
                        2                                                3           2
                                                                                                          lowest cumulative Hamming-
                                                                             1                            distance path can be part of the
   B              B               B              B 10 2 11       B
                                              2              1 2                                          most likely path so four of the eight
                             1                            00                                              paths will again be eliminated.
                                                        01 4
   C             C                C                              C                                     The second error has made

                                               1 C             2
                                                                                                       four paths all with equal chances

                                                                     01                                of being the most-likely paths

   D             D                D                   D               10 2       4        D            (four paths with 2 )
                                                                                                       But see what happens next.
   t=n         t=n+1             t=n+2              t=n+3                                t=n+4

                                                                                                                                         FIGURE 15
Rec’d 11               01→11               01                2nd error
input                                                         00→01                               10
                                                                                                                          Entering t=n+5
    A            A               A                  A                            A        00 1 3                            Eight new paths are
                                                                                         111                          A
          0                                     2                                                                           created, keep the four
                         2                                                   2                     3          3
                                                                                                                            lowest H ones enter
    B            B               B                  B                            B                    1                     ing each state
                                              2                                                   11 1 3 B
                                                                         2                          00                      Since two paths
                             1                                                                       10
                                                                                                   01 0 2                   have the same H
    C            C               C            1 C                                C                        C                 as they enter B,

                                                                                                                            we have no way

                                                                     2                        2   4                         of choosing a

                                              2                                          01                                 better path.

   D            D                 D                  D                         D              10 0 2                D       Pick one randomly;
   t=n         t=n+1             t=n+2              t=n+3                    t=n+4                                t=n+5     Here we choose
                                           There are two most likely paths                                                  the one A⇒B.
   Note path dies out.
                                           (with H=2). Down from four at t=n+4

Authors Fred Ma, John Knight                                  January 26, 2001                                                                           9
                                                                                                                                        Convolution Codes

                       error                       2nd error                                                       Entering t=n+6
Rec’d 11
input                 01→11           01            00→01                10                          11
                                                                                                                     Note how the
                                                                          3                                          correlation has
  A            A               A               A             A                        A 100 2 5                  A   continued to act.
         0                                                                               10
                      2                2                2                                    3  2                    We are now down
                                                                                                                     to one most likely
  B            B               B               B                                                     0
                                                        2 B                           B
                                                                                                11 2 4
                                                                                                                 B   path.
                       1                                                                          00
                                                                                                 01 1 4
  C            C               C               C                C                     C                 C

                                       1                2
                                                                                               1 3

  D             D           D            D                 D              2     D               10 1 3           D
  t=n         t=n+1       t=n+2        t=n+3             t=n+4                t=n+5                          t=n+6                      FIGURE 16

                     error                                                                                                                  FIGURE 17
Rec’d 11                                           2nd error
input               01→11             01            00→01                 10                         11                        11

   A            A              A               A                A             3           A                        A 100 2 4                        A
          0                                                                                                           10
                          2                2                2                 3                          3       2        2  3

   B            B               B              B                B                         B                           B               0
                                       2                                                                                           11 2 5 B
                          1                                                                                                          00 0
                                                                                  2                                                 01 1 4
   C            C              C               C                C                         C                           C                    C

                                           1             2                                                   3


                                           2                                                                              01

   D            D               D            D              D D        3    D    10 1 4
                                                                                  2         D
   t=n        t=n+1           t=n+2        t=n+3            t=n+4
                                                          t=n+5          t=n+6            t=n+7
       Entering t=n+7: The one best path is getting fairly clear.
       The most likely path ends at B and a close second at A. The paths to C and D have H= 4
                                                   Retrieving the Original Message                                                          FIGURE 18
                     error                         2nd error
Rec’d 11            01→11             01            00→01                 10                    11               11                    10
   A            A              A               A                A                     A                  A                A                 4       A
   B            B               B              B                B                     B                  B                B                         B

   C            C              C               C                C                     C                  C                C                         C

 Common path
   D         D        D         D          D           D           D          D              D
   t=n     t=n+1 t=n+2        t=n+3     t=n+4       t=n+5        t=n+6      t=n+7         t=n+8
   Entering t=n+8: One can be fairly sure the best path at t=n+8 ends at state C.
   Follow the path back from C -> B-> A-> C-> B-> C-> D-> B-> A. Also follow the paths
   back from A, B and D. No matter what state you start in at t=n+8, all paths come together
   when you get back to t=n+1. From the solid       (for “0”)and dashed       (for 1) lines along
   the path one can decode the probable original message as 11010010 (travelling t=n to t=n+8).

Authors Fred Ma, John Knight                                    January 26, 2001                                                                        10
                                                                                                            Convolution Codes

       As illustrated above, the Viterbi decoder can decode a convolution code for a message of N
bits in the presence of some errors.
      If two branches entering a state have equal “H,” then the code is unable to tell if one path is
more likely than another. Pick one path at random.

                                                                                                                 FIGURE 19
4.1 Exercise 2: A Viterbi Decoder Design                                                   0/00 h00
                                                                               HA A                                   A   HA
  1. Problem: Using the algorithm                                                          1/1


       A typical step in the trellis decoder is shown.                                                        1

                                                                               HB    B                                B   HB

       The cumulative Hamming distances H at each trellis step                                           0
                                                                                                    0h 0
       are HA, HB, HC, and HD.                                                                   1/0 /1
       The Hamming distance for each edge are given sub-                                                         10

                                                                               HC   C                                 C   HC

       scripts matching the input which makes them 0. Thus the
       edge from A to A , and C to B both use the symbol h00.                             1h 0

                                                                                                            h 01
       If the input is 00, h00=0, If the input is 10 or 01, h00=1, if          HD   D    1/10 h10                     D HD
       the input is 11, h00=2.
                                                                                   t=n                    t=n+1
                                                              a) For the first lab partner: Starting at t=n+8 with
                                Input = 00 FIGURE 20
                                                              an input of 00, as in Figure 20, calculate and fill
                                      h00=                    in the values of hij and hence the Hk for t=n+9.
              HA=4 A                              A HA=
                                       h1                     b) For the 2nd lab partner: Starting at t=n+9, us-
                                           1=                 ing the Hk from step a) and input 10, calculate
              HB=4 B                              B HB=

                                                              and fill in Figure 21.


                                     h 00
                                        h                                                                    FIGURE 21
                                           10 =                                     Input =10
                                      h 01

              HC=2 C                              C HC=                                  h00=

                                                                         HA=   A                         A HA=5
              HD=4 D                h10=          D HD=                  HB=   B                         B HB=
                 t=n+8                            t=n+9
                                                    FIGURE 22            HC=   C                         C HC=
               Input =11

                                                                         HD=            h10=
 HA=      A                    A HA'= HC + h11 = 2                             D                         D HD=
                                                                           t=n+9                            t=n+10
 HB=      B                        '
                                B HB=
                      h1                                         c)For the 3rd partner: Start at t=n+10, with
                                                                 input 11 and use the Hk from step b). Let the
 HC=      C                         '
                                C HC=                            new Hk at t=n+11 be written with a prime i.e.
                  =                                              HA HB HC and HD Fill in Figure 22 but put
                                                                    ' ' '           '.
              h 01
 HD=      D                        '
                                D HD=                            in an expression, as well as a number, for
                                                                 each Hk. This has already been done for HA   '.
     t=n+10                        t=n+11                        Only the better path is written here.
     This is Verilog in which the syntax is not critical. For example begin, end and semicolons
     may be omitted if the meaning is clear to the reader. In pseudocode the comments are often
     more important than the code.

Authors Fred Ma, John Knight                          January 26, 2001                                                         11
                                                                                      Convolution Codes

  2. Problem: In parts a) and b) you will write pseudocode to calculate the Hamming distances
      for each step.
      Let the two input bits In[1:0] be y, x.
      Let the Hamming distances associated with the eight trellis edges for this step be h00, h01,
      For part b) use reg /*wire*/ [1:0] h00, h01, h10, h11;
   a) Calculate these distances using a case statement:
        case ({y, x})
            2'b00 : begin h00=0; ... h11=2; end
            2'b01 : ...
   b) Another partner should use Boolean algebra to calculate them as 2-bit binary numbers.
           h00[1] = y&x ; h00[0] = y^x;
  3. Problem: Pseudocode to update the Hk in going from step t=n to step t=n+1.
   a) Use if statements to calculate the Hk' to be associated with the four states at t=n+1. Use
      HAnext instead of HA' since Verilog cannot handle quotes.
          if (HA+h00 < HC+h11) then HAnext= HA+h00; else ...
  4. Problem: The flip-flop procedure.
     Write a procedure to clock the flip-flops and store the necessary data.
     Combinational logic in parts 2 and 3 calculated the D inputs for the flip-flops. For example:-
       HAnext = ... HA + h00 ....
     This procedure stores the data i.e it clocks HA <= HAnext.
     Don’t put combinational logic in a flip-flop procedure, and don’t forget a reset.
  5. Problem: When is the output correct?
     Experience has shown that all backward paths converge into one if one traces them back 4 or
     5 times the constraint length. Using the paths in Figure 18, you will show for this example
     that if one traces back far enough it does not matter which path one follows.
   a) Take a copy of Figure 18. Start at t=n+8; start at each state in turn and colour backwards un-
      til you reach t=n or until you hit previous colouring. At what time (t=n+?) do the paths all
   b) Look at Figure 14 in which the ending time is t=n+4.
    • Using data available at t=n+4 could you say, with          Test         encoder    decoder
      confidence, what the original data bit was between
      t=n and t=n+1? Why not?                                 original data bit
                                                               encoded, 2 bits for 1
   c) Take a copy of Figure 17. Start at t=n+7; start at each    decoded output, back to 1 bit.
      state in turn and colour backwards until you reach t=n
      or until you hit previous colouring. At what time (t=n+?) do the paths all converge?
       In communications latency is the term for the time difference between the time the input
       signal was received and the output signal is sent out.
   d) If a decoder had to wait until all paths converged before it had confidence it could send out a
      correct output, what would the latency be in clock cycles?
      There are two answers for c):
      (i) The latency as observed for typical data stream as shown in Figure 18 and 17.
      (ii) The latency, mentioned earlier, that experience has shown gives the most likely bit for
      almost all cases. State the latencies for both (i) and (ii).

Authors Fred Ma, John Knight                January 26, 2001                                        12
                                                                                            Convolution Codes

   e)    If the decoder delays the signal by 12 to 15 clock cycles, would anyone care assuming:
    •     The signal was a digitized phone conversation?
    •     The signal was a www page?
    •     The signal was a digital TV signal?
  6. Problem: How to backtrack.
     Figure 23 is the same as Figure 18 except the numbers are all removed. It still contains
     enough information to trace back from t=n+8.

                                         Retrieving the Original Message                    FIGURE 23

   A             A             A           A          A             A       A       A           4 A

   B             B             B           B          B              B      B       B               B

   C             C             C           C          C              C      C       C               C

   D           D           D               D         D             D         D       D            D
   t=n       t=n+1       t=n+2           t=n+3     t=n+4         t=n+5     t=n+6   t=n+7        t=n+8

      Figure 24 shows a trellis decoder only. It gives no information about the data. Figure 23
      shows paths, but when you trace back to the area between t=n+2 and t=n+3 you cannot tell
      from the figure what the data was.
   a) Use Figure 24 only. If the decoder was in state C at t=n+3, what was the original data (be-
      fore encoding) between t=n+2 and t=n+3? (The obvious answer is right.)
      If it was in state A at t=n+3, what was the original data between t=n+2 and t=n+3?
      If it was in state B at t=n+3, what was the original data between t=n+2 and t=n+3?
      If it was in state D at t=n+3, what was the original data between t=n+2 and t=n+3?
   orig. data                                                                               FIGURE 24
                         Trellis Diagram with no signal knowledge superimposed
          is 0
          is 1       A              A             A                 A        A          A               A

                     B              B             B                 B        B          B               B

                     C             ? C            C                 C        C          C               C

                   D                 D            D                D         D           D             D
                 t=n+2             t=n+3         t=n+4            t=n+5    t=n+6        t=n+7       t=n+8

   b) Figure 25 is the same as Figure 24 except some little squares have been drawn associated
      with each state in each time step.

Authors Fred Ma, John Knight                          January 26, 2001                                      13
                                                                                       Convolution Codes

     • Lab partner one should fill a minimum of information in each square. This information
       would allow lab partner two to back trace knowing that Hc had the minimum Hamming dis-
       tance at t=n+8. Thus by looking only at Figure 25 partner two, starting at state C at time
       t=n+8, should be able to tell what the original bit was between t=n+2 and t=n+3. You may
       establish some conventions like a 1 in the state C box means .... However they must be in-
       dependent of the data.
     • Using the same figure (Fill in the boxes at t=n+3 if you have not done so already) partner
       three should be able to determine the original data bit between t=n+1 and t=n+2.
       You should hand in the filled in Figure 25 and your list of conventions.
                                                                                        FIGURE 25
                  Trellis Diagram on which you will superimpose signal knowledge

                   A            A         A                 A         A            A             A

                   B            B         B                 B         B            B             B

                   C           ? C        C                 C         C            C             C

                  D              D        D                D          D            D             D
                t=n+2          t=n+3     t=n+4            t=n+5     t=n+6         t=n+7       t=n+8
   c) How many bits per step must be stored to allow for backtracking?
   d) Describe the Verilog storage declaration for flip flops to hold the backtracking information.
      One dimension of the array will be the latency.

4.2 Extracting The Original Data.
       Consider Figure 26. The path with the lowest cumulative Hamming distance H , starts at
state C at t=n+8 with H=2. Backing up would take the path to B at t=n+7. The edge is a solid line
which seems to say the original data was 0. Unfortunately we can’t be sure of this. Because of the
convolution code, this path’s H of 2 could increase in the next few cycles and another path might
get the lowest H.

       However if one goes back to t=n+2 and travels ahead in time, only paths that start at D or C
make it all the way to t=n+8. The others die out. Only the path from D has H=2 at t=n+8, thus we
are fairly sure the edge from D at t=n+2 to C at t=n+3 is on the most likely path and the original
data between these two clock edges was 0 (a solid line is 0, a broken line is 1).
       This illustrates why we want to wait six (or usually more) cycles before sending out the out-
put. If we are at time t=n+8, we can be confident that the “0” data at t=n+2 is the most likely.

Carrying the Data Forward Instead of Tracing the Path Back
       Tracing back is a long process and the full trace must be done every data cycle. The back
trace could be done as a FSM but this is convenient only if the clock runs several times faster than
the data rate. However it turns out one can avoid the back trace, and allow the data rate to equal the
clock rate, by sending the data forward through a shift register.

Authors Fred Ma, John Knight                  January 26, 2001                                        14
                                                                                                                                Convolution Codes

                                                                                                                                    FIGURE 26
        input             error                          2nd error
        rec’d     11     01→11              01            00→01          10                   11            11             10
            A          A               A             A               A       3       A                 A           A 100 1 4                A
                   0                                                                      3        2       2          11
                                             2                   2                                                        4


              B         B              B             B               B               B                 B               B                    B
                                             2                2
                                   1                                                                                              1
                                                                             2                                                  01 00 2
              C       C        C                     C               C               C                 C               C                    C


                                                 1             2
                  On best path                                                                3

          D        D       D         D         D      2 D     3 D         4 D                D
          t=n t=n+1 t=n+2 t=n+3 t=n+4 t=n+5                      t=n+6 t=n+7              t=n+8
    One may not be sure which data bit is best at t=n+2. However if one traces the paths forward
    from t=n+2, only two paths survives to t=n+8, and one has a much smaller H.
        Figure 27 shows the essence of this circuit drawn to show feeding forward the ones and ze-
ros as perceived from the data at t=n+2. This data is shifted forward through the flip flops and is
not changed by later inputs. However the path through the shift register is controlled by these later
inputs. At t=n+8, the decoder can supply the data bit originally received at t=n+2. The desired bit
is at the end of the shift register, in the flip flop corresponding to the state with the lowest H .
     Note this is a schematic showing connections. However, for the data in the flip-flops and the
appropriate mux connections, each column represents a different time.
                                                                                                                                FIGURE 27
 Rec’d            01                   01                   10                       11                11                  10
          A                 A                    A                       A                         A               A                    A
                               0                     0                   0                         0               1                    1
          B                 B                    B                       B                         B
                                                                                                                   B                    B
                  0         1                        0                   0                         0               0                    1
                   1        C                    C                       C                         C               C
                                                                                                                            2           C
                  1            0                     1                   0                         1               0                    0

                  0         D                    D                       D                         D               D                    D
                               1                     1                   1                         1               1                    0
        t=n+2        t=n+3         t=n+4            t=n+5        t=n+6     t=n+7          t=n+8
     The data bits at t=n+2 are shifted right each clock cycle. Thus the 0 bit here at the lowest H
     at t=n+8 is the best choice for the data bit at t=n+2. The advantage of the shift register is
     that one does not have to backtrack to know that the data on this path at t=n+2 was also 0.
     Figure 28 shows the same thing as Figure 27 except the muxes are not specifically shown. It
shows how the 4 data bits, inserted in the four best paths at t=n+2, can be shifted from flip-flop to
flip-flop down the paths one clock cycle at a time. They arrive at the output at t=n+8.
       At each cycle the data bit is shifted right into a state controlled by later input data. These
forward paths may disappear, or fork. However the minimum H path never stops, so the “0” inject-
ed into it at t=n+2 appears at t=n+8 in state C, which is the minimum H= 2 path.

Authors Fred Ma, John Knight                                 January 26, 2001                                                                   15
                                                                                                              Convolution Codes

      Compare Figure 28 with Figure 14. Note the path from t=n+2 to t=n+8 is the same. The dif-
ference is the data bit ‘0’was shifted through and comes out at t=n+8 without backtracking.
                    2nd error                                                         FIGURE 28
    Rec’d 01
    input            00→01             10         11         11        10
       A               A               A          A                 A         A      00 1 4 A                   output
                   2    0              0             0              0          1     111    1
       B                                                                                  4 B
             0 2B
                                                                              0                           1

             1 C                       C          C                 C         C
                                                                                                  2 C            best
             1 10                      1          0                 1         0                           0

             0 2D

       D                               D          D                 D         D                           D     output
                        1              1          1                 1         1                           0
    t=n+2          t=n+3           t=n+4         t=n+5  t=n+6 t=n+7            t=n+8
           At t=n+3, one is probably in state C, but because of errors one might be A, B, or D.
         If one is in state C, the decoded data between t=n+2 and t=n+3, would be 0. In state A
   it would be 0, and in B or D it would be 1. We will shift these data bits forward through the
   paths of the trellis diagram, storing the data in flip-flops during each clock cycle.
           Most of the paths die out.
         At t=n+8, the flip-flop beside state C indicates there was a 0 in this path between
   t=n+2 and n+3. This is the same result one got in Figure 18 by tracing the path backwards.

 FIGURE 29: The 0,1,0,1 between t=n+3 and n+4 is carried forward to be used at t=n+9
       Rec’d               2nd error
       input                00→01          10            11             11           10                         00
                   A                   A         A              A             A                       A                   A
                                                                                          4                   00 0 4
                                       0         0              1              1                      1                   1
                    B            0B              B              B             B               4       B                   B
                                  1              0              0             1                       1 10 1
                                                                                                      0               21
                                 1C              C              C             C
                                                                                                                     5 C

                                 00              1              1             0                       1                   1


                                 1D              D              D             D                       D                   D

                                  1              1              1             1                       1                   1
                 t=n+3             t=n+4        t=n+5         t=n+6          t=n+7
                                                                               t=n+8         t=n+9
 The data capture at t=n+3 is carried forward along the paths, if they don’t break. Note the
 selected trellis paths are the same as in the previous figure, but the data stored in the flip-flops is
      Figure 29 shows the next cycle where the 0,1,0,1 data bits between t=n+4 and n+5 are inject-
ed into four paths at t=n+5. Although the paths look the same as in Figure 28, the bits travelling
down them are different unless they coincide by accident. Later we will see that this data can time-
share flip-flops with the data in the previous figures.
      Figure 30 shows the bits that would be injected into flip-flops at t=n+5. This bits would trav-
el down the paths and be available for output at t=n+10.

Authors Fred Ma, John Knight                     January 26, 2001                                                             16
                                                                                                                       Convolution Codes

                   Figure 30 shows another point. Both possible paths coming into each state at t=n+5 are
            shown even though the Viterbi algorithm will discard one. This shows that no matter which path is
            discarded states A and C always receive a “0” and states B and D always receive a “1.” Thus there
            is no need to actually use flip-flops to store the data. It can be hard wired.
              Solid lines are 0             Rec’d                                                                              FIGURE 30
                                            input          10             11               11           10
              dashed lies are 1

                                                                                                                                    Output will not come until t=n+10
                                                A                A                  A            A            4    A
              Note that both paths going
              into state A correspond
                                                                00                  0             1
                                           B                     B                  B            B                 B
              to a data bit of “0,” thus
              one can permanently
              associate state A with “0.”
                                                                11                  0             0                    1
              Also state C can be          C                     C                  C            C            2    C
              associated with “0”
              and, B and D with “1.”
                                                                00                  1             0                0

              In other words the first      D                                        D            D                 D
              column of flip-flops is                              1                  1             1                    0
                                         t=n+4                  t=n+5              t=n+6        t=n+7         t=n+8

                                                                                                                       FIGURE 31
             Rec’d                         2nd error
             input           01             00→01               10                 11            11               10
section 3

                      A                A               A                  A                A            A                          A
                                                       0                  0                0                                       0
                                   00                                                                    0
                      B                B               B                  B                B            B                          B
                                       1               0                  0                0             0                         0
                                  1                                                                                        2
                      C             C                  C                  C                C            C                          C
                                  00                   1                  0                0             0                         0
                      D                D               D                  D                D            D                          D

               Useless ff          11                  1                  1                1             1                         0
                  t=n+2             t=n+3           t=n+4             t=n+5             t=n+6         t=n+7                     t=n+8
                   Figure 31 is like Figure 28 except it shows how the forward path is controlled by multiplex-
            ers. The state and inputs at t=n+k control the mux which selects what will be clocked into the flip-
            flop at t=n+k+1. This will turn out to be the same logic used to select the path with the lowest H .
                    Figure 31 looks like it has 20 MUXs and 24 flip-flops just to forward 4 bits. However:
               a) There is no need to use flip-flops to store the initial constants which are always 0,1,0,1.
               b) The four bits injected at t=n+3 need only four flip-flops at any time. If those 4 bits are shift-
                  ed right the first flip-flops become available to hold data injected later.
                   The complete circuit can be arranged as an unconventional shift register. See Figure 33.
                   Figure 32 shows data injected at three different time steps travelling down the paths. At any
            given time only 4 flip-flops are in use for today’s input set. However 4 more are used for the previ-
            ous set, and 4 more for the set before that.
                   To get Figure 33 from Figure 32, note that at say t=n+6 only one set of flip-flops and MUXs
            is active in each section. Thus at t=n+6 one can overlay the three sections of the figure and ignore

            Authors Fred Ma, John Knight                        January 26, 2001                                                                                        17
                                                                                                                                   Convolution Codes

components operating at any time except t=n+6. The top of Figure 32 has two more sections which
were left out because the figure was too big already. When the five sections are overlaid, and one
extracts all the registers active at t=n+6, one obtains Figure 33
 FIGURE 32:                                          To show three shift registers can be compacted into one
                                                  Only 4 flip-flops in each section are active at say t=n+6, thus only the shaded flip-flops
                                                  are in use. The others only show what is going to be stored later or what was stored
                                                  earlier. This means that at t=n+6 one can erase all but the shaded flip-flops.
              The data is collected between t=n+2 and n+3
              Note it is always the same.

                                                                          #A #B#C#D           MUX control wires     Sections 4 and 5 would be
                                                                     4          4                           4       up here but are not shown.
                                                                                                                  This shows how the data
                                              0            0          0          0                1          1
                                                                                                                  collected between t=n+2
                                                                                                                  and t=n+3 goes through
                                              1            0          0          0                0          1
                                                                                                                  the shift register.
                                                           1          0          1                0          0     To see what is in the shift
                                              0                                                                    register at any given time
                                                           1          1          1                1          0     follow a common time
                                              1                                                                    down as was done for the
                t=n+3                                  t=n+4      t=n+5      t=n+6           t=n+7        t=n+8    shaded MUXs at t=n+6.
               Data from t=n+3 to n+4

                                              0            0          1          1               1           1
                                                                                                                  How the data collected
                                                                                                                  during t=n+3 to n+4 goes
  section 2

                                              1            0          0          1               1           1
                                                                                                                  through the shift register.
                                                           1          1          0               1           1    The control for the MUXs is
                                              0                                                                   represented by the line
                                                                                                                  running through them. This
                                                           1          1          1               1           1
                                              1                                                                   line is a cable and contains
                                                                                                                  4 wires.
                               t=n+4                   t=n+5      t=n+6      t=n+7           t=n+8       t=n+9
                     Data from t=n+4 to n+5

                                              0            0          1         1                1           1    How the data collected
                                                                                                                  during t=n+5 to n+6 goes
                                                                                                                  through the shift register.
 section 1

                                              1            0          0         1                0           1
                                                                                                                  Note all MUXs operating at a
                                              0            1          0         0                1           0    given time, have the same
                                                                                                                  control lines. The top (state A)
                                                           1          1         0                1           0    MUX in each section all use
                                              1                                                                   control wire #A. The bottom
              t=n+5                                    t=n+6     t=n+7      t=n+8         t=n+9         t=n+10    MUXs all use wire #D, etc.

       In Figure 33, four data bits start through the trellis paths in each clock cycle. The MUXs do
not change the bits but only place them in the right path. Since all the columns represent the same
time step all the MUXes are set the same way in each column. Here they are set for t=n+6.

Authors Fred Ma, John Knight                                                         January 26, 2001                                                18
                                                                                               Convolution Codes

FIGURE 33 WARNING: This shows hardware and data at a single time.
              #A #B#C#D         Control wires

         A          4     A             4   A      4     A          4     A             A
     0                     0                1            0                1
         B                B                 B            B                B             B
     1                     0                0            0                1

         C                C                 C            C                C             C
     0                     1                0            0                1

         D                D                 D            D                D             D
     1                     1                1            1                0
     t=n+6         t=n+6          t=n+6         t=n+6       t=n+6            t=n+6
     Column          (i)         (ii)           (iii)        (iv)             (v)
   Shift register structure. The flip-flops contain the data for t=n+6. The 4 path edges selected
   at t=n+6 were made thicker.
    The first three columns contain the data that can be taken from Figure 26. Column (I) contains
   data injected at t=n+2 and one has to go back to Figure 17 to obtain it. Can you calculate the
   data in column (v)? Hypertext link to solution (Figure 45).
   All 5 MUXs in a row are controlled by the same input line, i.e wire #A for the top row, #B for
   the next etc.

4.3 Summary of Circuit Up Through Section 4.4
                               dataIn                Top module
        Test Bench                                                                          Encoder
                               reset                  Encoder
       Signal Source            clk
       Comparison                                             serial_in
       with original                                         Error generator
       (loopback)                                           serial_in_err
                                                       Top module         serial_in_err
                                dataOut                                            Parallel

                    Calc_Came_From_and_Ham_Dist                           Data_Shift_Forward
                    input clk, reset, convSig[2:1];                input clk, reset, came_from[4:1];
                    output dataOut;                                //maybe input HA,HB,HC,HD;
                                                                   output dataOut;

Authors Fred Ma, John Knight                    January 26, 2001                                             19
                                                                                                  Convolution Codes

4.4 Second Lab: Start of Convolution Decoder in Verilog
      At this point the lab is starting to switch from a lab to a project. It is now you need to know
where you are going. You should be able to recognize each block in the block diagram. The
Data_Shift_Forward block has been described in the theory. However it will not be done until Ex-
ercise/Lab 3.
You should consider these concepts:
   a)    Normally the encoder and decoder are widely separated so they cannot run from a common
        clock. The decoder will have a clock recovery module. This is beyond 97.478 and we will
        use a common clock for both.
   b) Your design will be a rate=1/2, constraint length=3; [111],[101] decoder.
      This is to make it easy to check things by hand or from books.
   c) To save work you will want to parameterize your design. One can do this automatically in
      Verilog for some parameters. For others it too much trouble.
    • First, design a distinctive comment style like
                /*|Para|* comment on parameters *|Para|*/
      which indicate code where there are parameters nearby which will need attention. In your
      comments cross-reference all the modules that are effected by the parameters.
    • Second, there are two ways to pass parameters in Verilog. Which one works for synthesis?
   d) Considerable emphasis will be given to testing. One simple test is a loopback test where the
      output is sent back to the input and the two compared. Other thing you can do to your circuit
      to aid testing will be considered later.
   e)    The Error Generator block is necessary if you want to simulate to the error correction prop-
        erties. First it will be done as a test bench so it is only useful during simulation. Later you
        might consider making it part of the loopback test so it can be used for testing in the field.
 What to do for the lab
  1. Draw a block diagram somewhat like that of Section 4.3 on page 19. 1However make it big-
     ger and show the arguments passed to all modules. If a module will be over a page of code,
     try to divide it.
  2. Write Verilog for the Decoder Top Module and Encoder Top Module (already done?)
  3. Design a serial to parallel module. The serial_in signal changes at twice the clock rate. Let
     the serial_in bits be labelled s, e, r, i, a, l ...
     Decide how these bits will come out of a transparent-high latch.See the latch_sig below.
     You will probably use a transparent latch and two flip-flops in the module.
                 serial_in                                 serial_in s      e    r       i    a       l
                or serial_in_err
                                      C1                  latch_sig         s
           1D                      Transparent-           ConvSig[1]             s            r
            C1                      high latch            ConvSig[2]             e            i
                           C1                                                                FIGURE 34
                                            Waveforms for serial to parallel

1. We like originality in block diagrams as long as you can give a reason for changes.

Authors Fred Ma, John Knight                   January 26, 2001                                                 20
                                                                                                      Convolution Codes

  4. Write the Verilog code for the serial to parallel module.
     How do you write a latch in Verilog? Hints, see Figure 46.
  5. Write the Calculate Next State and Hamming Distance module. (See Exercise 2.)
  6.    Modify the Test Bench to handle the decoder                   // send in a new x every clock cycle
       and the encoder. This should include a loop-                   always @(posedge clk)
       back test which compares the dataIn (x on the                    begin
       right) with dataOut.                                                if (I==9) $finish;
       You will have a delay (latency) between dataIn                       x<= #1 data[I];
       and dataOut. At the start dataOut will be the bit                    if(I>latncy) y<=#1 data[I-latncy];
       corresponding to the present lowest H (cumula-                      I<=I+1;
       tive Hamming distance) so the latency will be                     end
       only that of the serial-to-parallel converter. Lat-              assign err=(y!=dataOut) FIGURE 35
       er you will want to add a latency of 4 to 5 times
       the constraint length.
  7. Add to the                                                                                         FIGURE 36
                                                              input 11
       module to generate a four-bit signal        3 A       00 2 5                       A came_from[0]=down
       called came_from. These signals in-                        110                 2
       dicate whether the trellis lines lead-                                         3
                                                   3 B                    0               B came_from[1]=up
       ing back from the next states to the
                                                                      11 0 2 5
       present-time-step states, came from a                             0 10 0
       higher state or a lower state.                                   01      3
                                                   2 C                        2           C came_from[2]=up
        Thus it would show whether the                                    3
       next state A came from the present A                           1
       (up) or C (down). Figure 36 shows           2 D                        10 1 3 D came_from[3]=down
       these bits and their meaning. These          t=now                           t=next step (now + 1)
       will be the MUX control signals to
       shift the data forward.
  8.    Then write a preliminary Data_shift_Forward module “stub” which has input declarations
       for these four signals but no code to do anything with them, at least not yet.
  9. Consider the Error Generator. For the moment treat it                                               FIGURE 37
     like a test bench so you can use nonsynthesizable                            reg [4:0] randy;
     constructs like $random. This gives a new random                             always @(clk) begin
     integer every time it is called. Try to make it so there                     //Run at twice clock rate
     is an error every 16 time steps (every 32 serial_in bits)                    //randy gets the 5 lsb of $random
     on average. A random 5-bit number will be 01110 (or                              randy <= $random;
     any single value) one time out of 32 on average.                                 if (randy = = 4’b01110)
     Alternately you might try a pseudorandom generator                                   serial_in_err<= ~serial_in;
     as used to be done in 97.350. There is a lot about
     pseudorandom generators in the notes.

Authors Fred Ma, John Knight                  January 26, 2001                                                      21
                                                                                                                                   Convolution Codes

4.4.1 Feed Forward, an Alternate Viewpoint

     D     C B       A         Input 11            11          01          01         10         11          11          10         00
                                   n+0      n+1         n+2         n+3         n+4        n+5        n+6         n+7     n+8
   “State” Inputs
     1 0 1 0                       1010 1010 1010 1010 1010 1010 1010 1010 1010

                                            1100 1100 1100 1100 1100 1100 1100 1100

                                                     0001 0111 0111 1000 1101 1001 0000

                                                                  0000 1011 0111 1100 1011 0011

                                                                                0000 1111 0011 1001 1111

                                                                                           0000 1111 0110 0011

                                                                                                      0000 1111 1100

                                                                                      Output            0           1          1
 Direction of                            \\/\     ///\    /\\\            /\\\ \//\              \\/\       \//\        ////       //\/
 FIGURE 38 The horizontal axis is time. the vertical axis shows the circuit (space). The table
 shows how the “state” input bits shift through the flip-flops with time.
   Boxes in the same row show the contents of the same four flip-flops, each box shows a
 different time.
   Boxes in the same column show the flip-flop contents at a given time.
   The “\” and “/” symbols at the bottom show the direction the mux inputs came from. In each
 time step the six muxs in a column have the same control signal.

4.5 Third Exercise: Forward Tracing
  1. Problem: Walk-through of the data-shift-forward algorithm
      Figure 39 through Figure 44 show one step of the trellis on the left, and the circuit to imple-
ment the shift forward on the right. You will fill in the data as it exists in the circuit.
      It is important to note the circuit only shows data at one time, t=now. The trellis diagram
shows more than one time. In the circuit you will show the data at the flip-flop’s D inputs ready to
be stored and the likely different data stored inside the flip-flop.

  2. Problem: Assign a group member to clean up unfinished parts from Lab 2.
  3. Problem: Write pseudocode for the Data_Shift_Forward module
   a) The latency will be a parameter which will effect this module and the loopback test.
      You will want to define this parameter from the top module (or maybe the testbench) and
      pass it down. Write down how to do this.

Authors Fred Ma, John Knight                                  January 26, 2001                                                                   22
                                                                                                                 Convolution Codes

                               decoded bit between t=now and t=now+1 for state A                                     FIGURE 39
    rec’d     01                           01                            If you know the present and next trellis
       A               A   o           A            A                    states, then you know what the proper
                   2                            2                        decoded output bit is.
                                                                         You can guess the states by choosing the
        B    02        B               B   0 B                           lowest H but often you must wait several
                                                                         steps to be sure.
             1                             1
                       C               C   13C
             0                             0

        D    13        D               D
                                      t=now t=now+1
    t=now        t=now+1
    a) Fill in the blanks showing the candidate decoded bits between t=now and now+1
        for each state in these two typical trellis steps.

                                                                                          #1 #2 #3 #4                FIGURE 40
   Here we inject the data associated           input
   with each path into the initial flip          rec’d       01
                                                                                      A           4          A
   flops of the feed-forward shift
                                                   A                 A                                       X
   register.                                                     2
                                                                                              0                      Unknown
                                                                                              0                      We haven’t
   b) At the D-input to each                                                          B                      B       put anything
      flip-flop, show the bit that                     B     02        B
                                                                                              1              X       is in these
      will be stored on the next                                                                                     flip-flops
      clock after t=now.                         1         1                          C       1              C
                                                                                                                     at the start
                                                     C               C                                 0 X
      State C has it written in                                1                              0
      already.                                   1
                                                          0                                   0
                                                   D      13     D                    D
                                                                                              1              D        D input
                                                t=now          t=now+1                                       X        to this
                                                (t=n+2)        (t=n+3)                        1

                                                          TRELLIS                                 CIRCUIT

 The clock has advanced one                                                                                          FIGURE 41
                                                                                      #1 #2 #3 #4            Control wires
 cycle from Figure 38.                      input        2nd error
                                            rec’d         00→01
                                                                                  A           4        A         4         A
c) Fill in the data on the D inputs             2 A                  A
   in column (i), and also what                                  2                            0
   was clocked into the column                                                    B                    B                   B
   (i) flip-flops (Q).                            2 B        0         B
     Fill the column (ii) D in-                            1
                                                             2                                1
   puts.These will be shifted from              1 C                              C                     C                   C
                                                                 3 C                                                   1
   column (i) along the best four                          0                                  0

                                                 3 D       1    D                 D                    D                   D
 The first row of muxes is shown                 t=now        t=now+1                          1        1
 with dashes because they are                   (t=n+3)      (t=n+4)                t=now
 redundant.                                                                     D                      (i)                 (ii)

Authors Fred Ma, John Knight                         January 26, 2001                                                             23
                                                                                                                              Convolution Codes

  the up or down position                                  UP #1                                         Control wires             FIGURE 42
                      input                                   #2
                      rec’d 10                                #3            A                       A     4            A       4            A
                              3 A                             #4
  The first column       2 A              0                                          0

  of muxes is                  3         1
  slowly being                                                              B                       B                  B                    B
  removed from the      2 B      B


  picture.                     2
                                3 C                  C                      C                       C                  C                    C

                                2 D         2 D
                                         1t=now+1                           D
                                                                                                    D                  D                    D
                               t=now                                                1               1


                               (t=n+4)       (t=n+5)
                                                                            t=now              (i)                 (ii)                 (iii)
     d) Continue writing in D and Q for the flip-flops.
       Also write in whether the control wires will switch the muxes to up or down.

                                                             #1 #2 #3 #4                Control wires                         FIGURE 43
                          rec’d      11
                                                                                         4                 4                    4               A
 The 1st column                                               A                 A                    A                    A
 of MUXes has                3 A             2
 been removed.                       1 3                                        B                    B                    B                     B
 We don’t need                                                B
                             3 B     0 B
 them. The shad-                                                     1
 ed flip-flops will                    03                                         C                    C                    C                     C
 be removed in               2 C                 C            C
 the next figure.                                                     0
                             2 D     13     D                                   D                    D                    D                     D
                           t=now         t=now+1                     1
                           (t=n+5)       (t=n+6)
                                                                             (i)             (ii)           (iii)                       (iv)
     e) Continue writing in D and Q for the flip-flops.
                                                             #1 #2 #3 #4                Control wires                         FIGURE 44
                     rec’d         11
                                                                                         4                 4                    4               A
                                                               A                A                    A                    A
                         2 A             3
                                   1 2                         B                B                    B                    B                     B
                         3 B       0 B                                   1
                                   04                                                                                                           C
                         2 C                 C                 C                C                    C                    C
                          2 D     14    D                      D                D                    D                    D                     D
                         t=now       t=now+1                             1
                        (t=n+6)        (t=n+7)                     t=now
    f) Complete filling in the Q outputs.
        At now which is also t+6, we know the best path ends on B.
    g) How do you find what the data value on that path was between t=n+2 and n+3?

Authors Fred Ma, John Knight                             January 26, 2001                                                                           24
                                                                                   Convolution Codes

   b) Develop pseudocode to implement the forward shift registers. A hint as to a possible meth-
      od follows:
      Define four registers in the form of:
           reg [1:latency-1] Areg, Breg, Creg, Dreg;
      Then consider-
           if (came_from[A]) AregNxt ={0,Areg}>>1; else AregNxt={0,Creg}>>1;
      Watch out whether you shift in a 1 or a 0. on the left.
      The following code may give you some ideas:
          parameter lat=12; // latency
          parameter A=0, B=1, C=2, D=3;
          reg [1:lat] Areg, Breg, Creg, Dreg; //Storage
          reg [1:lat] Anxt, Bnxt, Cnxt, Dnxt;    //Not storage
          always @(came_from or A reg or Breg or Creg or Dreg)
                 if (came_from[A])Anxt={1'b0,Areg}>>1;
                                else Anxt={1'b0,Creg}>>1;
                 if (came_from[B])Bnxt= whatever;
                 if (came_from[C]) Cnxt= ...;
                 if (came_from[D]) Dnxt= ...;
          always @(posedge clk or posedge reset)
                 Creg ...
                 Dreg ...
                if (reset) begin
                      Areg<=0; Breg<=0; Creg<=0; Dreg<=0;
   c) Decide a strategy to get the dataOut bit. Do you take the one on the best path? Do you take
      the majority of the four? Do you take the first one and assume the others will be the same?
      Write some pseudocode to implement your strategy to get the dataOut bit.

Authors Fred Ma, John Knight                January 26, 2001                                     25
                                                                                                               Convolution Codes

4.6 Some Hints and Answers
         Solution: to Figure 33. (back)
                                                                                                                   FIGURE 45

   A            A              A           A               A           3        A           A 1                      A
          0                                                                                     10

                                       2               2               3                           2           3
   B            B              B           B               B                    B           B          0             B
                                       2                                                          11
                         1                                                                             10 1
   C            C              C           C               C                    C           C                        C
                                       1               3


   D            D          D             D               D                 2     D      3  D    10 1 4                D
   t=n        t=n+1      t=n+2         t=n+3           t=n+4                   t=n+5    t=n+6                       t=n+7

                     0             0              1                1                1       1              1                1

                     1             0              1                1                1       1              1                1

                                   1              1
                     0                                             0                1       1              1                1

                                   1              0
                     1                                             1                1       1              1                1
               t=n+1           t=n+2           t=n+3           t=n+4            t=n+5   t=n+6     t=n+7               t=n+8

                    0              0              1                1                1       0              0

                    1              0              1                1                1       1              0

                    0                             1                1                0       1              1

                    1                             0                0                0       0              1

               t=n+2           t=n+3       t=n+4               t=n+5            t=n+6   t=n+7     t=n+8

 FIGURE 46. How to code a latch                (Back)
         Latches have something happen on both edges. Do not use posedge clock.
         When transparent, latches must follow the data. You need more than @(clock).
         Put the reset for the latch in the procedure for the latch, not with some stray flip-flop.
         Latches cannot be put in the same procedure as flip-flops.
         Do not put logic in the same procedure as the latch.

Authors Fred Ma, John Knight                               January 26, 2001                                                     26

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