2-BIT ADDER CARRY AND SUM LOGIC CIRCUITS CLOCKING AT 19 GHZ CLOCK FREQUENCY IN TRANSFERRED SUBSTRATE HBT TECHNOLOGY T. Mathew1 , S. Jaganathan2 , D. Scott1 , S. Krishnan1 , Y. Wei1 , M. Urteaga 1 , M. Rodwell1 , S. Long1 1 Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA-93106, USA 2 GTRAN Inc, Newbury Park, CA-91320, USA Abstract We report carry and sum circuits for a 2-bit adder. The 2-bit adders are designed to be part of a pipelined 2N-bit adder-accumulator. The ICs clock at a maximum of 19 GHz and were fabricated in InAlAs/InGaAs transferred substrate HBT technology. To obtain high clock rates in a design with multiple gate delays, we have employed a novel merged AND-OR logic structure using 4-level series-gated current-steering logic. Further, this logic is merged with the synchronizing latch circuit so as to minimize the overall gate delay. The 2-bit carry circuit has 250 transistors, a maximum clock frequency of 19 GHz, and dissipates 1.2 W. The sum logic circuit of a full adder was realized as a 4-level series-gated ECL XOR gate. This circuit has a maximum clocking frequency of 24 GHz, has 150 transistors and dissipates 750 mW. accumulator digital word width . This work focuses I. Introduction on increasing the maximum clocking rate of the adder- accumulator. Fast sine ROM and DAC’s are other Direct digital frequency synthesizers (DDFS) significant DDFS design challenges. offer several advantages over phase locked loop (PLL) based synthesizers in commercial frequency hopped II. Adder-accumulator architecture communication systems, radars, and radar jamming applications [1,2]. The advantages include precise The carry and sum logic circuit discussed in this frequency control, fast and phase continuous frequency paper form the building blocks of a 2N-bit pipelined switching, and excellent temperature and aging stability adder-accumulator. A 8-bit pipelined adder-accumulator [1,2]. The block diagram of a DDFS system is shown in architecture is shown in fig. 2. Pipelining the inputs to fig. 1. A digital signal processor (DSP) outputs a digital the adder allows one to trade latency for maximum phase increment word ∆φ(t), which is added to the clocking frequency. Latency is defined as the time delay existing phase value φ(t) in the accumulator. The adder- between a change at the input end and the resulting accumulator (phase accumulator) outputs the digital change in the output. The inputs of the adder- phase word φ(t+∆t) which addresses a sine ROM. The accumulator are delayed in increments of the clock output of the sine ROM is the digital word representing period. Correspondingly, the outputs are also delayed to sin φ(t +∆t). The D/A converter converts the digital word realign the outputs in time. The maximum clocking corresponding to sin φ(t+∆t) to its analog form. frequency of the 2-bit adder is limited by the carry propagation delay. The next section details the design of PHASE SINE DSP ACCUMULATO R ROM DAC the carry and sum logic circuits. ∆φ(t) φ(t+∆t) sin φ(t+∆t) III. 2-bit adder circuit design CK CK CK Fig. 1: Simplified block diagram of a DDFS system. The sum and carry logic realization for a full adder is shown in Fig. 3 . A0 and B0 are the 2 adder The frequency tuning range of DDFS systems is inputs and Cin is the carry input to a full adder. The sum f from dc to ~ ( ck max /3), where fck max is the maximum (S0 ) logic can be realized using a 3-input XOR gate. The clock frequency of operation . The frequency carry (Cout ) generation requires an AND-OR logic resolution is given by ∆f = fck/ 2N , where N is the phase operation (fig. 3). Hence the carry logic circuit sees two further 48% improvement. The block diagram of the 2- gate propagation delays (i.e. Tpd carry = 2 Tgate) whereas bit adder carry logic is shown in fig. 6. Fig. 7 shows the the sum logic circuit sees a single gate delay. sum logic circuit realized by merging the 3-input XOR gate and the master-slave latch. The circuit diagrams are S0 S1 S0 shown in fig.11 and fig.12. A0 2 Bit Add er R R R R S1 A1 CK CK CK CK a C rry out C2 S2 S3 A2 S2 2 Bit Adder R R R S3 A3 CK CK CK C rry a out C4 Out = AB + BC + A C S4 S5 A4 S4 2 Bit Add er R R S5 C in Bi B i+1 A5 CK CK Carry B B A A out C6 S6 S7 Ai A6 S6 Si R 2 BIT A7 2 Bit Adder S7 ADDER Si+1 CK A i+1 Carry C o ut out C4 A A B B Fig. 2: Block diagram of an 8-bit pipelined adder C C . A0 A0 B0 S0 Cin Cin B0 Fig. 5: Circuit diagram of the 3- level series-gated AND- OR gate that generates the carry output. Fig. 3: Sum and carry logic realization in a full adder. LOGIC STAGE LOGIC STAGE The full adder implementation is extended to LAT CH LATCH A0B0+B0C in+ A0C in STAGE C A1B1+B1C 1 in+A0C1 in STAGE realize the 2-bit adder block shown in fig. 4. Latches are C in 1 in C out needed at the outputs of the 2-bit adder for pipelining the carry bit and realigning the outputs in time. The latched sum output bits are fed back as input to the adder to CK CK CK CK perform the add and accumulate function. As is evident from fig. 4, the carry logic circuit is the critical delay path and limits the maximum clock frequency. Circuit simulations indicate that the maximum clock frequency for the carry logic circuit to be approximately 23 GHz. Fig. 6: Carry logic realized by merging the AND-OR gate with the synchronizing latch. A0 A1 INPUT STAGE B0 D Q B1 D Q S0 S1 LATCH ECL C in CK C Q CK C Q Cin A +B+C STAGE LATCH C 1 o ut S0 CK CK A0 A1 C 1 o ut CK CK C in D Q C 2 ou t B0 B1 CK C Q Fig. 4: Typical implementation of a 2-bit adder. In the Fig. 7: Sum logic realized by merging the XOR gate with case of an adder-accumulator, Bi = S i. the master-slave latches. The AND-OR logic required to generate the carry bit can be realized as a single 3-level series-gated IV. InAlAs/InGaAs transferred substrate ECL logic gate. This is shown in fig. 5. The carry logic HBT technology realized using this AND-OR logic gate shows a 40% improvement in clocking speed as compared to the Transferred substrate HBT technology has earlier approach. A further increase in clock speed can demonstrated excellent RF performance with peak ft and be achieved by merging the master-slave latch and the fmax of about 300 GHz and 800 GHz respectively [4,5]. AND-OR logic gate, resulting in a 4-level series-gated Circuits fabricated in this technology include small structure shown in fig. 6. Simulations indicate that this signal amplifiers, flip flops configured as frequency approach provides a 40 GHz clock rate, which is a dividers, and oversampled A/D converters [6,7]. The process starts with process steps similar to had a maximum clock rate of 24 GHz. The output that of mesa HBT processes. The process steps include waveforms measured on an oscilloscope are shown in emitter and base metallization, emitter/base mesa fig. 13 and fig. 14. isolation, junction passivation and interconnect metallization. After front side processing, Benzocyclobutene (BCB) is spun on the wafer, and gold ground plane plating is carried out. The InP wafer is then inverted and bonded on to a GaAs carrier wafer and the InP substrate is then removed to contact the collector layer. The wafer cross section after bonding is shown in fig. 8. The presence of a continuous gold ground plane provides for a low dielectric constant microstrip wiring environment. The ability to lithographically define the collector contacts directly opposite to the emitter leads to significantly lower collector-base capacitance as compared to triple-mesa HBT processes. trans istor resis tor capacitor microstrip bypass capacitor Fig. 9: Chip photograph of the carry logic circuit. C B E BCB gold thermal v ia ground gold ground plane via In/P b/A g solder G aAs car rier wafer metal 1 polyimide metal 2 SiN NiCr contact Fig. 8: Cross section of a transferred substrate HBT wafer after bonding. V. Measurements and results The chip photograph of the carry and sum logic Fig. 10: Chip photograph of sum logic circuit. circuits fabricated are shown in fig. 9 and fig. 10. HBTs with 3.0 x 1.0 µm2 emitter and 4.0 x 2.0 µm2 collectors VI. Conclusion were used. These transistors exhibited an ft and f max of 170 GHz and 180 GHz respectively at Vce = 1.0 V and Je A new 3-level series-gated current-steering = 1.0 mA/µm2 . DC measurements indicated a current logic to realize the carry logic of a full adder was gain β of approximately 5 to 6. These transistors can presented. The carry logic gate was then merged with the operate at a peak current density of 1.5 mA/µm2 and a synchronizing latches to improve the clock rate in a Vce < 1.5V. The low current gain was due to problems pipelined adder-accumulator application. The 2-bit adder associated with base band gap grading during the carry logic and sum circuits were fabricated in epitaxial growth. InAlAs/InGaAs transferred substrate HBT technology and had maximum clocking frequencies of 19 GHz and The circuit diagram of the fabricated 2-bit adder 24 GHz respectively. It is likely that the low current carry logic circuit is shown in fig 11. Fig. 12 shows the gains (β ~5-6) led to reduced frequency of operation. sum logic circuit diagram. For testing purposes the Simulations indicate that clock frequencies of 40 GHz circuits were configured as static frequency dividers. should be possible. This involved setting the inputs to either logic high or logic low and feeding back the carry/sum outputs VII. Acknowledgement appropriately. This is indicated in fig. 11 and fig. 12, and was realized on chip using resistors and current sources. This was supported by the Office of Naval The clock input was applied to the circuits and the Research under ONR-97:N0014-98-1-0068. maximum clocking speed for a divide by two operation was determined. The carry logic circuit exhibited a maximum clocking rate of 19 GHz and the sum logic VIII. Bibliography and references . A. Edwin, “Direct Digital Synthesis Applications”’ . Q. Lee et al, “Submicron transferred-substrate Microwave Journal, Vol. 33, No :1, pp. 149-151, January heterojunction bipolar transistors with greater than 800 1990. GHz f max”, IEEE conference on Indium Phosphide and . V. Manassewitsch, “Frequency Synthesizers Theory Related Materials, May 1999. and Design”. New York, Wiley-Interscience, 1980, pp. . T. Mathew et al, “75 GHZ static frequency divider 37-43. in transferred substrate HBT technology”. Submitted to . C. G. Ekroot and S. I. Long, “A GaAs 4-bit Adder- IEEE conference on Indium Phosphide and Related Accumulator Circuit for Direct Digital Synthesis”, IEEE Materials, Nara, Japan, 2001. Journal of Solid State Circuits, Vol. 23, No:2, pp 573 – . S. Jaganathan, et al “An 18 GHz continuous time 580, April 1988. Σ − ∆ modulator implemented in InP transferred . Y. Betser, et al, “InAlAs/InGaAs HBTs with substrate HBT technology”, IEEE GaAs IC symposium, simultaneously high value of ft and fmax for mixed signal Seattle, WA, November 2000. analog/digital applications”, IEEE Electron Device Letters, pp 56-58, Vol 22, No:2, Feb 2001 C 2ou t = A 1 B 1 + B 1C 1 + A 1 C1 C 1ou t = A 0B 0 + B 0 C0 + A 0C 0 C 2ou t = A 1B 1 + B 1C1 + A 1C1 C 1o ut = A 0B 0 + B 0 C0 + A 0 C0 LAT CH STAGE C0 C0 C1 C1 C1 C1 B0 B0 B1 B1 C1 C1 B0 B0 C0 C0 B1 B1 C1 C1 C1 C1 A0 A0 LOGIC ST AGE A1 A1 CK CK CK CK D IODE L EVEL SH IFT ER B 0 = B1 = Hig h ( 0.0V ), A0 = A1 = L ow ( -0.3V) , C0 = C2out for t esting Fig. 11: 2-bit adder carry logic circuit. 0 f = 24GHz, f = 12GHz LATC H LATC H FOR PIPE LINE ck. max out S TA GE DE LAY -0.05 S 0 = A0 + B0 + C 0 Vout(Volts) C0 C0 C0 S0 = A0 + B0 + C0 -0.1 B0 B0 B0 A0 3 I NPU T XOR A0 -0.15 CK CK CK CK -0.2 0 100 200 300 400 500 600 C0 = High (0.0V ), A0 = Low (-0.3V), B 0 = S0 for testing Time (ps) Fig . 12: Sum logic circuit with latches at the output Fig.14: Output waveform of the sum logic circuit for a 24 GHz clock input. 0 f max ck = 19GHz, fout = 9 .5GHz -0.05 -0.1 Vout(Volts) -0.15 -0.2 -0.25 -0.3 0 100 200 300 400 500 Time(ps) Fig. 13: Output waveform of the carry logic circuit for a 19 GHz clock input.
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