Development of a RF Bipolar Transistor in a Standard
0.35µm CMOS Technology
I-Shan Michael Sun and Wai Tung Ng
University of Toronto, Dept. of Elec. & Comp. Engineering
10 King’s College Road, Toronto, Ontario, M5S 3G4
Tel: (416) 978-6249 E-mail: email@example.com
and Philip K.T. Mok
Hong Kong University of Science & Technology, Elec. Engineering
Clearwater Bay, Kowloon, Hong Kong, China
and Hidenori Mochizuki, Katsumi Shinomura, Hisaya Imai,
Akira Ishikawa, Nobuo Saito, Kiyoshi Miyashita, Satoru Tamura, Kaoru Takasuka
Asahi Kasei Microsystems Co., Ltd.
Atsugi AXT Maintower, 3050 Okada, Atsugi, Kanagawa 243-0021, Japan
ABS T RACT A RF Bipolar Transistor integrated to a standard 0.35µm CMOS process is
presented. This BiCMOS technology features a single-poly NPN transistor with simulated
performance of fτ = 16GHz and BVCEO = 6.4V. With implanted base and no trench isolation, this
device offers full compatibility with standard CMOS technology at the cost of three additional
mask layers, while demonstrates good performance compared to previously published BiCMOS
Key Words 0.35µm CMOS Technology, RF Silicon Bipolar Transistor, cutoff frequency fτ
Recently, the market for analog RF LSI’s for mobile communication has been growing rapidly.
This trend pushes the need for new processing technologies that can achieve higher operating
frequency, lower power consumption and more compact system integration . The
development of main stream CMOS technology has been moving along this trend. With gate
length reduces to 0.1µm expected in 2002 , next generation CMOS technology will have
further improvement in performance and increase in transistor density. However, most standard
CMOS processes are presently used to design baseband and digital circuits only. When CMOS
is used in radio frequency circuits, it does not perform as well as other processes such as GaAs
FETs, SiGe HBTs and Si BJT.
Traditionally, GaAs or InP technologies are the most prominent candidates for implementation
of RF circuits. However, due to improvements in processing and material growth technology,
silicon bipolar transistor and SiGe base bipolar transistors are now capable of similar
performance with respect to the more expensive III-V compound semiconductor technologies
. Consequently, if a high frequency RF device can successfully integrated to a standard
CMOS process, this technology can offer full integration from analog baseband circuitry to radio
frequency circuits, with digital functions and programmability.
It has been demonstrated that GaAs offers superior fτ and power added efficiency (PAE) , but
is very expensive and is impossible to integrate with CMOS on silicon (refer to Table. 1).
MOSFETs in a standard CMOS process have good frequency performance, a 0.25µm NMOS
typically has fτ in the range of 20GHz. However, the MOSFETs fundamentally have higher
noise figure and poor linearity compare to other competing technologies. Also, the current level
needed to bias the MOSFET at peak fτ is significantly higher, which results in higher power
consumption. Even though a large amount of literatures have demonstrated the feasibility of
CMOS technology in RF applications , no commercial product has yet to be manufactured.
In comparison, SiGe HBT has better fτ performance than Si BJT and both can be integrated with
CMOS. However, Si BJT is less complex to integrate and can significantly reduce both the cost
and the time to market. Consequently, this paper presents the integration of a silicon based RF
bipolar transistor in a standard 0.35µm CMOS technology. The design motivations and
challenges for this project are outlined in section II. The detail process flow and structure are
described in section III, while simulation and fabrication results are presented in section IV.
Table 1: Comparison for performance parameters of various technologies .
fτ fmax On
Technology NF PAE Linearity Cost Process
(GHz) (GHz) Silicon
GaAs HBT 100 100 Fair Excellent Good Expensive Complex Impossible
SiGe HBT 120 120 Fair Good Fair Expensive Complex Possible
Fair Good Least
Si CMOS 135 N/A Fair Cheapest -
(1GHz) (2GHz) complex
Si BJT 50 40 Good Fair Good Inexpensive Moderate -
II. D E S I GN O B J E C T I V E S A N D C H A L L E N GE S
The objective of this work is to integrate a RF silicon bipolar transistor in a standard 0.35µm
CMOS process that adds a minimum number of processing steps and avoids changes to the
electrical characteristics of the CMOS transistors. The motivation is that it allows the possibility
of integrating both Si BJT-based RF/IF circuits with CMOS-based DSP and Digital Control
circuitry on the same chip. By using least possible number of additional processing steps, the
extra cost and the complexity of this process can be minimized. Also, by carefully choosing the
insertion points for the additional processing steps, the original electrical characteristics of the
CMOS transistors are preserved. This can save time for re-modeling the CMOS transistors and
speed-up the overall product development cycle time.
With the introduction of 0.25µm, 0.18µm, and even 0.12µm channel width CMOS technologies
in recent years, the presented integration is not limited to a 0.35µm CMOS process. One can
simply follow the same design guideline in this work to integrate the RF BJT in any CMOS
compatible process. However, choosing a 0.35µm lithography process has several significances:
First, the lateral scaling of the BJT has limited effectiveness on fτ improvement . Therefore,
using a smaller lithography process results in higher costs but minor improvement on fτ.
Secondly, with the introduction of more advanced CMOS technologies, the 0.35µm CMOS
processes are rapidly approaching their end-of useful life. Furthermore, 0.35µm CMOS
processes are primary 6-inch wafer technology. This leaves silicon foundries with little options
for process improvement, because fabrication equipments for finer lithography resolution are
only made for 8-inch (or larger) wafer size. This means that if the silicon foundry wishes to
advance from 0.35µm to 0.25µm CMOS technology, an entirely new production line has to be
built with new equipments. As a result, additional feature such as the presented RF BJT is a
welcomed upgrade for the standard 0.35µm CMOS process to in order to maintain a useful
The challenge of this work is that all process modifications must be compatible with the standard
CMOS process. Specifically, special process techniques used by advanced RF BiCMOS process
such as deep or shallow trench isolation, selective epitaxial-base growth (silicon or silicon-
germanium), and double poly-silicon structure  are not considered for implementation.
Furthermore, the construction of the BJT has to selectively incorporate several optional process
modules such that they do not interfere with the original CMOS process flow. If these optional
modules were not used, the process flow should be able to revert to the original standard CMOS
process without changes. Therefore, the room for optimization of the transistor characteristics is
very limited. Nevertheless, this work is not designed to be a competing technology performance
with current state of the art RF BiCMOS technologies, the main goal is implementing a truly
CMOS compatible process.
I I I . PROCES S FL OW AND S T RUCTURE
This BiCMOS process uses an existing 0.35µm CMOS production technology from Asahi Kasei
Microsystem (AKM) as the base process. Added to this CMOS process, are an additional n+
buried layer, a p-type epitaxial deposition, a deep n-well implant, a p-base implant and a poly-
emitter deposition for building the RF bipolar transistor. The process flow is as depicted in Fig.
1. The added processing steps and thermal annealing for the bipolar transistor are mostly done
before the processing steps for CMOS. Therefore, these added steps result in little effect on the
CMOS device characteristics. The cross-sectional diagram of the RF bipolar transistor is as
shown in Fig. 2.
The new process starts with the same p-type substrate as the CMOS. It is followed by the n+
buried layer implant for the BJT to reduce collector resistance, RC. Then, the p-type epitaxial
layer with the same concentration as the substrate is deposited. This allows the CMOS device to
form on the same substrate as the original CMOS process. In order to achieve high BVCBO for
the BJT, the collector width has to be relatively wide to avoid avalanche breakdown. This is
done by the deep n-well diffusion that provides a large collector width and makes contact with
the buried layer. Following this, the original n-well and p-well implant and diffusion for the
CMOS are performed.
The shallow base region for the BJT is then implanted. The concentration and width of the base
region are selected to optimize BVCEO and fτ. These two criteria are inversely proportional and
govern by the Johnson’s Limit . After the gate oxidation and gate poly deposition, the gate
oxide is etched selectively and poly-silicon is deposited on top. The poly-silicon is doped and
annealed to form the n+ emitter region. Subsequently, the rest of the remaining standard CMOS
processing steps are performed unaffected.
IV. S I MULATION AND FABRICATION RES ULTS
The device structure is simulated using TSUPREM4 and the SEM micrograph of the cross-
section of the fabricated bipolar device is as shown in Fig. 3. This micrograph shows the n+
diffusion formation under the poly emitter, implanted shallow base junction and the p+ diffusion
for the base contact. The width of the poly-emitter window is 0.4µm, while the separation
between the Base-Emitter and Base-Collector contacts are at the minimum size allowed by the
design rules. This minimizes the parasitic capacitance between Base-Collector and Collector-
Substrate junctions and increase the fτ of the transistor.
The electrical characteristics of the device are simulated using MEDICI. The simulated fτ and
BVCEO for this device are 16GHz and 6.4V, respectively. The simulated fτ vs. IC characteristics is
as plotted in Fig. 4. The device performance parameters are summarized in Table2.
V. CONCLUS IONS
Using the figure of merit fτ × BVCEO product (Johnson’s limit), the performance of the bipolar
transistor in this work is compared with previously published results in Fig. 5. Furthermore,
the process complexity and device performance are summarized in Table 3. The fabricated BJT
delivers comparable performance with the references cited, while only using single poly,
implanted base and with no trench isolation. Therefore, this bipolar transistor is easier to
integrate and is truly compatible with standard CMOS technology.
Table 3: Comparison with previously published BiCMOS technology.
This work Suzuki et al. K. Chai et al. Iwai et al.  Deferm et al.
Year 2001 2000 2000 1999 1998
Conf. or Journal BCTM BCTM IEDM BCTM
Organization U of Toronto NEC Motorola Toshiba IMEC
Bipolar Structure Single Poly Single Poly Single Poly Double Poly Double Poly
Base Implant base Epi-base Implant base Epi-base Epi-base
Isolation None Trench ISO Trench ISO Trench ISO None
SE (µm ) 0.4X1.0 0.24X16.0 0.4X0.8 0.3X1.0 0.35X6.0
Peak fτ (GHz) 16 28 24 20 24
BVCEO (V) 6.4 5.5 6.3 10 4.3
The authors thank AKM, Micronet and NSERC for financial support, and to AKM for
fabricating the devices.
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1. n+ buried layer
2. p-type epitaxy
3. deep n-well
4. p-base implant 1.6E+10
Gate poly deposition
5. poly emitter
n & p LDD Implant 4.0E+09
NMOS n+ Diffusion
1.E-06 1.E-05 1.E-04 1.E-03
PMOS p+ Diffusion
Fig. 4. Cut-off frequency (fτ) as a function of collector
current for effective emitter size of 0.4×1.0
Passivation & pad mask µm2.
Fig. 1. Standard CMOS process flow with additional Table 2: Bipolar Transistor Parameter Summary
steps for RF BJT implementation.
B E B C Emitter Size 0.4µm × 1.0µm
BVCEO 6.4 V
SiO 2 SiO 2 SiO 2
p+ n+ p+ n+ BVCES 15.8 V
deep n- Cje 1.50 fF
CCB Cjc 1.23 fF
Cjs 1.20 fF
n+ buried peak fτ 16.0 GHz
CCS p- p-
Fig. 2. Cross-sectional view of the RF BJT structure. 10
8 Johnson’s limit
p+ Base 4
Implanted Base Base
0 10 20 30 40 50 60
Peak fτ (GHz)
Fig. 3. SEM micrograph of the base-emitter region of Fig. 5. BVCEO vs. fτ trade off for high-speed bipolar
the fabricated BJT. transistor. The solid line corresponds to
Johnson’s limit of 320 GHz⋅V .