Architecture of a Programmable Pattern Generator

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					               NASA Langley Research Center




Architecture of a Programmable Pattern
           Generator (PATGEN)
      ASIC for Space Applications

  W. C. Wilson1, R. F. Hodson2, and C. D. Armstrong1

            1NASA   Langley Research Center
            2Christopher Newport University
                 NASA Langley Research Center


               Introduction to PATGEN
                       • The Pattern Generator (PATGEN) avionics project
                         is developing a custom Application Specific
                         Integrated Circuit (ASIC) for detector clocking.

                       • The PATGEN ASIC is a Focal Plane Array (FPA)
                         or Charge Coupled Device (CCD) clock and control
                         signal generation device for space applications.

                       • PATGEN will have 8 outputs, but is is extendable in
                         both the number of output channels and the size of
                         the patterns.

                       • The chip is a digital pattern generation chip with
                         two levels of looping.
                       • Patterns can be either single shot or continuous.

                       • PATGEN is implemented in Silicon On Insulator
                         (SOI) technology for radiation tolerance.

W. C. Wilson                  1                                       E6A
                              NASA Langley Research Center

                            Graphical Entry tool
                                                                Configuration Memory



                                                                 PROM
• Custom ASIC Design
• Radiation Hard
    – 100K rads TID
    – Latchup Immune
• 8 Channels                                           PATGEN
• Up to 256 Gbit Pattern length.
• 2 Levels of 16K looping.
• PATGEN is extendible
    – The number of output channels.
    – The size of the patterns.
                                                              CCD or FPA
                                                                   Or
                                                             Any digital logic
                            Clock or Control Signals               CCD Array
  W. C. Wilson                                 2                                       E6A
                       NASA Langley Research Center

                      Project Partners




                NASA Langley Research Center
                Christopher Newport University




W. C. Wilson
               LaRC                 3
                                                      CNU   E6A
                           NASA Langley Research Center

                 Extendibility of PATGEN
                                                                        Analog Signals
2D Array of PATGEN Chips                             CCD or FPA
- Increase the number of Channels
- Increase the Pattern Length
- Arrays boot from a single PROM                      Clocking and
                                                      Control Signals




                                                                                 Increase the Pattern Length
                                               PATGEN              PATGEN



                                    PROM       PATGEN              PATGEN


                       Configuration Data      Increase the number of Channels

 W. C. Wilson                              4                                         E6A
                             NASA Langley Research Center

                               Technology
      Peregrine Semiconductor 0.5u UTSi CMOS Transistors
                       P-channel FET            N-channel FET



                                                                    Silicon Dioxide

                                                  Insulating Sapphire Substrate
• Radiation Hardened:
    – Single event upsets (SEU) less than 10-8 errors/bit-day
    – Single Event Latchup (SEL) immunity
    – Total dose hardness to 100 Krads
• Low power (30% lower than Bulk CMOS)
• Higher performance (due to less parasitics)
• Low Cost (Available through MOSIS in small quantities)
W. C. Wilson                               5                                E6A
                                       NASA Langley Research Center



                    PATGEN Looping Structure

                                         Continuous or Single Fire

               < 16K Iterations                                               < 16K Iterations

 < 16K          < 16K         < 16K     < 16K                    < 16K        < 16K       < 16K       < 16K

   Fn            Fn            Fn          Fn                      Fn          Fn          Fn          Fn


 < 64 bits     < 64 bits   < 64 bits    < 64 bits                < 64 bits   < 64 bits   < 64 bits   < 64 bits

                 < 4 fields                                                       < 4 fields

                                                    < 4 Groups




W. C. Wilson                                            6                                                E6A
                       NASA Langley Research Center

               PATGEN Looping Structure

    • The PATGEN device has eight channels with eight fields
      per channel.

    • The device also implements two levels of looping.

    • The lowest level of looping is implemented as 16K
      iterations on each of eight 64-bit fields.

    • The sequencer has four groups in which each group is
      made up of a sequence of up to four fields.

    • The second level of looping is 16K iterations on each
      group sequence.

W. C. Wilson                        7                          E6A
                      NASA Langley Research Center

               PATGEN Top Level
                              Chip Controller



               Bit Error                             Parity



                  Channel 8         .           Channel 1



                  Channel 7         .           Channel 2



                  Channel 6         .           Channel 3



                  Channel 5         .           Channel 4



W. C. Wilson                        8                         E6A
                       NASA Langley Research Center

                   PATGEN Top Level
    The PATGEN chip consists of the following:
    • Chip controller.
       – State Machine to control the modes of operation.

    • Eight identical Channels.
       – Each channel is made of 8 fields of 64 bits each.

    • The Parity block.
       – Used for Parity and Built In Self Test (BIST)

    • Bit Error block.
       – Used for SEU detection.
W. C. Wilson                        9                        E6A
                                 NASA Langley Research Center

               PATGEN Channel block diagram
                       Field
                       Length                          Field Mux
                       Control                         Select Lines
                                            Field #1
                  Field Enables
                                            Field #2

                  Field Select              Field #3
                                                                      Pattern
                                            Field #4         Mux      Output
                     Sequencer
                                                              &
                                    .       Field #5         OE

                                            Field #6

                      Channel               Field #7
                     Controller
                                            Field #8


W. C. Wilson                                  10                                E6A
                             NASA Langley Research Center

               PATGEN Channel block diagram
    The PATGEN channel block is comprised of:
    • The channel controller block.
         – State Machine, controls modes of operations.

    • The multiplexor and output enable block.
         – Provides Tri-state (High Impedance) and output selection.

    • The field length control block.
         – Allows each field to vary in length from 1 to 64 bits.

    • Eight identical field blocks.
         – 64 bit variable length cyclic shift registers.

    • The sequencer block.
         – Sequences the fields to make up patterns.
W. C. Wilson                              11                           E6A
                                           NASA Langley Research Center



                   PATGEN Variable Length Cyclic
                         Shift Register

                                                    SS

   Feedbk          DFF      Feedbk         DFF                 Feedbk         DFF      Feedbk         DFF
            B                        B                                  B                       B
DataIn             D                       D                                  D                       D         Data Out
            A          Q             A         Q    SS                  A         Q             A         Q
             Sel       QB            Sel       QB                       Sel                     Sel
                                                                                  QB                      QB

      MuxSel 0               MuxSel 1                           MuxSel 62               MuxSel 63
CLK
                                                     SS




   W. C. Wilson                                           12                                                   E6A
                            NASA Langley Research Center

                 PATGEN Variable Length
                   Cyclic Shift Register

  • The shift register is built of flip-flops and multiplexors.

  • Multiplexors allow for variable length from 1 to 64 bits.

  • Shift register allows for looping.

  • Patterns shifted out are also shifted back in.
       – Eliminates need for separate data storage for the patterns.




W. C. Wilson                             13                            E6A
                               NASA Langley Research Center

                     Mux & OE Block Diagram
  F1
  F2
  F3           Mux
               4:1
  F4


                         Mux                                           Channel Out
                         2:1
  F5
  F6
               Mux
  F7
               4:1
  F8

               2
  FSel 3             1
  OE                                                      D   Q

  CLK                                                         QB   Mask Register

W. C. Wilson                                14                                     E6A
                               NASA Langley Research Center

                  Mux & OE Block Diagram

• Mux&OE block controls and selects the output from the eight fields that make
  up a channel.

• The PATGEN has two output modes, binary and tertiary mode.

• In Binary mode, outputs are either high or low.
    – The mask bit is cleared.
    – The multiplexor uses outputs from the sequencer block to select from one of the eight
      fields to be output.

• In Tertiary mode, outputs can be high, low or tri-state (high impedance state).
    – The mask bit is set
    – The four upper fields are used to set the pattern output to a high or low.
    – The four lower fields are used as masks, for when the pattern should be tri-stated.


 W. C. Wilson                               15                                         E6A
                         NASA Langley Research Center

               Sequencer Block diagram
                                                    Group
                                                    Counter
                 Length Count Seq. Count
                  4 bit Cyclic Shift Register   3
                  4 bit Cyclic Shift Register
                  4 bit Cyclic Shift Register

                 Length Count Seq. Count
                  4 bit Cyclic Shift Register   3
                  4 bit Cyclic Shift Register
                  4 bit Cyclic Shift Register       Mux 3
                                                    4(3:1)
                 Length Count Seq. Count
                  4 bit Cyclic Shift Register   3
                  4 bit Cyclic Shift Register
                  4 bit Cyclic Shift Register

                 Length Count Seq. Count
                  4 bit Cyclic Shift Register   3
                  4 bit Cyclic Shift Register
                  4 bit Cyclic Shift Register

W. C. Wilson                              16                  E6A
                               NASA Langley Research Center

                   Sequencer Block diagram
The sequencer block, is comprised of four groups of sequencers.

• The groups are made up of small sequencers that each sequence up to four
  fields.
     – Each group has its own loop counter which allows up to 16K iterations.
     – Each group is made up of a set of three four-bit cyclic shift registers.

• The output of the shift registers selects and enables the active fields, and it
  drives the select lines of the output multiplexor.

• The group counter controls the number of groups up to four, which can be
  chained together.

• Allows up to 16 fields (four groups of four fields) to be sequenced.


 W. C. Wilson                               17                                      E6A
                           NASA Langley Research Center

                       Conclusions/Status
 • The PATGEN chip is a pattern generation ASIC.
      – PATGEN can be placed in arrays to extend the number of outputs and
        length of the patterns.
      – Within the chip, there are two levels of looping, each with 16K iterations.
      – The patterns are made up of eight 64-bit fields.
      – Patterns can be continuous or single shot.

 • Pattern lengths vary up to 256 Gbits, depending the amount of
   looping.
 • The PATGEN programming software, a graphical entry tool for
   developing patterns, has been written, tested and documented.
 • The project has fabricated a prototype PATGEN device
      – Fabricated using Peregrine’s 0.5u SOS process through MOSIS.
      – The prototype has two channels and the fields are 32 bits wide.
      – Device testing will begin in October of 2000.
W. C. Wilson                            18                                    E6A