Leakage Issues in IC Design Part 3

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					          ICCAD „03




Leakage Issues in IC Design: Part 3



           Anirudh Devgan

           devgan@us.ibm.com
           IBM Research Austin
            ICCAD „03


Outline


     Part1: Siva Narendra (Intel Corporation)
        – Device physics, process technology, leakage fundamentals
     Part 2: David Blaauw (University of Michigan)
        – MTCMOS, Dual-Vt, estimation/optimization techniques for dual-Vt
     Part3: Anirudh Devgan (IBM Corporation)
        – Process & Environmental variations, ABB, Vdd control
     Part4: Farid Najm (University of Toronto)
        – State dependence, sleep states, memory/cache circuits and architectures




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Leakage…
                                                            International Technology Roadmap
       Leakage power is becoming a                1.E+04
        significant portion of total power.                     NTRS '97
                                                                ITRS '99
         – Currently managed to 15-20% in                       ITRS '01
                                                   1.E+03
           current IBM designs.
         – Expected to increase dramatically in
                                                   1.E+02
           future designs & technologies.
         – In some cases (11S), predicted to
           more than 50% of total power.           1.E+01

       Leakage is the problem
         – Emerging as the critical challenge in   1.E+00
                                                         1990      1995     2000    2005       2010         2015   2020
           VLSI Design.
       Leakage depends super linearly with




                                                                                            Sub-Threshold
        Process variations, Temperature,
        Power supply voltage


                                                                           Gate




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Variability: Leakage and Timing




                                                  Source: Intel, DAC 2003


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Leakage & Thermal Variations
                                   Temperature varies with-in the chip

            F I
            UU
            P S                                  SF
                                                 IU U
                                                   P

              I
              DU
                  F L
                  I
                  B
                  X
                   US
                   U
                     U        FFXXUU         UU
                                             S F
                                             L I
                                                      X
                                                      B
                                                      U
                                                         I
                                                         DU




                             2
                             L            L
                                          2           2
                                                      L
    L3Directoy/Cntrol


                              Chip Floorplan                                         Chip Thermal Profile


                             Power 4 Server Chip: 2 CPU on a chip
                                   The CPUs can be much hotter than the caches




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Power Supply Variations
                                       Voltage
                                                    Vcrit

     Package          Grid                       time
                 Rg
     +    L           Rd
    VDD
                      Cd
                 Decap               Load
                           IDD
                                      Load
                                      Waveform
                                 m
                                      tp     time




    VDD Noise  m tp Rg + mL – m R2g Cd (1 – e-t /t)                        p
                                                                                         ~Same
                       DC        Package                    Decap

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Power Delivery
                                                               C4 “balls”
Connection
to package




                    Connection to circuits


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Supply Voltage & Temperature
           Leakage dependence on Vdd                           Leakage significantly affected by
                – Variation in both gate and sub-                temperature.
                  threshold leakage.                            With-in die temperature variations
           Need to combine Power supply                         need to be modeled.
            analysis with Leakage.

     3                                                            0.1
                     Gate         Subthreshold   Sum             0.09
    2.5
                                                                 0.08

                                                                 0.07
     2
                                                                 0.06

    1.5                                                          0.05

                                                                 0.04
     1                                                                                                 M ean Leakage
                                                                 0.03
                                                                                                       M ax Leakage
                                                                 0.02
    0.5                                                                                                M in Leakage
                                                                 0.01

     0                                                             0    Temperature (deg C)
          0.6      0.7      0.8      0.9     1   1.1   1.2               55         70         85        100        115




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     Power integrity & Package

     Package design becoming increasingly complicated
     Large number of power/ground layers in current packages
     Significant Power supply variations caused by the package



                         capacitor chip   capacitor
          Solder balls
                                                         chip carrier




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 Power Supply Variations – Package Effects


      VDD              C4s
      GND
  Planes


                       Balls



 Power IR Drop by the package
      – Is usually non- uniform across the various
        C4
      – Can be difficult to predict and analyze




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Is Variability Real?




                                                         S. Nassif DAC 2003

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 Variability Time Scales
                                                                                      S. Nassif DAC 2003


10-10 – 10-8           10-7 – 10-5             10-4 – 10-2                        105 – 107




Signal Coupling            SOI History         Temperature                         Process Line
                           VDD/Package Noise


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Variability Distribution
     Physical:
      Die to die variation
        –   Imposed upon the design (constant regardless of design).
        –   Well modeled via worst-case files.
      Within-die variation
        –   Co-generated between design and process (depends on details of
            the design).
        –   Example: nested vs. isolated poly-silicon DL.

     Environmental:
      Only makes sense within-die.




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Variability vs. Uncertainty

      Variability: known quantitative relationship to a source
       (readily modeled and simulated).
        –   Designer has option to null out impact.
        –   Example: power grid noise.
      Uncertainty: sources unknown, or model too difficult/costly to
       generate or simulate.
        –   Usually treated by some type of worst-case analysis.
        –   Example: DL within die variation.
      Lack of modeling resources often transforms variability to
       uncertainty.
        –   Example: nearest neighbor noise coupling.




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Within-Die Variations?
      Fundamentally different from die-to-die.
      Environmental components:
        – VDD & Temperature variations are natural byproducts of power
          distribution analysis.
        – Power distribution analysis unavoidable .
      Physical components:
        – VT and DL variations across the die.
        – Lot, Wafer, and Die distributions.
        – Layout (design) dependent.




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Spatial Variability

      Facility, Line, Lot, Wafer &
       Die components.
      Semi-periodic across wafer.




                                             Parameter
                                                                Die 1             Die 2
      Wafer level and above are                                                                wafer
       not of interest to a designer.
      Designer does not get to choose
       where on a wafer his design goes!                                                         Position




                                                                             S. Nassif DAC 2003

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Sources of Within-Die Variations
      Poly line-width (LEFF) variation comes from:
        –   Mask, Exposure and Etch variations
        –   Essentially identical to modeling required for OPC.



                                Layout (designer view)

                                   Mask & OPC bias


                                Lithography bias
                                                Resist
                                                            Poly
                                  Etch bias                                          Silicon


                                                                                S. Nassif DAC 2003

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LEFF variations via OPC




                                                              S. Nassif DAC 2003

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Sources of Within-Die Variations
      Vertical variations are caused by chemical-mechanical
       planarization (CMP) process.
                                                                       polishes
                                                                        faster




                              C1                                             C2


                                                                       S. Nassif DAC 2003

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Leakage Modeling and Analysis

                                      Input pattern vector
     Operating Environment            (state)
     (Temperature, VDD, …)




                                 Sub-Threshold
                       Gate


                                                 Process Variations
         Topology
                                                 (DL, VT, TOX, …)

         All effects need to be accurately modeled
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      Leakage Requirements

     Need to include environmental and process variations

       Channel length         Standby leakage
       Supply voltage
       Temperature          Active & burn-in leakage




                                                               S. Narendra ICCAD 2002

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Process Dependence
     0.25
                Leakage            M in Leakage
                 (mA)              M ean Leakage         ~10X                          IDDQ for typical chip
      0.2
                                   M ax Leakage


     0.15


      0.1


     0.05                  ~10%
                 Process Variation Parameter (NRN)
       0
                   1          2          3           4          5




                Leakage varies exponentially with process variations.
                   – 10X variation due to process vs. 10% variations due to different patterns.
                   – Reason: sub-threshold current varies exponentially with process variations




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Leakage & Process Variations
      Process parameters (Leff, Vth) have great influence
      Generate leakage performance statistics
         – Practical bounds for a given confidence level can be driven
         Leff distribution




                                                 +                            +
                              Global variations           Within-chip                Within-chip
                                                          (Deterministic)            (Random)




                                         0.99                                       Cumulative
                                                                                    Distribution for
                                         0.01                                       Leakage
                                                                            Total Leakage
                                           L-3s = L0.01       L3s = L0.99
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Process Variations
            Leakage is exponentially dependent on process variations




                                    L  Lmean
                               (
                   I  I oe
                                                )
                                       




             Normal distribution of L leads to a LogNormal distribution of leakage.




                                                                                        S. Narendra ICCAD 2002

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Process Variations: ACLV
                                                With-in Chip:
                                                ACLV




                                       Chip
                                       Mean
               No of Chips




                                       Leff




                             -4   -3    -2     -1  0    1  2               3       4
                                              Global Sigma
                                             Chip to Chip Variation
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     Leakage modeling
     Prior techniques
      Lower bound:
      Assumes all devices in the die are nominal L
                    wp                        wn o
      I leak -l            I   o
                                p               In
                     kp                       kn
      Upper bound:
      Assumes all devices in the die are minimum L
                       wp           3s             wn 3s
       I leak -u               I   off  p          I off n
                       kp                          kn                             S. Narendra ICCAD 2002

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Process Variations: ACLV
        If Length distribution on the chip is normal, the probability of given L is

                                                                           ( l  Lmean) 2
                                                            1          
                                         p (l )                  e            2s 2
                                                          s 2


             Leakage with ACLV can be computed as
                                              l  Lmean                        L max          ( l  Lmean) 2       ( l  Lmean)
                                         (               )       Io                                          
                    I leak  E ( I o e           
                                                              )
                                                                 s 2             e
                                                                                L min
                                                                                                   2s 2
                                                                                                               e                 dl


              which simplifies to
                                                                 s2
                                     I leak  I o e              22


            ACLV has exponential effect on total chip leakage

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     Applications…


                k I leak                 A macroscopic standard
     s   2 ln                          deviation (s) representing
               w I   o
                                           parameter variation in a chip


                             s p2                  s n2
               I o wp
                 p           2 p 2
                                            o
                                          I n wn 2n2
 I leak w              e                      e                                 Leakage
                kp                         kn                                      estimation

           Depends on parameters that can be estimated
                                                                        S. Narendra ICCAD 2002

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     Measurement results
     0.18 um 32-bit microprocessors (n=960)


                        Number of samples
                                            500
                                                                     m: 0.65
                                            400          Ileak-u     s: 0.27

                                            300                         m: 1.04
                                                            Ileak-w s: 0.3
                                            200
                                            100                      Ileak-l      m: 6.5
                                                                                  s: 3.8
                                             0
                                                  0.1   1            10            100
                                                   Ratio of measured to
                                                    calculated leakage

        50% of the samples within ±20% of the measured leakage
      Compared 11% and 0.2% of the samples using other techniques

                                                                                          S. Narendra ICCAD 2002

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Characterizing the variation
        Variations in channel length occur at both the intra-die (within-die) level and
         inter-die (die-to-die) level


                        Ltotal ,i  Lnominal  DLinter  DLintra,i




                         DLinter
                                                     DLintra
                                                                                 R. Rao,et al. ISLPED 2003

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Empirical Model
        Using the following mathematical model


             I  q1eq L  2   d    q3 L2
                                        d     hL 

                1                        q 
             L      q2  q2  4q3 ln  1    g I 
                2q 
                               2
                                           
                3                       I 

        Eliminate Vth as an intermediate variable and use general form of SPICE model
         to perform empirical fitting on channel length
        Properties of this equation:
          – Preserves exponential dependency of I on L
          – Is easily invertible (simple quadratic equation formula)
          – Yields closed-form expressions for the PDF of I
          – Accurately fits over a wide range of values of L for NMOS/PMOS and transistor stacks




                                                                                   R. Rao,et al. ISLPED 2003


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Goodness of fit
     NMOS in 0.18µm: Vgs=0, Vds=Vdd and ±10% variation in Ld

         Comparison of simulation data            Comparison of experimental PDF
         with analytical expression               with PDF obtained analytically

                        Simulation
                        Analytical                                              Simulation
                        BSIM3 Fit                                               Analytical




                                                                      R. Rao,et al. ISLPED 2003

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Accounting for inter/intra-die variations                                          R. Rao,et al. ISLPED 2003

    Ltotal ,i  Lnominal  DLinter  DLintra,i      s L,total  s L,inter  s L,intra
                                                      2           2           2



     We accommodate variation across both levels in our empirical
      model
         – Assume sL,total=15%. First determine the parameters for sL,inter=0% and
           sL,intra=15% of nominal
         – Enumerate all inter-die variation points (Ex: 1%, 2% etc.,)
         – For each point, shift the mean by sL,inter and obtain the distribution of currents
           around that average point using sL,intra
         – Perform weighted summation across the range of sL,inter

                                                               Weighted
                                                               Summation




                                                  Leakage Issues in IC Design: Trends, Estimation and Avoidance
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Leakage PDF for different intra/inter-die variation




                                                             R. Rao,et al. ISLPED 2003

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Leakage Modeling and Analysis

                                      Input pattern vector
     Operating Environment            (state)
     (Temperature, VDD, …)




                                 Sub-Threshold
                       Gate


                                                 Process Variations
         Topology
                                                 (DL, VT, TOX, …)

         All effects need to be accurately modeled
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Power with on-chip environmental variations

              Leakage                  Dynamic
               power                    power
                (P0)                    (PD0)
                    Y
             Stop        Converge ?
                            N

              Thermal           Voltage drop
               profile            contour


           Leakage Model        Dynamic power
        Pleak= P0f(dVdd, dT)    model ~ dVdd2


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Thermal Profile Computation
        Full chip thermal model
          – Thermal system modeled is this paper is assumed to be static (i.e. not time-varying)
          – Dynamic, time varying model can also be used if desired


                                          Package
                       C4
                                           Metal +
                                            ILD
                                              Si

                                            SiO2


                                          Silicon
                                         Substrate




             Heat sinks


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     Thermal Equations

      Steady-state heat conduction equation:


              k T ( x, y, z )  p( x, y, z )  0
                      2

       where p is the power density of the heat sources, k is the thermal conductivity




      Boundary conditions
         – Isothermal (Dirichlet): T = fi(x,y,z)
         – insulated (Neumann): ∂T/ ∂ni = 0
         – Convective (Robin): ki ∂T/ ∂ni=hi(T – Ta)




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Thermal Model
                               Tx,y,z+1
                                          Tx,y+1,z


      Tx-1,y,z                 Tx,y,z         Tx+1,y,z              Thermal network

               Tx,y-1,z
                               Tx,y,z-1



          Tx1, y , z  2Tx , y , z Tx1, y , z       Tx , y1, z  2Tx , y , z Tx , y 1, z       Tx , y , z 1  2Tx , y , z Tx , y , z 1
     k(                   dx 2
                                                                      dy 2
                                                                                                                      dz 2
                                                                                                                                                  )   dxdydz
                                                                                                                                                          p




     Model the circuit as a linear circuit



                     Ri                   dx
                                          kdydz                                                  Rb                  1
                                                                                                                    hdydz



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Thermal Model

      Analogy between thermal and electrical circuits:
               Thermal                                Electrical
            T : Temperature (K)          ==             V
            Rh: Thermal res (K/W)        ==              R
            Q : Heat flow (W)            ==              I



     Thermal System can be modeled as linear circuit
                                  GV=I



      However, thermal modeling of a typical chip leads to millions of nodes
         – Need to use specialized linear solvers




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Circuit Analysis for Thermal/VDD circuits

      General equation: Gx + Cx’ = B(t)
         –   G           conductance matrix.
         –   Ccapacitance matrix.
         –   x, x’       nodes voltages & KVL currents, time derivative.
         –   B(t)        time dependent current sources.

      Analysis using SPICE-like simulators is not practical.
         –   Dimension of x ~ 105 to 107.
         –   Standard circuit simulators cannot make use of any special properties of the
             analysis.




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Analysis Acceleration

     Make use of the linearity.
      BE discretization: (G+C/h)x(t+h) = B(t)+(C/h)x(t).
      System Solution: x(t+h) = (B(t)+(C/h)x(t))(G+C/h)1.
      The matrix (G+C/h) is independent of time \ only needs to be inverted once.

     Avoid data explosion.
      One layout “polygon” translates to many resistors.
      Retain geometrical description and leverage to reduce translation overhead.

     Specialized Linear Solvers.
      Algebraic multi-grid (AMG) solvers




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Multi-Grid Methods
     Basic idea:
      Reduce original grid wh to a coarser grid w2h.
      Map problem from original to coarser grid.
      Solve problem at coarse grid (iterative solver).
      Map solution back to fine grid and refine.

     Systems:
      Fine: Ah xh = bh
      Coarse:        A2h x2h = b2h
                                         Fine                             Coarse




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Leakage Variation


     Chip      Leakage        Vdd (V)                T (°C)                 Change in
                  (No                                                       Leakage
              variations)                                                      with
                  (W)                                                       variations
                                                                               (W)
      1          9.60       1.016-1.196 80.8 – 110.3                         -1.850


      2          1.12        1.159-1.2          75.5 – 89.1                     -0.136




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Thermal & Power Grid Solver


     Matrix Size    Analysis         Runtime                   Mem (GB)
                                      (sec)
        170k        Thermal           82.13                          0.45

        270k        Thermal           139.17                         0.61

        630k       Power Grid          88.39                         0.46

       1.74M       Power Grid         293.58                          1.3

       2.73M       Power Grid         438.10                          2.1




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Leakage Modeling

      Leakage various super linearly with temperature and power supply voltage
         –However, on chip variations of temperature and voltage are limited
         –Leakage as a function of temperature and voltage is modeled as second order




          I (DV , DT )  I (0,0)[1  a1DT  a2 DT 2
                                        b1DV  b2 DV  c1DTDV ] 2




        Gate and subthreshold leakage is modeled separately




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                                                Leakage Issues in IC Design: Trends, Estimation and Avoidance
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Leakage Modeling




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                   Leakage Issues in IC Design: Trends, Estimation and Avoidance
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Results: Thermal profile

          Thermal map of 9mm x 9mm ASIC chip




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                                Leakage Issues in IC Design: Trends, Estimation and Avoidance
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Results: VDD Profile

                       VDD profile




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                                Leakage Issues in IC Design: Trends, Estimation and Avoidance
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Results: Leakage w/ VDD & Temp Variations


        Leakage considering environmental variations
          –   Accurate leakage model of actual VDD and temperature profile
          –   For this example, leakage is lower by 10%




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Comparison to Fixed Drop Analysis

      Need to accurately captures the on-chip locality of power supply
       and temperature and their influence on leakage
      Reduce the optimism of the “fixeddrop” method



             Chip 1    Vdd (V)     T (°C)           Leakag              Change in
                                                      e                  Leakage
                                                     (W)                   (W)
              OCV      1.016-      80.8 -              7.75                  -1.85
                       1.196       110.3
             Fixed      1.08        85                 5.31                  -4.29
             Drop



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     Variable Threshold CMOS (VTCMOS)
        Body effect to change device Vt
        Standby leakage reduction with maximum reverse bias
        Triple well structure



         VBBP    VDD                 VSS        VBBN
                                                                  VDD

                                                                                VBBP

                 p+        p+   n+         n+
                                                                                VBBN
               N-well                 P-well
                                                                   VSS
          N-isolation

                                                              Body Effect:
       P-sub
                                                                                 
                                                                Vt  Vt0  γ 2φB  VBB  2φB                       
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VTCMOS


        Variable Threshold CMOS (from T. Kuroda, ISSCC, 1996)
        In active mode:
              – Zero or slightly forward body bias
                for high speed
        In standby mode:
              – Deep reverse body bias for low
                leakage
        Triple well technology required




     Kaushik Roy, ECE, Purdue University


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     VTCMOS Example

                               VTCMOS principle applied to 4-mm2
                                DCT core processor
                               SSB increases Vt (more reverse
                                bias)
                               SCI decreases Vt (Standby -> Sleep)
                               Leakage reduction
                                 0.1mA active -> 10nA sleep (2.8v DVBB)
                                 4 orders of magnitude
                               Dynamically tunes Vt (by matching
                                leakage current monitor) to
                                minimize Vt variation




                         T. Kuroda, et al, “A 0.9V, 150Mhz, 10mW, 4mm2, 2-DCT Core
                         Processor with Variable Vt Scheme, “ JSSC Nov. 1996

                                                            J Kao ICCAD 2002

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     VTCMOS Pros/Cons
       PROS:
        Significant standby leakage reduction
        Memory elements retain state
        No transistor sizing/ partitioning required
        Dynamically tunable Vt during runtime

       CONS:
        Requires expensive triple well process
        Body factor decreases with scaling




                                                                              J Kao ICCAD 2002

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     DVS vs. DVTS




                   TSMC 250 nm                              BPTM 70nm
               ( Vdd=2.5V, Vth=0.45V )                 ( Vdd=0.9V, Vth=0.15V )
Kaushik Roy, ECE, Purdue University

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     Speed Adaptive Vt CMOS


                           Dynamically tune Vt so that critical path
                            speed matched clock period
                           Reduces chip-to-chip parameter variations
                           Reverse bias:
                             Operate only as fast as necessary (reduces excess
                               active leakage)
                           Forward bias:
                             Speeds up slow chips
                           Standby leakage with maximum reverse bias
                           Also known as Adaptive Body Biasing (ABB)




                            M. Miyazaki, et al, “A 1.2-GIPS/W uProc Using Speed-
                            Adapative Vt CMOS with Forward Bias,” JSSC Feb
                            2002.
                                                              J Kao ICCAD 2002

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     Adaptive Supply & Body Bias (ASB)
                    Dynamically tune both VDD & Vt as operating conditions change
                    Trade-off between dynamic power (VDD knob), leakage power (Vt)
                    Minimize total ACTIVE power consumption
                      (higher active leakage current at expense of lowering dynamic power)




                             Power vs. VDD (implicit Vt) for fixed frequency

                     0.3
     Power [Watts]




                                                            Minimum point where
                                                            slope(leak) = - slope(dyn)
                     0.2                                                                             M. Miyazaki, et al, “A 175mV Multiply-
                                             Ptotal                                                  Accumulate Unit using an Adaptive
                                                                                                     Supply Voltage and Body Bias (ASB)
                                 Pleakage                                                            Architecture,” ISSCC February 2002.
                     0.1
                                                                          Pdynamic

                      0
                           0.1         0.3            0.5           0.7           0.9
                                                  VDD [Volts]
                                                                                                         J Kao ICCAD 2002

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     Optimal VDD/VT Selection
                     Optimal VDD & Vt target changes with operating conditions
                       –      e.g. Varying Workload
                     Low frequencies high Vt more optimal
                       –      reduce leakage at expense of increased dynamic
                     High Frequencies low VDD more optimal
                       –      reduce dynamic at expense of increased leakage


                                  Vt-VDD Constant Performance Locus
                        1
                      0.9                            100 Mhz
                                           50 Mhz                                                               Minimum Power Point (Vt implicit)
                      0.8                                      150 Mhz                             3
                      0.7
                                                                                                  2.5                                                250 Mhz
         Vt [Volts]




                      0.6                                         200 Mhz
                      0.5




                                                                                  Power [Watts]
                                                                                                   2
                      0.4
                      0.3                                           250 Mhz                       1.5
                      0.2                                                                                                             200 Mhz
                      0.1                                                                          1
                        0                                                                                             150 Mhz
                                                                                                  0.5     100 Mhz
                            0.1      0.6       1.1       1.6        2.1
                                                                                                                                                    50 Mhz
                                               VDD [Volts]                                         0
                                                                                                        0.1         0.6         1.1           1.6        2.1
                                                                                                                                VDD [Volts]


                                                                                                                                         J Kao ICCAD 2002

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       VDD/VT Optimization vs. DVS
                          Dynamic voltage scaling ignores VT influence
                          DVS is sub-optimal over the frequency range




                     0.25                                                                 3
                                                                                         2.5
                         0.2




                                                                         Power [Watts]
     Power [Watts]




                                          DVS (Vt=0.35)                                   2                         DVS (Vt=0.35)
                     0.15                DVS (Vt=0.14)
                                                                                         1.5                        DVS (Vt=0.14)
                         0.1
                                   Optimal VDD/Vt                                         1        Optimal VDD/Vt Scaling
                                   Scaling
                     0.05                                                                0.5

                          0                                                               0
                               0            50            100   150                            0       50     100       150     200   250
                                          Frequency [Mhz]                                                   Frequency [Mhz]




                                                                                                                         J Kao ICCAD 2002

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      ASB Architecture

VDD Controller                   Vt Controller
                                                                           Decouple VDD/ Vt tuning loops
            Variable                                                       ABB (Auto Body Biasing)
                                        ABB Generator                       generator chooses Vt based on
             DC/DC
                                                                            VDD/ Freq/ etc.
                                                                           Simple VDD sweep to search
      VDD                                      VBBN         VBBP            minimum active power point
                                                                           Architecture ensures minimum
                                                                            power for any operating
                                                                            condition

             DSP                             Power
            CORE                             monitor




            M. Miyazaki, J. Kao, A. Chandrakasan, “A 175mV Multiply-Accumulate Unit using an Adaptive Supply
            Voltage and Body Bias (ASB) Architecture,” ISSCC February 2002.
                                                                                                       J Kao ICCAD 2002
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                                                               Leakage Issues in IC Design: Trends, Estimation and Avoidance
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Active Well vs VDD Scaling
          Leakage Power (for 65nm)                             Total Power (for 65nm)




  Reverse Body bias (Active Well) is a more effective leakage minimization technique
   than VDD scaling
  Total Power savings depends on ratio of leakage to total power
      – Vdd scaling reduces dynamic power much more than Active Well



                                                                        B. Chatterjee, et al ISLPED 2003


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                                                  Leakage Issues in IC Design: Trends, Estimation and Avoidance
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Background: Active Well vs VDD Scaling




      VDD scaling
         – Less effective than Active Well to reduce leakage                     B. Chatterjee, et al ISLPED 2003

         – Causes higher degradation in performance
         – More effective in reducing dynamic power
      Active Well
         – More effective in reducing leakage
         – Does not work with SOI
         – Effectiveness reducing in newer technologies but still more effective than VDD scaling till 65nm
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                                                      Leakage Issues in IC Design: Trends, Estimation and Avoidance
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Total Power and VDD Scaling

          Total Power (for 130nm)                       Total Power (for 65nm)




                                                                       B. Chatterjee, et al ISLPED 2003


     VDD scaling is very effective in current technologies to reduce dynamic power
     VDD scaling is more attractive if total power is dominated by dynamic power.




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                                            Leakage Issues in IC Design: Trends, Estimation and Avoidance
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            Vth hopping scheme (Variable Vth)




                                                                         K. Nose, JSSC ‘02
     Kaushik Roy, ECE, Purdue University




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                                           Leakage Issues in IC Design: Trends, Estimation and Avoidance
                    ICCAD „03


     Vth hopping scheme




                                                                       K. Nose, JSSC ‘02
 Kaushik Roy, ECE, Purdue University




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                                       Leakage Issues in IC Design: Trends, Estimation and Avoidance
                       ICCAD „03


The DVTS Scheme

                       Fmax

     Frequency
                                                                                          time
      PMOS            2.7 V
     body bias
                      0.9 V
                            0

  NMOS
           -1.8 V
 body bias

              Vth 0.45 V
                     0.15 V




     Kaushik Roy, ECE, Purdue University



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                                           Leakage Issues in IC Design: Trends, Estimation and Avoidance
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     Implementation – overview

                     error[n] = Fclock[n] – Fvco[n]
     CLK
                                                                               PMOS body bias
           Counter



                      +                                                                                 System
                              +      Feedback Alg.     Charge Pumps            NMOS body bias
                          -
                                  Counter




                                            N       VCO




                                  Schematic of the DVTS system

                                                                  Kaushik Roy, ECE, Purdue University


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                                                     Leakage Issues in IC Design: Trends, Estimation and Avoidance
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     Forward Body-Biasing (50nm)
                                  1.E-03



                                                  Super high Vt + FBB                   3% 17%
                                  8.E-04
           Drain Current (A/um)


                                  6.E-04
                                               Nominal Vt + ZBB
                                  4.E-04
                                                                      Super high Vt
                                                                      + ZBB
                                  2.E-04
                                                                                                    Nominal Vt=270mV
                                  0.E+00                                                            Super high Vt=350mV
                                           0       0.2    0.4   0.6     0.8         1         1.2

                                                         Gate voltage (V)                Kaushik Roy, ECE, Purdue University

 •    Previous techniques: use circuit/arch. to lower leakage
 •    This technique: use dev/ckt/arch opt. to lower leakage
 •    Main idea: high Vt device + forward body-biasing
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                                                                      Leakage Issues in IC Design: Trends, Estimation and Avoidance
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32x32 Forward Body-Biased Subarray
                          M1
                                                                Kaushik Roy, ECE, Purdue University
     0.4V power
      supply
                         M2
      SUBSL
                        M3
                        WL31
              ..




                                   MA MP
                                                        ...




                                                     32
                  ...




                                     MN




                                                                            …
                                            32
                                      ...



                        WL0
              ..




                                                        ...
                          VPWELL




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                                                 Leakage Issues in IC Design: Trends, Estimation and Avoidance
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       Body Transition Delay Hiding
             A[N-1:0]



              SUBSL


              VPNWE
              LL

              WL

                        Standby      active
                        standby
     • Subarray turned on ahead of time using SUBSL
     • Extra time for body-bias transition to complete
                                                Kaushik Roy, ECE, Purdue University

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                                  Leakage Issues in IC Design: Trends, Estimation and Avoidance
               ICCAD „03

        Body Transition Energy Reduction

                                              95% 92% 91% 96%

           accesses to same subarray
                                                                  94% 95%                93%
           Percentage of consecutive   100%                   90%

                                       80%

                                       60%

                                       40%

                                       20%

                                        0%


                                                                                                         SPEC2000


•    32KB L1 inst. cache, SimpleScalar, 500M cycles
•    93% of the accesses hit the same subarray in the next access:
     locality of reference
•    Transition energy wasted only in 7% of accesses
                                                                             Kaushik Roy, ECE, Purdue University

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Bitline Performance Under Iso-Leakage
                                                 0.12
                                                                                 t=138ps
                                                 0.10
                                                                                      t=152ps t=164ps
                      Differential voltage (V)
                                                            SenseAmp
                                                 0.08        activates

                                                 0.06                                                 VBL
                                                                                                      VBLB
                                                 0.04                                          Vdiff

                                                 0.02                                  Conventional
                                                                                       FBSRAM
                                                                                       SBSRAM
                                                 0.00
                                                        0       40       80         120          160          200
                                         Time (ps)
•        SBSRAM delay penalty: 3 transistor stack
•        FBSRAM delay penalty: + diffusion capacitance
•        FBSRAM is 7.3% faster than SBSRAM under iso-leakage
                                                                                          Kaushik Roy, ECE, Purdue University

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                                                                              Leakage Issues in IC Design: Trends, Estimation and Avoidance
             ICCAD „03


Summary
      Leakage is critically dependent on process and environmental variations
      Leakage control through two promising techniques
         – Power supply control
         – Threshold voltage control
      Leakage will be the key design variable in next generation ICs




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                                             Leakage Issues in IC Design: Trends, Estimation and Avoidance