Asynchronous Counters - PowerPoint

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Asynchronous Counters




                        2
      Lecture Overview
• Classifications of Counters
• Definitions
• Asynchronous Counter…
  – J – K Flip Flops
  – D Flip Flops
  – Up Counters
  – Down Counters
  – Truncated Counters
• Design Example
                                3
     Classifications of Counters
Asynchronous Counters
   Only the first flip-flop is clocked by an external
    clock. All subsequent flip-flops are clocked by the
    output of the preceding flip-flop.
   Asynchronous counters are slower than
    synchronous counters because of the delay in
    the transmission of the pulses from flip-flop to
    flip-flop.
   Asynchronous counters are also called ripple-
    counters because of the way the clock pulse
    ripples it way through the flip-flops.
                                                         4
     Classifications of Counters
Synchronous Counters
   All flip-flops are clocked simultaneously by an
    external clock.
   Synchronous counters are faster than
    asynchronous counters because of the
    simultaneous clocking.
   Synchronous counters are an example of state
    machine design because they have a set of
    states and a set of transition rules for moving
    between those states after each clocked event.
                                                      5
States / Modulus / Flip-Flops
 The number of flip-flops determines the count
  limit or number of states.
      (STATES = 2 # of flip flops)

 The number of states used is called the
  MODULUS.

 For example, a Modulus-12 counter would
  count from 0 (0000) to 11 (1011) and requires
  four flip-flops (16 states - 12 used).
                                                  6
1 Bit Asynch-Counter / Modulus 2

                        5V
                        VCC



                          2               Q0
      Clock             ~1PR
              4    1J
                        U1A 1Q       15
              1    1CLK
              16   1K          ~1Q   14

                        ~1CLR
                          3
                                74LS76D

     GND




                                               7
1 Bit Asynch-Counter / Modulus 2
     With Timing Diagram from Logic Analyzer

                                                   XLA1
                                                   1



                         5V
                        VCC



                          2               Q0
     Clock              ~1PR
              4    1J
                        U1A 1Q       15
                                                   F
              1    1CLK                            C Q T
              16   1K          ~1Q   14
     10 Hz              ~1CLR
     5V
                          3
                                               Logic Analyzer
                                74LS76D

    GND




                                                                8
2 Bit Asynch-Counter / Modulus 4

                     5V                                5V
                     VCC                              VCC



                       2               Q0               2               Q1
   Clock             ~1PR                             ~1PR
           4    1J
                     U1A 1Q       15        4    1J
                                                      U2A 1Q       15
           1    1CLK                        1    1CLK
           16   1K          ~1Q   14        16   1K          ~1Q   14
   10 Hz             ~1CLR                            ~1CLR
   5V
                       3                                3
                             74LS76D                          74LS76D

  GND




                                                                             9
2 Bit Asynch-Counter / Modulus 4
          With Timing Diagram from Logic Analyzer
                                                                                         XLA1
                                                                                         1




                            5V                                 5V
                            VCC                               VCC



                              2                Q0               2               Q1
   Clock                    ~1PR                              ~1PR
                  4    1J
                            U1A 1Q       15         4    1J
                                                              U2A 1Q       15            F

                  1                                 1                                    C Q T
                       1CLK                              1CLK
                  16   1K          ~1Q   14         16   1K          ~1Q   14
   1MHz                     ~1CLR                             ~1CLR
   5V
                              3                                 3
                                    74LS76D                           74LS76D

  GND




            MSB
             0 0
               LSB            0 1             1 0 11




    0         1                     0           1                          0         1
    0         0                     1           1                          0         0           10
2 Bit Asynch-Counter / Modulus 4
         With Timing Diagram from Logic Analyzer
                                                                           XLA1
                                                                           1
                                                                                   Tip for using the
                    5V
                    VCC
                                                     5V
                                                    VCC
                                                                                   Logic Analyzer:
                      2               Q0              2               Q1
 Clock              ~1PR                            ~1PR
           4   1J
                    U1A 1Q       15        4   1J
                                                    U2A 1Q       15        F

           1                               1                               C Q T
               1CLK                            1CLK
           16 1K           ~1Q   14        16 1K           ~1Q   14
 1MHz               ~1CLR                           ~1CLR
 5V
                      3
                            74LS76D
                                                      3
                                                            74LS76D                   Double click here
GND                                                                                   to open the analyzer




                                                                                                       11
                                        Leave on internal
      Set this clock

to be at least 10 times faster
than the circuit clock.




                         Click Here to open Clock setup
                                                            12
2 Bit Asynch-Counter / Modulus 4
         With Timing Diagram from Logic Analyzer
                                                                           XLA1
                                                                           1




                    5V                               5V
                    VCC                             VCC



                      2               Q0              2               Q1
 Clock              ~1PR                            ~1PR
           4   1J
                    U1A 1Q       15        4   1J
                                                    U2A 1Q       15        F

           1                               1                               C Q T
               1CLK                            1CLK
           16 1K           ~1Q   14        16 1K           ~1Q   14
 1MHz               ~1CLR                           ~1CLR
 5V
                      3                               3
                            74LS76D                         74LS76D

GND




                                                                                   13
3 Bit Asynch-Counter / Modulus 8

                    5V
                    VCC



                      2               Q0               2               Q1               2               Q2
  Clock             ~1PR                             ~1PR                             ~1PR
          4    1J
                    U1A 1Q       15        4    1J
                                                     U2A 1Q       15        4    1J
                                                                                      U3A 1Q       15
          1    1CLK                        1    1CLK                        1    1CLK
          16   1K          ~1Q   14        16   1K          ~1Q   14        16   1K          ~1Q   14
  1MHz              ~1CLR                            ~1CLR                            ~1CLR
  5V
                      3                                3                                3
                            74LS76D                          74LS76D                          74LS76D

 GND




                                                                                                             14
The Ripple Effect…


 Q0

 Q1

 Q2




                     15
Ripple Effect…The Problem


    Q0

    Q1

    Q2

          3           4



              2   0
                            16
D Flip-Flop… Nothing Special About J-K




                                         17
             Six Examples
1.   Modulus 4 Up Counter with Negative
     Edge Triggered Flip-Flops
2.   Modulus 4 Down Counter with Negative
     Edge Triggered Flip-Flops
3.   Modulus 4 Up Counter with Positive
     Edge Triggered Flip-Flops
4.   Modulus 4 Down Counter with Positive
     Edge Triggered Flip-Flops
5.   Truncated Counter
6.   Counter Design                         18
Up Counter w/ Negative Edge Flip-Flops
Down Counter w/ Negative Edge Flip-Flops
Up Counter w/ Positive Edge Flip-Flops
Down Counter w/ Positive Edge Flip-Flops
Truncating the Count… Modulus 6
Modulus-6 Counter
 Asynchronous Counter Design Steps

1.   Select Type
         Up or Down
         Modules
2.   Select Flip-Flop Type
         J-K or D
         Positive Edge Trigger (PET) or Negative Edge
          Trigger (NET)
3.   Determine Number of Flip-Flops
         (2# Flip-Flop  Modules)

                                                         25
     Asynchronous Counter Design Steps

5.    Design Basic Counters
          Same polarity for down counters: Q  PET or Q  NET
          Opposite polarity for up counters: Q  NET or Q  PET


6.    Design Limits Logic
          Input to logic is count that is one past the end
           of sequence.



                                                              26
                Design Example

1.   Select Type
         Up or Down
         Modules MOD – 14 (0..13)
2.   Select Flip-Flop Type
         J-K or D
         Positive Edge Trigger (PET) or Negative Edge
          Trigger (NET)
3.   Determine Number of Flip-Flops
                                    4 Flip-Flop
         (2# Flip-Flop  Modules) 2             16

                                                         27
                 Design Example

5.   Design Basic Counters                Q  PET or Q  NET
         Same polarity for down counters:
                                         Q  NET or Q  PET
         Opposite polarity for up counters:


6.   Design Limits Logic
         Input to logic is count that is one past the end
          of sequence. Limit 13+1 = 14 (1110)



                                                             28
Design Example…Solution