On-chip Measurements of Standard-Cell Propagation Delay

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					       East-West Design & Test Symposium




On-chip Measurements of Standard-Cell
         Propagation Delay



Sergey Churayev, Bakhyt Matkarimov, Timour Paltashev


         Kazakh-British Technical University


                September 19, 2009
1. Abstract.

We report on implementation of random sampling methodology for on-chip
measurements of the pin-to-pin propagation delay of single standard cells
of core library.
A test chip has been implemented in 0.13μm GL130SB
(130nm Logic Process) technology at Dongbu HiTek, South Korea,
2007-2008, and used to monitor up to picosecond’s timing behavior
of 32 DUT’s of core library.
Observed mismatch between simulated and measured parameters
helps to improve and verify library cell models.

Reference design: S. Maggioni, A. Veggetti, A. Bogliolo, L. Croce, “Random
sampling for on-chip characterization of standard cell propagation delay”, in
Proceedings of the Fourth International Symposium on Quality Electronic
Design, 24-26 March 2003, pp. 41- 45.

Design implemented by M. Alekseyev, S. Churayev, G. Kwon, M. Kim

                                     1 / 27          September 19 2009
1. Abstract.

          Measurements is base of core library development



                                 SOC
                                Design

                                  IP
                             development

                           Foundry business


                           Library design


                     High precision measurement




                                 2 / 27           September 19 2009
1. Abstract.

               Infinite cycle of core library development


                          IP design team




    Core library                                      Test team:
    design team                                     High precision
                                                    measurement


          Quality of design ~ Accuracy of core library model

                                  3 / 27         September 19 2009
1. Abstract.

        Random sampling for timing parameters measurements

Random sampling characterization of cell timing behavior is based on
measurement of cell’s pin signals at random moments of time and
statistical analysis of collected data. Let us denote the signals at the pins of
cell as cell state; obviously we have finite number of cell states.
When we are applying periodic input signal to the cell, in general, we may
observe cell state changes, and the probability to find particular cell at the
given state is proportional to the time, when cell is in this state.
If we collect statistics of cell states at random moments of time we can use it
to create the image of cell timing behavior

Open questions:
• Impact of measurements on target device
• Evaluation of quality of measurements


                                      4 / 27           September 19 2009
1. Abstract.

We implemented on-chip measurement methodology and made a test chip for Dongbu’s STD cells.
In this report, we re-visit the basic concept and give you the test results.


                                   Basic goal of measurement is define
                                    Delay Time in delay chain of cells




                                              Black Box
                                       (Delay line of STD-cell, I/O
          Input under test              block, special IP-core, …              Output under test
                                                   etc)




     Main goals of design and implementation this idea:
1.   Test Automation without high-end test equipment.
2.   Provide highly accurate on chip measurement method.
3.   Easy apply not only for STD cell library but also IP core, I/O, etc …




                                                     5 / 27                  September 19 2009
2. Introduction.
        There are three main methodologies for measurement of propagation delay inside chip:
1.      With using external probes.
2.      With using e-beams to observe interest signal.
3.      With using on-chip special design solution.


 1             Reference            Oscilloscope
                                                               2                           Test board
                 clock            Channel1 Channel2
               generator                                                                       Test
                                                                                               chip
                                        Test board

                                          Test
       Error of                           chip
     measurement                                                   Reference
                                                                                           E-beams
      is too big.                                                    clock
                                                                   generator          transmitter / receiver


 3                         Test board         Reference                                  Oscilloscope
                                                clock                                  Channel1 Channel2
        Optional                              generator
      correlation          Test                                   Price of
     between error         chip                  PC            equipment is
       and price.                                                too high.



                                                      6 / 27               September 19 2009
3. Main idea.
                                               T (period of clock)
              DUT – device                                                                     Trr – rising
               under test         Trr          Thh           Tff          Tll                      time

Ref. clock                                                                                     Thh – 1 to 1
  PAD               input
                                                                                                  time

                                                                                               Tff – falling
                    DUT
                                                                                                   time

                                                                                                 Tll – 0-0
 Output                                                                                            time
  PAD           output


              Stage in                                                                          Decoder
             delay chain     00   01              11         10           00          01         state



              Random                                                                             Depend on
              sample                                                                            counter state
                                                                                                 correspond
                                                                                                 counter will
              Counter                   Here           OR            OR         OR                increment
                                         +1            +1            +1         +1                ours value
             CHIP

                                                 7 / 27                    September 19 2009
4. Schematic realization.

                                               L1(C1)                                                              T(00) = (N(00)*T)/N(all)
    REFCLK                  Input                                                Enable
                                                                                         Counter 1        Out
                                               Fl/Fl       D                     Clock    (rising time)
                                                           E                                                       T(rise) = (N(01)*T)/N(all)
                             Unit                                                Enable
      Key                                                  C                             Counter 2
                            under                                                                         Out
   features
   L1(C1) =                  test                          O                     Clock (1 to 1 time)
    L2(C2)                  (delay                         D                                                       T(11) = (N(11)*T)/N(all)
  (!!!!!!!!!!!!)            chain)                                               Enable
                                                           E                             Counter 3        Out
                                               Fl/Fl
                                                           R                     Clock (falling time)

                           Output            L1(C1)                                                                T(fall) = (N(10)*T)/N(all)
     XORO                                                                        Enable
                                                                                         Counter 4        Out
                                                 0.5                             Clock     (0 to 0 time)
   Standard error = (+/-) ((T(rise) * P) / N(all))
                                                                                                                   T(all)=N00+N01+N10+N11
                                                        High                     Enable
                            Random ring                                                  Counter 5     Out
   Test chip                 oscillator                                          Clock    (total sample)




 Value of Counter 5 must be equal sum of value Counter 1, Counter 2, Counter 3, Counter 4, at the end of measurement process of test chip.
 It equability will be define absent of violation in clock tree.




                                                                   8 / 27                       September 19 2009
5. Waveform.

 IN

OUT

DECODER         01


                          10
                                00
                                      01


                                                10
                                                     00
                                                          01


                                                                     10
                                                                           00
                                                                                01


                                                                                          10
                                                                                               00




                                                                                                               10
                                                                                                    01




                                                                                                                    00
                                                                                                                         01


                                                                                                                                    10
                                                                                                                                         00
                                                                                                                                              01


                                                                                                                                                          10
                                                                                                                                                               00
                     11




                                           11




                                                               11




                                                                                     11




                                                                                                                               11
                                                                                                          11




                                                                                                                                                    11
 STATE

 RND RO

 Counter 1                       00                                                  01                                       02                   03

 Counter 2                                                01                                                   02                   03                   04

 Counter 3           00              01                             02                                         03                                  04

 Counter 4                 00                        01                    02                            03                                   04


After long time of measurement, each                       Phase of RND RO will have random process of behavior all time,
counter will be accumulate value, which                    so each posedge of signal can by apply to any area, as small as
be in proportion for time delay for each                   possible.
stage in delay chain. Based on this
value we can easy calculate realistic
time of delay inside each elements.



                                                                         9 / 27                          September 19 2009
6. Accuracy of measurements

Calculation of delay time
                                                           Counter 1
 in delay chain (only for
 non inverter elements):    T rising =                                                    T/N   (1)
                                          Counter 1 + Counter 2 + Counter 3 + Counter 4

    N – amount of
  elements in delay                                        Counter 2
  chain (*optional)         T high =                                                      T/N   (2)
                                          Counter 1 + Counter 2 + Counter 3 + Counter 4
T – reference period

                                                           Counter3
                            T falling =                                                   T/N   (3)
                                          Counter 1 + Counter 2 + Counter 3 + Counter 4



                                                           Counter4
                            T low =                                                       T/N   (4)
                                          Counter 1 + Counter 2 + Counter 3 + Counter 4



                                             10 / 27               September 19 2009
6. Accuracy of measurements
Calculation of delay time in delay chain (only for inverter elements):


Reference clock in

                               Trr                      Tff
 Out from delay chain
   (200 elements)


                                       Δ Tr                        Δ Tf

                                Tr+1                    Tf+1


Out from delay chain (200
  elements + 1inverter)



  Δ Tr and Δ Tf –
 rising and falling
time repetitively in
     1 element.             Δ Tr = Tr+1 - Trr                 Δ Tf = Tf+1 - Tff


                                              11 / 27             September 19 2009
6. Accuracy of measurements
                      Accuracy estimation and choice period of T:

 Standard                                                                For
deviation for              T rising               T rising             T >> T                  T rising
 1 sample       σX=                     1
                                                                 (5)   rising       σ  X~
                                                                                        =                 (6)
                                T                    T                                              T




  Standard
  deviation                     σX
(average for          σ=                    (7)
 N samples)                         N




   Standard error
 (with combine (1),                 1         T rising                      T rising   T      (8)
                       ~
  (6), (7) formulas   σ     =
                                                   T
                                                             T    =
                                                                                N
      together)                     N


                                                  12 / 27                 September 19 2009
6. Accuracy of measurements

Error calculation for AD2D4 delay chain:           In general, the input time period T does not impact
                                                   the measured propagation delay. In fact, equation (1)
T rising of element         = 100 ns               expresses Trr, as the product between T and the
T (period)                  = 200 ns               ratio Counter1/(Counter1+2+3+4),
N (Total amount of sample) = 4294967295            that is inversely proportional to T. However, the
                                                   value of T does affect the accuracy of the measure.
According formula (3) obtain average standard      But with estimation formula (8) we obtain - choosing
deviation of Trising        = ± 2.1 ps.            a time period T much larger that the propagation
                                                   delay of interest leads to a standard error that grows
                                                   with the square root of T. The best choice for period
Error calculation for NID4 delay chain:            T is the minimum value that guarantees that the
                                                   distance between rising and falling input transitions
T rising of element          = 60 ns               is safely greater than the propagation delays under
T (period)                   = 200 ns              measure.
N (Total amount of sample) = 4294967295
According formula (3) obtain average standard            T1 - bad          T1<T2         T2 - good
deviation of Trising         = ± 1.6 ps.

Error calculation for IVTD4 delay chain:
T rising of element          = 150 ns
T (period)                   = 200 ns
N (Total amount of sample) = 4294967295                Trr1   Tff1                     Trr2   Tff2
According formula (3) obtain average standard
deviation of Trising         = ± 2.64 ps.                 T1<T2, Trr1=Trr2 and Tff1=Tff2 - constant




                                         13 / 27                September 19 2009
7. Key features of implementation.
     There are two main implementation issues that may affect the accuracy of the delay measures
     provided by our approach:
1.   Same condition between input and output point of delay chain.
2.   Same condition between Flip-flop output point and input of decoder.
3.   Matching and synchronization of the S/H circuits (Flip-Flop) used for sampling of signal and
     counters.
4.   Generation of random sampling pulses independent from input waveform Vin.

                Test chip    Module

         REFERENCE                    Input driver             S/H elements   Decoder
           CLK in                                                                       Counters   Mux
                                                     o1
                                                                    Fl/Fl

                                     Unit
       Key features                 under                        L (C) =
      L1(C1) = L2(C2)                test                         L(C)
                                    (delay
                                    chain)
                                                     o2
                                                                    Fl/Fl

             OUT                   Output driver




                                                     14 / 27                  September 19 2009
7. Placement

To reduce possible mismatch in synchronization of F/F circuits,
we applied special constraints in the synthesis and layout design processes.

Main target to be achieved is equal propagation delay from random generator
to F/F elements.

We used a special command script file for synthesis in Synopsys tool, and we
checked synthesis results by Verilog netlist simulations.

Layout of critical elements and wires was done manually.

Finally, we carried out post layout SPICE simulations.




                                     15 / 27             September 19 2009
7. Random generator


     Ring oscillator 1 (17 inverters)


     Ring oscillator 2 (19 inverters)                      +




     Ring oscillator 238 (255 inverters)




     Internal referenc CLK                             RND
                                           FLIP FLOP   CLK
     e generator




                                        16 / 27        September 19 2009
8. Sequence quality estimation of random generator.
                     For quality of RND generator we suggest to use next solution:


       RND RO1                                 Enable
       (on-chip)                   FLIP-                     COUNTER for 1                N1
                                   FLOP
       RND RO2                    element
                                                             COUNTER for 0                N0
       (on-chip)                              CLK
       Or external
        reference
       generator             Pn1 = N1/(N1+N0) ≈ 0.5              Pn0 = N0/(N1+N0) ≈ 0.5

          Probability of N(1,0)
                                                                          “1” much more than “0”
  1
0.75                                                                                      RND problem!

0.5                                                                                       RND OK.


                                                                                           TIME
                                      Time of measurements


                                               17 / 27            September 19 2009
 8. Sequence quality estimation of random generator.
                              Easy estimation of on-chip RND test generation with using Lab View system:

      1. Prepare schematic:
                                                                                  PC LABVIEW
                                                RND out                                 COUNTER
                                                                                                           N1
                                   TEST                                                   for 1
                                                                   FLIP-FLOP
                                   CHIP                             element
                                                                                        COUNTER
                                                                                                           N0
                     External reference                                                   for 0
                                                               CLK
                     generator (10 MHz)

      2. Build graphics with using following formulas:

           Probability of N(1,0)                         Pn1 = N1/(N1+N0) ≈ 0.5     ≈      Pn0 = N0/(N1+N0) ≈ 0.5
 1


                                                                                                         RND quality
0.5                                                                                                       estimation


                                                                                                           TIME
                                                  Time of measurements


                                                                18 / 27             September 19 2009
9. Methodology of measurement.

Basic conception:              Main idea consist in sequential changing the frequency of reference generator
                               for each delay chain, with goal to minimize dummy area – make it as less as
                               possible. This will decrease standard deviation of measurement.


 REFERENCE           Step 1: set REFCLK = 10 MHz              REFERENCE             Step 2: set REFCLK = 20 MHz
 FREQUENCY
                                                              FREQUENCY
 GENERATOR
                                                              GENERATOR



 Unit under test
                                                              Unit under test
  (delay chain)
                                                               (delay chain)




    Useful zone                                                    Useful zone
  (define rising &                                               (define rising &
    falling delay                          Dummy                                                    Dummy zone
                                                                   falling delay
         time)                              zone                                                      (better
                                                                        time)
                                         (Very large)                                               correlation)


   Sequentially increase reference clock frequency, until the moment, when dummy area become as small
       as possible. Using special algorithms and test chip modules it was carried out automatically.




                                                    19 / 27                     September 19 2009
10. Test data estimation.
Number of      Name of        Name of    Simulation      Test result             Test condition:
delay chain   delay chain      time     results (ps)   from chip (ps)
                                                                             Reference clock= 5MHz
                               Low      1003.202684         1040.0690
                NET           Falling    0.000000           0.118542
    1         (simple short
                 net for      Rising     0.000000           0.049185
               calibration)                                                  Difference between simulation
                               High     996.797316          959.7637         and test results explained by
                               Low      900.106756         933.5191363       difference in time of simulation
                                                                             on workstation and on-chip
                              Falling   101.875858         88.11493123
    2           AND                                                          measurements of test chip.
                                                                             Simulation time can’t cover all
                (AD2D4)       Rising     97.605612         106.1820897
                                                                             necessary time for calculation
                               High     900.411774         872.1838427       of delay time, it’s too big and
                                                                             speed of workstation is too
                               Low      938.233948         984.1565783
                                                                             slow for that. So:
                              Falling    64.053683         46.25940713
    3             NI                                                         1. Simulation time:
                 (NID4)       Rising     54.293122         55.60843068       Tsim = 0000_199Dh.
                               High     943.419247         913.9755839
                                                                             2. Real time for test:
                               Low      845.508617         888.3672173       Treal = FFFF_FFFF.
                              Falling   167.168980         153.650000
    4            IVT                                                         Tsim << Treal, so error between
                (IVTD4)       Rising    146.168980         148.180000        simulation result and test result
                               High     842.153424         806.9450533       can be big.



                                                 20 / 27                 September 19 2009
11. Interface of test chip.

 Lab View,                    Test board
 FPGA,
 PC,
               RESET            Test chip
 Etc…                           Delay chain
             REF CLOCK                                       Ref clock out

             Chip select
                                                               BONUS PIN
               Write                                        (optional - reserve)
                                                                  [09:00]

             AD [31:00]         Module of
                               measurement              More simple interface will
                                                                 provide:
         DATA [31:00]
                                                     1. Easy test of chip.
                                                     2. Compatibility between old
                                                     and new version of test chip
              UART IN                                (Not necessary make new
                               UART module           board and program for
             UART OUT                                capture data).
                                                     3. Flexible address module
                                                     allocation for each delay
                                                     chain.




                              21 / 27         September 19 2009
11. Interface of test chip.
      To get easy access for each module of test chip, we must design special
      design agreements for interface of test chip. It will let in future design new
      test chip without change of test board and communication program.

      New interface must include next pin (total available 144 pin) :

1.    RESET           :       1 pin
2.    Ref clock       :       1 pin
3.    Chip select     :       1 pin
4.    WRITE           :       1 pin
5.    ADDRES          :       31 down to 0 pins
6.    DATA            :       31 down to 0 pins
7.    Ref clock out   :       1 pin
8.    Uart in         :       1 pin
9.    Uart out        :       1 pin
10.   Bonus pin       :       10 pins
11.   Power pins      :       63 pins

TOTAL in use          : 144 pins (81 user pins + 63 power pins (VCC+GND))




                                              22 / 27             September 19 2009
11. Interface of test chip.

                 Memory address allocation for new test chip
         Number of delay chain       Name of delay chain      Memory address allocation
                   1                         AND                     1000_0000h
                   2                         OR                      1000_0004h
                   3                         XOR                     1000_0008h
                   4                        NAND                     1000_000Ch
                   5                        NOR                      1000_0010h
                   6                        XNOR                     1000_0014h
                   7                         BUF                     1000_0018h
                   8                         NOT                     1000_001Ch
                   9                       BUFIF1                    1000_0020h
                  10                       BUFIF0                    1000_0024h
                  11                       NOTIF1                    1000_0028h
                  12                       NOTIF0                    1000_002Ch

       * Because each measurement module have 4 counter, we should use each 4 address
       for 1 measurement module.



                                           23 / 27              September 19 2009
12. Conclusion.
We have presented an approach of on-chip delay measures based on random sampling. The proposed
approach is independent of the nature of the DUT, making it suitable for measuring the propagation delay
of any combinational path across a single cell, a complex combinational unit, or a single interconnect.
The distinguishing feature of our technique is the capability of measuring single-cell delays, thus enabling
the characterization of corner cases, without using high-performance test equipments.
Moreover, the compact implementation enables the integration of many DUTs on the same die.
A prototype test chip with an array of 32 DUTs has been realized in GL130SB (130nm Logic Process)
technology.




                                                  24 / 27                September 19 2009
12. Conclusion.

     Bonuses of using this idea:
•    Measurement of Single DUT propagation delay
•    Distinguish between raising and falling propagation delay’s
•    Measurement equipments can be placed as close as possible to the test structure, thus improving
     the signal to noise ratio.
•    Delay measures can be performed in the actual operating conditions.
•    Many test structures can be integrated on the same die.
•    A large number of measures can be simultaneously performed.
•    Only low-cost external instrumentation is required.




     Minus:
1.   Random sampling method for on-chip characterization require high accuracy in chip design.
2.   Time of simulation & test is too big. In real case is high probability, that external & internal condition
     will influent on schematic than more, than more test time. To decrease simulation and test time need
     apply special algorithms of calculation middle value of test.
3.   For achieved more accuracy result we need to improve design special module of observation &
     control, to decrease dummy zone of measurement (1 - > 1 & 0 - > 0) with using external (internal)
     reference clock.




                                                    25 / 27                September 19 2009
13. References.


1.   O. Coudert, “Timing and design closure in physical design flows,” in Proceedings of ISQED pp. 511-
     516, 2002.
2.   J. A. Davis, et al. "Interconnect Limits on Gigascale Integration (GSI) in the 21st Century," in
     Proceeding of IEEE vol. 89, no. 3, pp. 305- 324, 2001.
3.   B. E. Stine, E. Chang, D. S. Boning, and J. E. Chung, “Analysis and decomposition of spatial
     variation in integrated circuit processes and devices,” in IEEE Transactiona on Semiconductor
     Manufacture, vol. 10, pp.24-41, 1997.
4.   W. H. Kao, Chi-Yuan Lo, M. Basel, and R. Singh, “Parasitic extraction: current state of the art and
     future trends,” Proceeding of IEEE, vol. 89, no. 5, pp. 729-739, 2001.
5.   S. Maggioni, A. Veggetti, A. Bogliolo, L. Croce, “Random sampling for on-chip characterization of
     standard cell propagation delay”, in Proceedings of the Fourth International Symposium on Quality
     Electronic Design, 24-26 March 2003, pp. 41- 45.
6.   S. K. Thompson, Sampling, 2nd Edition, Wiley, 2002.




                                                 26 / 27               September 19 2009
THANK YOU FOR ATTENTION
P1. Ring oscillators module analyzing.

        Ring oscillator 1                       Test chip                     Ring oscillator 2


                                               Same condition:
                                          1.     Schematic.
                                          2.     Layout.
                                          3.     Process variation.
                                          4.     Noise.
                                          5.     Temperature.
      1024 IVD4 elements                  6.     Etc…                       1024 IVD4 elements



  IVD4 delay time = T/1024
                                               Ideal case for simulation


Simulation RO 1

Simulation RO 2



                             Phase error depend on: Δθ= f (1,2,3,4,5,6…)
                            Current ideal case: Θn = Θn-1 ±Δθ = const = 0


                                                 28 / 27              September 19 2009
P1. Ring oscillators module analyzing.
      Net list + SDF simulation result : Θn = Θn-1 ±(Δθerror layout ≠0); Fro1 ≈ Fro2;


NET+SDF RO 1

NET+SDF RO 2



                   Layout is not same for NET + SDF simulation.                                  Δθerror layout ≈ 662 ps
1.      Tro1 = 51696 ps => Fro1 = 19343856 Hz.
2.      Tro2 = 51034 ps => Fro2 = 19594779 Hz.                                                   Δθ(2,3,4,5,6) ≈ RND ps


      Real silicon simulation result : Θn = Θn-1 ±Δθerror layout ±Δθerror (1,3,4,5,6)              IVD4 delay ≈ 50 ps


     Real RO 1

     Real RO 2




     Δθerror layout                                                                              Δθerror (2,3,4,5,6)


                                                            29 / 27                     September 19 2009
P2. Phase error accumulation methodology.
The main idea consist in start both ring oscillator at same time and stop when value counter 2 not will be
equal value counter 1. To define this state we use comparator. Each enable signal of counter connect to
the comparator output. Because ring oscillator have different amount of elements – after some time
counter value1 and counter value 2 became not equal, and comparator will produce stop condition for
counter1,2,3. Counter 3 calculate time after start. With using value of counter3 we can obtain total time
between start and stop point and define propagation delay time in 2 last elements.



                                 Ring oscillator1 (odd elements)        Clock
                                                                                Counter 2   Out




                                                                                                       DATA multiplexer
                           Enable                                       Enable
                 Synchronizer




                                              Start / stop
                                                                          Comparator
REFCLK
                                           Enable
                                             Counter 1 Out
                                           clock

                           Enable                                       Enable
                                                                                Counter 3   Out
                                Ring oscillator2 (odd elements + 1)     clock




                                                              30 / 27              September 19 2009
P2. Phase error accumulation methodology.
               θerr=0                                                                      θerr=0
               (start)                                                                     (stop)
                                          Θn = Θn-1 ± (Δθelement ≠0)                                        Θn = Θn-1 ± (Δθelement ≠0);
                      P - period
Reference
  clock


RO1

RO2



 Start/stop


  Counter 1                01             02               03             04         …                          2000


  Counter 2                 01            02                 03            04          …                        1001

  Counter 3                  01                02                 03            04     …                        1000


                                                                                                          Stop of the measurement


T (time of measurement) = P * Ncounter3             Delay time = T / 2*(Ncounter2-1)                      Delay time = T / 2*Ncounter3




                                                                31 / 27                         September 19 2009
P2. Phase error accumulation methodology.
  Point of       Time of      Value of     Point of       Time of      Value of                      For example :
simulation 2   simulation 2   counter2   simulation 3   simulation 3   counter3        P – period                = 10 ns.
                                                                                       ΔD – delay in 1 element = 10 ns
     1              0            0            1              0            0            Ring oscillator 2         = 10 elements.
                                                                                       Ring oscillator 3         = 11 elements.
     2             200           1                                                     After finished calculation –
                                              2             220           1
                                                                                               ΔD = T simulation / 2*N3=
                                                                                        (P * Value counter1) /2*Value_counter3
     3             400           2
                                              3             440           2                              = 10 ns

     4             600           3
                                              4             660           3
     5             800           4
                                              5             880           4
     6            1000           5
                                              6             1100          5
     7            1200           6
                                              7             1320          6
     8            1400           7
                                              8             1540          7
     9            1600           8

    10            1800           9            9             1760          8

    11            2000          10           10             1980          9
                                                                                            Stop condition

    12            2200           11          11             2200         10
                                                                                         Next cycle of iteration
    13             Etc           …           12             2440          11



                                                        32 / 27                   September 19 2009