SEU Mitigation Techniques for Low-Power, High Speed Microprocessor

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					                Space Micro Inc.


SEU Mitigation Techniques for
  Low-Power, High Speed
      Microprocessor

                Author: David Czajkowski
                        dcz@spacemicro.com



D. Czajkowski                                Paper – P14
                              1
           SBC Performance = CPUs

• SBC sub-elements
                                                CPU
     • CPU
     • Memory                                  Bus                   Memory
                                               Controller
     • Communication ports
     • Special functions (ADCs, etc)
                                           COMM             COMM              ADC

• Most sub-elements “solvable”             Port 1           Port 2            Port 1


     • EDAC for Memory
     • TMR FPGAs & ASICs for communication
     • Handle special functions on case-by-case
• CPU problem not easily solvable
     • SEU ?    Power ?   Speed ?
D. Czajkowski                                                                   Paper – P14
                                                                                        P15
                                       2
        Commercial vs. Rad Hard Processors

                              High
                             Speed
 COTS performance:                   Less Speed
• 2,000-3,000 MIPS
• Poor SEU                                     RH performance:
                                              • 20-250 MIPS
                                              • Good SEU




                 Low                      SEU
                Power   More Power
  Result is RH is behind COTS 3 Generations
D. Czajkowski                                         Paper – P14
                                 3
                     RH/RT CPU Solutions

    RH Chips                                             RHBD Chips




   Proven RH technique                            Proven cells
   3-4 generations behind commercial              Can use COTS foundry
      250 MIPS is leading edge                       0.13/0.15 um processes
      0.25/0.35 um processes                      Severe reduction in speed compared
   SEU Tolerance Falling                           to COTS
      Foundry performance flat                       Adding gate delays
      Number of bits rising dramatically          Increase in power
                                                      Adding gates



    D. Czajkowski                                                           Paper – P14
                                            4
                    Triple Modular Redundancy
                            Architecture
 SEU proven mitigation technique  Applying on single CPU
 Hard to apply at system level     eliminates SEU value
    Synchronizing CPUs               If SEU hit during clock cycle,
    Triple (+1W) power consumption     all 3 may give wrong answer
    Larger boards, more traces
                        Software Instructions               Computer/Hardware

                  Instruction   Instruction   Instruction     CPU

                     C1             B1            A1           #1


                  Instruction   Instruction   Instruction
                                                              CPU
                     C2             B2            A2
                                                               #2

                  Instruction   Instruction   Instruction
                                                              CPU
                     C3             B3            A3
                                                               #3


          Time:    T=3            T=2         T=1
                                                                     Voter

D. Czajkowski                                                                   Paper – P14
                                                       5
           Time Redundancy Architecture

 SEU proven mitigation technique                               SEU problem
 Slows performance substantially                                  If SEU hit, logic section may
    3-4X speed reduction                                           continue to give wrong
    3-4X power per instruction                                     answer on 2nd/3rd cycle
                                                                   What if ALU perform + vs - ?
                        Compare    Instruction   Instruction     Instruction    Single
                        A1-A2-A3       A3            A2              A1          CPU



                Time:   T=4         T=3           T=2              T=1

                                                                                Computer
                        Compare    Instruction   Instruction     Instruction
                                                                                Hardware
                        B1-B2-B3       B3            B2              B1



                Time:    T=8         T=7           T=6             T=5


                        Compare    Instruction   Instruction     Instruction
                                                                                 Software
                        C1-C2-C3       C3            C2              C1        Instructions


                Time:    T = 12      T = 11        T = 10          T=9

D. Czajkowski                                                                                 Paper – P14
                                                     6
                                                        CPU Architectures

                 RISC                                           Superscalar                                                          VLIW

                                                                                                     Control                                             Control
                                                                           MMU          Cache                                MMU         Cache
                  MMU          Cache                                                                  Logic                                               Logic
                                                         Parallel
Clock                                        Control      Issue
Control                                       Logic      Control                     Multiplier                                        Multiplier
                                                           Unit           32-bit                     Clock                  32-bit                       Clock
                                                                                       #1                                                #1
                    32-                                                  ALU #1                      Control               ALU #1                        Control
                             Multiplier
                     bit
                    ALU                                                ALU #2       Mult #2                            ALU #2         Mult #2

                    Bus InterfaceUnit
                                                                            Bus InterfaceUnit                                        Bus InterfaceUnit


     UART                PCI              Parallel IO
                       Controller         Controller            UART              PCI             Parallel IO         UART                PCI               Parallel IO
                                                                                Controller        Controller                            Controller          Controller




          Pinstruction = Pcore + Pperipherals                Pinstruction = Pcore + Pperipherals + Pparallel               Pinstruction = Pcore + Pperipherals
                                                                                   Number of Instructions                                Number of Instructions

                                                                                                                Software
                                                                                                                 Issue
                                                                                                                Compiler




             D. Czajkowski                                                                                                                           Paper – P14
                                                                                             7
                   Introducing TTMR™ Technology

              Time-Triple Modular Redundancy Architecture
                                                                               VLIW CPU
                   Software Instructions                                       Hardware


                                                                  32-bit
        Compare         Instruction   Instruction   Instruction            Multiplier       MMU          Cache
                                                                   ALU
                                                                             #1
                                                                    #1
        C1-C2-C3            B3           C2               A1

        Compare         Instruction   Instruction   Instruction   32-bit                   Clock          Control
                                                                           Multiplier
                                                                   ALU                    Control          Logic
                                                                             #2
        B1-B2-B3           C3             A2              B1        #2

                                                                                             Bus InterfaceUnit
                                                                  32-bit
        Compare         Instruction   Instruction   Instruction            Multiplier
                                                                   ALU
                                                                             #3
        A1-A2-A3            A3            B2              C1        #3
                                                                                          PCI             Parallel IO
                                                                                        Controller        Controller




Time:   T=4                T=3        T=2            T=1
        D. Czajkowski                                                                           Paper – P14
                                                      8
                    Improved TTMR Algorithm

   Not                 Software                  Inst A1    ALU #1
Required             Instructions                                    VLIW CPU
99.9% of                               Inst A2              ALU #2
  Time
                               COMP
                                                            Branch
                               A1-A2
                                                              #1
                     Inst A3
                                                            ALU #3

             COMP                                           Branch
             A1-A2                                            #2

   Time
             T=5       T=4      T=3       T=2         T=1
         • Repeat 2 Instructions 100% of Time
         • Compare A1-A2 100% with “Free” Branch
         • When NO Match, complete Inst A3 and
         additional compare
    D. Czajkowski                                                       Paper – P14
                                                  9
                     TTMR Experiment Layout
                  Texas Instruments VLIW 320C6201 chip

•Limited by TI
DSP
architecture             Z                        X
•Induce known
                       Multiply               Multiply
data error in X                   Open
                       A1 x A2                A1 x A2
•Verify Compare
gives Y-Z
answer

                                    Y
           Compare                Multiply
                       Open                  Open
             X-Y-Z                A1 x A2


                  Software Instructions

     Time: T = 4       T=3        T=2             T=1
     D. Czajkowski                                       Paper – P14
                                             10
                       TTMR Simulation Results

                       Simulation of TTMR Complete!
INIT REG    ASSIGN A    ASSIGN B    SEU BIT ERROR            MULTIPLY A x B                ERROR DECTECT
            VALUES      VALUES




               A= 5                B = 10           Error            A x B = 50             Compare
                                                                                            Value = 010;
                                                    B’ = 1                    A x B’ = 5    50 = answer

                   Next Step: SEU Radiation Test
      D. Czajkowski                                                                         Paper – P14
                                                        11
       TTMR System is Hardware & Software

                                                               VLIW Chip



                TTMR
                Assembly
                Routines


                              Takes advantage of VLIW parallel opportunities
                              SEU error rate expected to be equal to TMR
                              Software controllable
                              Selectable performance
                                  High speed worse SEU rate
                                  50% speed better SEU rate
          Software            SEFI is NOT fixed with TTMR

D. Czajkowski                                                     Paper – P14
                                    12
             Solving other Radiation Issues

 Total Dose solved by COTS fab selection
     TSMC 0.13, 0.15 um expected >100 krad
     MEC 0.6, 0.25 um 95 krad
 SEL solved by COTS fab selection
     TSMC 0.13, 0.15 um expected no SEL
     MEC 0.6, 0.25 um no SEL
                                                     CPU              Timer Signal



 SEFI Solved with SEFI
                                          Bus              Watchdog
                                                                      Memory
  Watchdog Controller                   Controller          Timer


 Special TTMR hardware
                                     COMM                  COMM          ADC
  used for buses                     Port 1                Port 2        Port 1




 D. Czajkowski                                                         Paper – P14
                               13
                                 Instruction Type   TTMR Rules   TTMR Algorithm


   TTMR Software
    Development
    Environment

 Industry standard software
  tools, modified to include:
    Additional TTMR library
    TTMR Pre-Compiler
 Produces TTMR code from
  standard C-code




    D. Czajkowski                                                      Paper – P14
                                14
        C to Mirrored C Pre Processor

 Goal
       Convert standard C to a series of Mirrored C Operations
       No programmer intervention.
       Diagnostics so that converted code will compile cleanly
       Generated code is “recognizable” by the programmer
 Tasks
       Design infrastructure
       C Language
            Generate C Language Parser with pass through of #include and
             Comment statements
            Method Declaration Processing (Local/Global Sections)




D. Czajkowski                                                               Paper – P14
                                           15
                          TTMR Library Status
      Variable Declarations                        Equation Evaluation
     Declarations (static, linked, values,        C math/logic Operations
      expression initialization)                    Precedence and TTMR generation
           Integer                                     Integer
           Integer Constants                           Integer Constants
           Integer Array                               Integer Array
           Integer Pointer                             Integer Pointer
           Integer Pointer Array                       Integer Pointer Array
           Char                                        Char
           Char Constants                              Char Constants
           Char Array                                  Char Array
           Char Pointer                                Char Pointer
           Char Pointer Array                          Char Pointer Array
           Float/Double                                Float/Double
           Double Consants                             Double Constants
           Float/double Array                          Float/double Array
           Float/double pointer                        Float/double pointer
           Float/double pointer array                  Float/double pointer array

                                                   Blue = Complete
    D. Czajkowski                                                                     Paper – P14
                                              16   Red = In Proguress
           TTMR Library Status – cont.
         Task - Loops                     Methods/Structs

 for                            Declaration conversion
       simple (integer only)            simple (integer only)
       complex                          complex

 while                          Structs – need to be designed.
       Simple (integer only)
       complex


 do while
       Simple (integer only)
       Complex


                                      Blue = Complete
D. Czajkowski                                                     Paper – P14
                                 17   Red = In Proguress
               TTMR Pre-Compiler is Operational
     Original C-Code                  TTMR C-Code
for(ixx=0; ixx<=nx; ixx++)             seuSET(ixx, _seucons_0);
 {                           __seulab__0:
*pv_Out = *pv_x >> ishift;             seuGT(__seuvar__0,ixx,nx);
pv_Out += 1;                           seuEQU(__seuvar__1,__seuvar__0 );
 }                                     if( seuVALIDATE( __seuvar__1 ) )
                                       {
                                           goto __seulab__1;
                                       }
                                       {
                                           seuVALUE(__seuvar__0, pv_x);
                                           seubSHR(__seuvar__1, __seuvar__0, ishift);
                                           seuDerefAssign(pv_Out, __seuvar__1);
                                           seuASSIGN_ADD(pv_Out, _seucons_1);
                                           seuINCV(ixx, ixx);
                                           goto __seulab__0;
                                       }
                             __seulab__1:

       D. Czajkowski                                                         Paper – P14
                                      18
                Proton100k Processors
      Equator BSP-15:            TI 320C6415 DSP:
     • 2,400 MIPS               • 5,760 MIPS
     • 4.9 W @ 400MHz           • 1.7 W @ 720MHz
     • 0.15um TSMC              • 0.12um TI fab




D. Czajkowski                               Paper – P14
                         19
       BSP-15 Based Proton100k In Progress

                                                                                            Current
                            Voltage Regulators                                              Montor              DEVICE POWER
                                                      VCC / VSS   FUSES
                          (5V -> 3.3V, 2.3V, 1.35V)                                        Jumpers



 Rad Test Board Design                                                                 RAD-TEST LOGIC
                                                                                                                                                    TEST
                                                                                                                                                   CABLE


  in PCB Layout                                                                                                                                    (RJ-45)




                                                                                                 INT SIGNALS
 Same design as
                                                                                                                                                   EEPROM




                                                      SDRAM

  Engineering Model                                                                     BSP-15 CPU                                    IIC    87LPC764uC      RS-232




                                                                          INT SIGNALS
                                                      FLASH



 Rad Testing             RJ-25                       Ethernet
                                                                                                                                            External
                                                                                                                                             OSC/
                                                                                                                                              PLL




    SEL-Sept 03




                                                                                                                 PCI signals




                                                                                                                               TRST
                                                                                                                                            JTAG


    TTMR SEU-Oct 03
                                                                                                               LATCHS




    TID-Oct 03                                                                                                ACTEL FPGA                                       Parallel
                                                                                                                                                                Delays




 Eng Model Est. Jan 04                                                                     TEST SIGNAL I/O (32-PIN) x3




 D. Czajkowski                                                                                                                                  Paper – P14
                                        20
                320C6415 Based Proton200k In
                         Progress

 First Step: SEL Testing
 Rad Test Board Design in
  PCB Layout
 Proceed pending SEL
  results




D. Czajkowski                                  Paper – P14
                             21
          Proton100k Expected Performance

    2,400 MIPS, 64 bits @400 MHz
    >1,440 MIPS SEU corrected
    SEU < 1E-5 uncorrected errors/day
    SEFI 1E-2 corrected resets/day
    No SEL
    Total Dose > 100 krad
    4.9 W CPU, 8W total power
    1 Gbyte/s 64 bit DMA bus
    PCI, I2C, parallel buses
    3U cPCI form factor
    VxWorks and Linux OS s/w
    D. Czajkowski                        Paper – P14
                                22
          Proton Performance Comparison

             Proton200k
             2,850 MIPS
               2 watts
MIPS
                 Proton100k                TMR Boards
                 1,440 MIPS                 1,400 MIPS
                   5 watts                   27 watts
                        RH ICs
                       240 MIPS    Best COTS
                        8 watts     54 MIPS
         0                          10 watts
                   CPU Power Consumption
 D. Czajkowski                                  Paper – P14
                              23
      Proton100k Projected Performance
SEU Rate                        SBC MIPS vs SEU Rate
 1E-8                    TMR SBCs


 1E-6
         Upset/day




 1E-4                 RH      Proton100k             Proton200k
                                 SBC                    SBC
                     SBCs

 1E-2                       Time Redund. SBC-ARGOS Data

 1E-0                                      Commercial SBCs

                     0         2000               4000              6000
                                           MIPS
D. Czajkowski                                                     Paper – P14
                                           24
                    Proton100k Status


 Basic TTMR Demonstration Completed Sept. 2002
 BSP-15 based Proto Board Design Completed
        In PCB Layout
 TTMR Code Running on Equator BSP-15 Board
 TTMR Software Development Tools Operating
        TTMR C-Code Libraries
        TTMR Pre-Compiler
 Proton100k Engineering Model Design in Progress
 Radiation Testing Scheduled for Sept/Oct 2003

D. Czajkowski                                  Paper – P14
                                 25
                Ultra Low-Power Computer
                         Summary

 VLIW microprocessors offer solutions for SEU
 Developed a New SEU Mitigation Technique:
        Time-Triple Modular Redundancy (TTMR)
 Selection of fab process can aid other radiation factors
 Lab Demo/Simulation of TTMR was Completed
 Space Micro believes >1,400 MIPS, low power (5 watt
  CPU) and good SEU (1E-5) are easily achievable
 AFRL/NASA funding in place to demonstrate & test
 Side Note: TTMR improvements: Patent Pending
 Thank You

D. Czajkowski                                       Paper – P14
                                 26