Baud Rate Generator

Document Sample
Baud Rate Generator Powered By Docstoc
					LAB – 3                                                  UART Baud Rate Generator Circuit Design




Baud Rate Generator
The transmission of serial data between two devices requires co-ordination by
both the transmitter and the receiver. The receiver must be synchronized to
the received bits and to the agreed transmission rate. Therefore, serial data
requires precise timing of the information bits such as the duration of a single
bit. This duration also determines the transmission rate of the serial channel.

A baud rate generator is a programmable, bit timing device that is used to
synchronize the bit duration for both the receive and transmit sections of a
serial communication device such as a Universal Asynchronous
Receiver/Transmitter (UART). Typically the receiver baud pulse is 8 or 16
times that of the transmitter pulse and will be down converted by the receiver
circuit. Figure 0-1 illustrates the function of the baud rate generator. In our
example, the bit clock rate, CLK, is 14.7456MHz.


                CLK
                                                                   B_CLK
            RESET_N                 Baud Rate
                                    Generator
           BAUD_SEL                                                B16_CLK



            CLK
                               16 pulses per bit Transmission
          B16_CLK                                                            1 CLK cycle

                                    1 bit Transmission time
           B_CLK                e.g. 1200 Baud : T=1/1200= 833µs             1 CLK cycle


                        Figure 0-1 Baud Rate Generator

The baud rate generator can be programmed via the BAUD_SEL signals to any
supported baud rates.

For this exercise the following entity definition is given:

Entity of Baud Rate Generator:
entity BAUD_GEN is
     port(CLK             :   In    std_logic;
          RESET_N         :   In    std_logic;
          BAUD_SEL        :   In    std_logic_vector(2 downto 0);
          B_CLK           :   Out   std_logic;
          B16_CLK         :   Out   std_logic);
end BAUD_GEN;




                                           Page 1
LAB – 3                                       UART Baud Rate Generator Circuit Design


The targeted baud rate generator shall support the following baud rates
according to the baud select (BAUD_SEL) lines as given in table below.
                          Table 1 Baud Rate Select
                BAUD_SEL                  Baud Rate
                   000                300 bits per second
                   001               1200 bits per second
                   010               4800 bits per second
                   011               9600 bits per second
                   100              19200 bits per second
                   101              38400 bits per second
                   110              57600 bits per second
                   111              115200 bits per second


a) Design a baud rate generator according to the above given specification
   using VHDL.

b) Write a test bench for the baud rate generator circuit to verify your design.

c) Simulate your design using ModelTech simulator.

d) Synthesis your design using Synplicity synthesis tool.




                                     Page 2
LAB – 3            UART Baud Rate Generator Circuit Design


          Notes:




          Page 3